From patchwork Mon Sep 4 08:43:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Morten_Br=C3=B8rup?= X-Patchwork-Id: 131145 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7CC4424EE; Mon, 4 Sep 2023 10:43:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8AE1D402AF; Mon, 4 Sep 2023 10:43:56 +0200 (CEST) Received: from dkmailrelay1.smartsharesystems.com (smartserver.smartsharesystems.com [77.243.40.215]) by mails.dpdk.org (Postfix) with ESMTP id E36D0400EF for ; Mon, 4 Sep 2023 10:43:54 +0200 (CEST) Received: from smartserver.smartsharesystems.com (smartserver.smartsharesys.local [192.168.4.10]) by dkmailrelay1.smartsharesystems.com (Postfix) with ESMTP id A50912089E; Mon, 4 Sep 2023 10:43:54 +0200 (CEST) Received: from dkrd2.smartsharesys.local ([192.168.4.12]) by smartserver.smartsharesystems.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 4 Sep 2023 10:43:53 +0200 From: =?utf-8?q?Morten_Br=C3=B8rup?= To: thomas@monjalon.net, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, konstantin.v.ananyev@yandex.ru, bruce.richardson@intel.com, mattias.ronnblom@ericsson.com Cc: olivier.matz@6wind.com, andrew.rybchenko@oktetlabs.ru, dev@dpdk.org, =?utf-8?q?Morten_Br=C3=B8rup?= Subject: [PATCH] clarify purpose of empty cache lines Date: Mon, 4 Sep 2023 10:43:49 +0200 Message-Id: <20230904084349.12044-1-mb@smartsharesystems.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-OriginalArrivalTime: 04 Sep 2023 08:43:53.0438 (UTC) FILETIME=[EF2B7FE0:01D9DF0B] X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch introduces the generic RTE_CACHE_GUARD macro into the EAL, and replaces vaguely described empty cache lines in the rte_ring structure with this macro. Although the implementation of the rte_ring structure assumes that the hardware speculatively prefetches 1 cache line, this number can be changed at build time by modifying RTE_CACHE_GUARD_LINES in rte_config.h. The background and the RFC was discussed in this thread: http://inbox.dpdk.org/dev/98CBD80474FA8B44BF855DF32C47DC35D87B39@smartserver.smartshare.dk/ Signed-off-by: Morten Brørup Acked-by: Bruce Richardson Acked-by: Mattias Rönnblom --- config/rte_config.h | 1 + lib/eal/include/rte_common.h | 13 +++++++++++++ lib/ring/rte_ring_core.h | 6 +++--- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/config/rte_config.h b/config/rte_config.h index 400e44e3cf..cfdf787724 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -37,6 +37,7 @@ #define RTE_MAX_TAILQ 32 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO #define RTE_MAX_VFIO_CONTAINERS 64 +#define RTE_CACHE_GUARD_LINES 1 /* bsd module defines */ #define RTE_CONTIGMEM_MAX_NUM_BUFS 64 diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h index 771c70f2c8..daf1866a32 100644 --- a/lib/eal/include/rte_common.h +++ b/lib/eal/include/rte_common.h @@ -527,6 +527,19 @@ rte_is_aligned(const void * const __rte_restrict ptr, const unsigned int align) /** Force minimum cache line alignment. */ #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) +#define _RTE_CACHE_GUARD_HELPER2(unique) \ + char cache_guard_ ## unique[RTE_CACHE_LINE_SIZE * RTE_CACHE_GUARD_LINES] \ + __rte_cache_aligned +#define _RTE_CACHE_GUARD_HELPER1(unique) _RTE_CACHE_GUARD_HELPER2(unique) +/** + * Empty cache lines, to guard against false sharing-like effects + * on systems with a next-N-lines hardware prefetcher. + * + * Use as spacing between data accessed by different lcores, + * to prevent cache thrashing on hardware with speculative prefetching. + */ +#define RTE_CACHE_GUARD _RTE_CACHE_GUARD_HELPER1(__COUNTER__) + /*********** PA/IOVA type definitions ********/ /** Physical address */ diff --git a/lib/ring/rte_ring_core.h b/lib/ring/rte_ring_core.h index d1e59bf9ad..327fdcf28f 100644 --- a/lib/ring/rte_ring_core.h +++ b/lib/ring/rte_ring_core.h @@ -126,7 +126,7 @@ struct rte_ring { uint32_t mask; /**< Mask (size-1) of ring. */ uint32_t capacity; /**< Usable size of ring */ - char pad0 __rte_cache_aligned; /**< empty cache line */ + RTE_CACHE_GUARD; /** Ring producer status. */ union { @@ -135,7 +135,7 @@ struct rte_ring { struct rte_ring_rts_headtail rts_prod; } __rte_cache_aligned; - char pad1 __rte_cache_aligned; /**< empty cache line */ + RTE_CACHE_GUARD; /** Ring consumer status. */ union { @@ -144,7 +144,7 @@ struct rte_ring { struct rte_ring_rts_headtail rts_cons; } __rte_cache_aligned; - char pad2 __rte_cache_aligned; /**< empty cache line */ + RTE_CACHE_GUARD; }; #define RING_F_SP_ENQ 0x0001 /**< The default enqueue is "single-producer". */