From patchwork Wed Aug 9 01:32:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129995 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE18743011; Wed, 9 Aug 2023 03:33:30 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0401743249; Wed, 9 Aug 2023 03:33:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 4CCA8410FD for ; Wed, 9 Aug 2023 03:33:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544805; x=1723080805; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PTwTG0wZt6IDuPmliuZ0QueNFgK8Ha7b1bg1O21nbjs=; b=g1S+rk7oJYwUhJFjEzOvwr6Zpbfx66alYrtY6rJ3qqacE819fKPeEYYf dHuRXb3cb3Jv/g9YS2tEuIcZoVPqWwpQedRbdumgZcdaQDlnH/BBP+uPl PVesQddU5Us3K1Vgz6Zt/Ysg+aB2qTlh82Nbc7g4X+pSB9mRqtj0QinsD o9axgGNmXo/OVtydT9VHmTXdo9AM9YGdWAi+00yVeG6TdEl/LesHV/jFd XgJBnWNZdCkC2LnIpPGymXK7zGoP7QAcpjHWMmINI8KBa+A2sY/hn6IJC 7zn1iJDK0wHCcLHeOjxj2jrMcBcloVZGqEwfZffhkoa4cYSlEVHO4qV4m w==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704454" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704454" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735046" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735046" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:21 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Zhenning Xiao , Jayaprakash Shanmugam Subject: [PATCH 01/14] common/idpf/base: enable support for physical port stats Date: Wed, 9 Aug 2023 01:32:55 +0000 Message-Id: <20230809013308.1449103-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Add support to indicate physical port representor and query its statistics. Signed-off-by: Zhenning Xiao Signed-off-by: Jayaprakash Shanmugam Signed-off-by: Simei Su --- .mailmap | 2 + drivers/common/idpf/base/virtchnl2.h | 80 +++++++++++++++++++++++++++- 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index 864d33ee46..8f90e6f972 100644 --- a/.mailmap +++ b/.mailmap @@ -1638,3 +1638,5 @@ Ziye Yang Zoltan Kiss Zorik Machulsky Zyta Szpak +Jayaprakash Shanmugam +Zhenning Xiao diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 594bc26b8c..cd47444835 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -97,6 +97,7 @@ #define VIRTCHNL2_OP_CONFIG_PROMISCUOUS_MODE 537 #define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 #define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 +#define VIRTCHNL2_OP_GET_PORT_STATS 540 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -582,6 +583,9 @@ struct virtchnl2_queue_reg_chunks { VIRTCHNL2_CHECK_STRUCT_LEN(40, virtchnl2_queue_reg_chunks); +/* VIRTCHNL2_VPORT_FLAGS */ +#define VIRTCHNL2_VPORT_UPLINK_PORT BIT(0) + #define VIRTCHNL2_ETH_LENGTH_OF_ADDRESS 6 /* VIRTCHNL2_OP_CREATE_VPORT @@ -620,7 +624,8 @@ struct virtchnl2_create_vport { __le16 max_mtu; __le32 vport_id; u8 default_mac_addr[VIRTCHNL2_ETH_LENGTH_OF_ADDRESS]; - __le16 pad; + /* see VIRTCHNL2_VPORT_FLAGS definitions */ + __le16 vport_flags; /* see VIRTCHNL2_RX_DESC_IDS definitions */ __le64 rx_desc_ids; /* see VIRTCHNL2_TX_DESC_IDS definitions */ @@ -1159,6 +1164,74 @@ struct virtchnl2_vport_stats { VIRTCHNL2_CHECK_STRUCT_LEN(128, virtchnl2_vport_stats); +/* physical port statistics */ +struct virtchnl2_phy_port_stats { + __le64 rx_bytes; + __le64 rx_unicast_pkts; + __le64 rx_multicast_pkts; + __le64 rx_broadcast_pkts; + __le64 rx_size_64_pkts; + __le64 rx_size_127_pkts; + __le64 rx_size_255_pkts; + __le64 rx_size_511_pkts; + __le64 rx_size_1023_pkts; + __le64 rx_size_1518_pkts; + __le64 rx_size_jumbo_pkts; + __le64 rx_xon_events; + __le64 rx_xoff_events; + __le64 rx_undersized_pkts; + __le64 rx_fragmented_pkts; + __le64 rx_oversized_pkts; + __le64 rx_jabber_pkts; + __le64 rx_csum_errors; + __le64 rx_length_errors; + __le64 rx_dropped_pkts; + __le64 rx_crc_errors; + /* Frames with length < 64 and a bad CRC */ + __le64 rx_runt_errors; + __le64 rx_illegal_bytes; + __le64 rx_total_pkts; + u8 rx_reserved[128]; + + __le64 tx_bytes; + __le64 tx_unicast_pkts; + __le64 tx_multicast_pkts; + __le64 tx_broadcast_pkts; + __le64 tx_errors; + __le64 tx_timeout_events; + __le64 tx_size_64_pkts; + __le64 tx_size_127_pkts; + __le64 tx_size_255_pkts; + __le64 tx_size_511_pkts; + __le64 tx_size_1023_pkts; + __le64 tx_size_1518_pkts; + __le64 tx_size_jumbo_pkts; + __le64 tx_xon_events; + __le64 tx_xoff_events; + __le64 tx_dropped_link_down_pkts; + __le64 tx_total_pkts; + u8 tx_reserved[128]; + __le64 mac_local_faults; + __le64 mac_remote_faults; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(600, virtchnl2_phy_port_stats); + +/* VIRTCHNL2_OP_GET_PORT_STATS + * PF/VF sends this message to CP to get the updated stats by specifying the + * vport_id. CP responds with stats in struct virtchnl2_port_stats that + * includes both physical port as well as vport statistics. + */ +struct virtchnl2_port_stats { + __le32 vport_id; + u8 pad[4]; + + struct virtchnl2_phy_port_stats phy_port_stats; + struct virtchnl2_vport_stats virt_port_stats; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(736, virtchnl2_port_stats); + /* VIRTCHNL2_OP_EVENT * CP sends this message to inform the PF/VF driver of events that may affect * it. No direct response is expected from the driver, though it may generate @@ -1384,6 +1457,8 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; + case VIRTCHNL2_OP_GET_PORT_STATS: + return "VIRTCHNL2_OP_GET_PORT_STATS"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1648,6 +1723,9 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 case VIRTCHNL2_OP_GET_STATS: valid_len = sizeof(struct virtchnl2_vport_stats); break; + case VIRTCHNL2_OP_GET_PORT_STATS: + valid_len = sizeof(struct virtchnl2_port_stats); + break; case VIRTCHNL2_OP_RESET_VF: break; /* These are always errors coming from the VF. */ From patchwork Wed Aug 9 01:32:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129996 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0DF1943011; Wed, 9 Aug 2023 03:33:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D75C40DFB; Wed, 9 Aug 2023 03:33:30 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id EA09443255 for ; Wed, 9 Aug 2023 03:33:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544808; x=1723080808; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w7uVDmUs2fQ6n9rqqilVIfEF27NzZRJNRwiCAPk2wJg=; b=Cuhgur6gO6I/8q4VYy7GDoDUO56k+ri4/4A/uhHzD5EnIusfBh85J9MH y3cecVhpBcUzVNr9AIl8T61OpcsktzJCFv5t2ez+Mb8UCOVmj1GZMGCZh 5TwdS+o3veEEN9vcslwLUA95D9p6lUa/ZfIZ/C0+YyZB+2SninNQ/DKN/ I6BnRrIodhCTa1OGVZMVnaIDz3NJC969Kq5VoZXNhaWU17pedpfVtwwAq 44uCDLo4b33rfim44SL+heOlUtgrz2BeZyiyuD3ldSZgQkgOwQ7Xy7pHE qQa4Dye2TNDpzbj/JaFCVJ4dPYm6xItqoLiek/Osy5gOtoFkWzkGWlqOa g==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704461" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704461" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735055" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735055" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:25 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Josh Hay Subject: [PATCH 02/14] common/idpf/base: add miss completion capabilities Date: Wed, 9 Aug 2023 01:32:56 +0000 Message-Id: <20230809013308.1449103-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Add miss completion tag to other capabilities list, to indicate support for detecting a miss completion based on the upper bit of the completion tag. Signed-off-by: Josh Hay Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/virtchnl2.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/.mailmap b/.mailmap index 8f90e6f972..af452d54c6 100644 --- a/.mailmap +++ b/.mailmap @@ -1640,3 +1640,4 @@ Zorik Machulsky Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao +Josh Hay diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index cd47444835..c49e4b943c 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -231,6 +231,10 @@ #define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) #define VIRTCHNL2_CAP_PTYPE BIT(18) #define VIRTCHNL2_CAP_LOOPBACK BIT(19) +/* Enable miss completion types plus ability to detect a miss completion if a + * reserved bit is set in a standared completion's tag. + */ +#define VIRTCHNL2_CAP_MISS_COMPL_TAG BIT(20) /* this must be the last capability */ #define VIRTCHNL2_CAP_OEM BIT(63) From patchwork Wed Aug 9 01:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129997 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6A7343011; Wed, 9 Aug 2023 03:33:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48E64410FD; Wed, 9 Aug 2023 03:33:33 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 9302D43255 for ; Wed, 9 Aug 2023 03:33:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544810; x=1723080810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6EdDKPGNlIlhL7Q+OOODX7tyuiw8nTCWKBlwT/w94KM=; b=LDIdjIxhJZcO6LvRsOtsZbl063fPlaNEDIWGDzx0dcehpz6IlkO0i/vU vkXDImXJ8db1FZ9bGne+CwuEkL1GeAVECWAaOmaj6prFzB6+G+7w+OIL6 YLfqBuzKHNyHlNUbra+aABxzwHq4ahrYpVS/DWRFrAJAlQXaIxiaZQcYx X3Z6/ub4Stg9LadX4rKeRB/Uko0PKzTmVPggI6ogCHT/hxX/Shn+9tjOA CCnUIsPGfkx6OXyfTUWJqWJo/4GGsBwc3GaSchT87vD+7uOCHDQOB5J7J pfXd7pj7FQVp7TXg56F3oM8BoaH2cuRiASNKTAa1AzrDWtma/Ejz/v2cx A==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704463" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704463" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735065" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735065" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:27 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Milena Olech Subject: [PATCH 03/14] common/idpf/base: initial PTP support Date: Wed, 9 Aug 2023 01:32:57 +0000 Message-Id: <20230809013308.1449103-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Adding a few PTP capabilities to determine which PTP features are enabled - legacy cross time, ptm, device clock control, PTP Tx timestamp with direct registers access, PTP Tx timestamp using virtchnl messages. Creating structures and opcodes to support feautres introduced by capabilities. Signed-off-by: Milena Olech Signed-off-by: Simei Su --- drivers/common/idpf/base/virtchnl2.h | 145 +++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index c49e4b943c..320430df6f 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -98,6 +98,9 @@ #define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 #define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 #define VIRTCHNL2_OP_GET_PORT_STATS 540 + /* TimeSync opcodes */ +#define VIRTCHNL2_OP_GET_PTP_CAPS 541 +#define VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES 542 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -1395,6 +1398,112 @@ struct virtchnl2_promisc_info { VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_promisc_info); +/* VIRTCHNL2_PTP_CAPS + * PTP capabilities + */ +#define VIRTCHNL2_PTP_CAP_LEGACY_CROSS_TIME BIT(0) +#define VIRTCHNL2_PTP_CAP_PTM BIT(1) +#define VIRTCHNL2_PTP_CAP_DEVICE_CLOCK_CONTROL BIT(2) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_DIRECT BIT(3) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_VIRTCHNL BIT(4) + +/* Legacy cross time registers offsets */ +struct virtchnl2_ptp_legacy_cross_time_reg { + __le32 shadow_time_0; + __le32 shadow_time_l; + __le32 shadow_time_h; + __le32 cmd_sync; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_legacy_cross_time_reg); + +/* PTM cross time registers offsets */ +struct virtchnl2_ptp_ptm_cross_time_reg { + __le32 art_l; + __le32 art_h; + __le32 cmd_sync; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_ptm_cross_time_reg); + +/* Registers needed to control the main clock */ +struct virtchnl2_ptp_device_clock_control { + __le32 cmd; + __le32 incval_l; + __le32 incval_h; + __le32 shadj_l; + __le32 shadj_h; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_device_clock_control); + +/* Structure that defines tx tstamp entry - index and register offset */ +struct virtchnl2_ptp_tx_tstamp_entry { + __le32 tx_latch_register_base; + __le32 tx_latch_register_offset; + u8 index; + u8 pad[7]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_entry); + +/* Structure that defines tx tstamp entries - total number of latches + * and the array of entries. + */ +struct virtchnl2_ptp_tx_tstamp { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_entry ptp_tx_tstamp_entries[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp); + +/* VIRTCHNL2_OP_GET_PTP_CAPS + * PV/VF sends this message to negotiate PTP capabilities. CP updates bitmap + * with supported features and fulfills appropriate structures. + */ +struct virtchnl2_get_ptp_caps { + /* PTP capability bitmap */ + /* see VIRTCHNL2_PTP_CAPS definitions */ + __le32 ptp_caps; + u8 pad[4]; + + struct virtchnl2_ptp_legacy_cross_time_reg legacy_cross_time_reg; + struct virtchnl2_ptp_ptm_cross_time_reg ptm_cross_time_reg; + struct virtchnl2_ptp_device_clock_control device_clock_control; + struct virtchnl2_ptp_tx_tstamp tx_tstamp; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(88, virtchnl2_get_ptp_caps); + +/* Structure that describes tx tstamp values, index and validity */ +struct virtchnl2_ptp_tx_tstamp_latch { + __le32 tstamp_h; + __le32 tstamp_l; + u8 index; + u8 valid; + u8 pad[6]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_latch); + +/* VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES + * PF/VF sends this message to receive a specified number of timestamps + * entries. + */ +struct virtchnl2_ptp_tx_tstamp_latches { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_latch tstamp_latches[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp_latches); static inline const char *virtchnl2_op_str(__le32 v_opcode) { @@ -1463,6 +1572,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; case VIRTCHNL2_OP_GET_PORT_STATS: return "VIRTCHNL2_OP_GET_PORT_STATS"; + case VIRTCHNL2_OP_GET_PTP_CAPS: + return "VIRTCHNL2_OP_GET_PTP_CAPS"; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + return "VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1732,6 +1845,38 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 break; case VIRTCHNL2_OP_RESET_VF: break; + case VIRTCHNL2_OP_GET_PTP_CAPS: + valid_len = sizeof(struct virtchnl2_get_ptp_caps); + + if (msglen >= valid_len) { + struct virtchnl2_get_ptp_caps *ptp_caps = + (struct virtchnl2_get_ptp_caps *)msg; + + if (ptp_caps->tx_tstamp.num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((ptp_caps->tx_tstamp.num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_entry)); + } + break; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + valid_len = sizeof(struct virtchnl2_ptp_tx_tstamp_latches); + + if (msglen >= valid_len) { + struct virtchnl2_ptp_tx_tstamp_latches *tx_tstamp_latches = + (struct virtchnl2_ptp_tx_tstamp_latches *)msg; + + if (tx_tstamp_latches->num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((tx_tstamp_latches->num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_latch)); + } + break; /* These are always errors coming from the VF. */ case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: From patchwork Wed Aug 9 01:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129998 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 629AB43011; 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a="374704471" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704471" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735070" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735070" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:30 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Madhu Chittim Subject: [PATCH 04/14] common/idpf/base: remove mailbox registers Date: Wed, 9 Aug 2023 01:32:58 +0000 Message-Id: <20230809013308.1449103-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Removing mailbox register offsets as the mapping to device register offsets are different between CVL and MEV (they are swapped out) individual drivers will define the offsets based on how registers are hardware addressed. However the it will begin with VDEV_MBX_START offset. Signed-off-by: Madhu Chittim Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/siov_regs.h | 13 ++----------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/.mailmap b/.mailmap index af452d54c6..f23f8fecfa 100644 --- a/.mailmap +++ b/.mailmap @@ -1641,3 +1641,4 @@ Zyta Szpak Jayaprakash Shanmugam Zhenning Xiao Josh Hay +Madhu Chittim diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index fad329601a..7e1ae2e300 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -4,16 +4,6 @@ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ -#define VDEV_MBX_ATQBAL (VDEV_MBX_START + 0x0000) -#define VDEV_MBX_ATQBAH (VDEV_MBX_START + 0x0004) -#define VDEV_MBX_ATQLEN (VDEV_MBX_START + 0x0008) -#define VDEV_MBX_ATQH (VDEV_MBX_START + 0x000C) -#define VDEV_MBX_ATQT (VDEV_MBX_START + 0x0010) -#define VDEV_MBX_ARQBAL (VDEV_MBX_START + 0x0014) -#define VDEV_MBX_ARQBAH (VDEV_MBX_START + 0x0018) -#define VDEV_MBX_ARQLEN (VDEV_MBX_START + 0x001C) -#define VDEV_MBX_ARQH (VDEV_MBX_START + 0x0020) -#define VDEV_MBX_ARQT (VDEV_MBX_START + 0x0024) #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ /* Begin at offset after 1MB (after 256 4k pages) */ @@ -43,5 +33,6 @@ #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) -/* Next offset to begin at 42MB (0x2A00000) */ +#define SIOV_REG_BAR_SIZE 0x2A00000 +/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ #endif /* _SIOV_REGS_H_ */ From patchwork Wed Aug 9 01:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 129999 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EC7A43011; Wed, 9 Aug 2023 03:33:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6FFA343260; Wed, 9 Aug 2023 03:33:37 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 61E0F43265 for ; Wed, 9 Aug 2023 03:33:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544815; x=1723080815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lQGyd+16XrZHM681LQWEjVUSuclMNfbsipMJ8L7HbiU=; b=O+qc9k2d8+DY2Od3qhof07IYE/6MHUPrPnkEWRX0ZmL0hC6PP/EwBdFb aYWiZ5s1/AqrdmE2qTAd59APyctiOlctkwzpbdpVmR0E9JFb9mvhOEmMk OkuWrgOBWDak8ttzbb+GF+7c7wQE7X7P3L2HlaAVd6ygW06s2ISegZVj4 IUt6jm4Xa8dJuY+IBrp+U4lonwnFW5qfeUBm08xiEc4/5HJxpNeKOMplK IaoFgE47O6YzWnIu2/sM4/GoEnvccthnJkxoSItBuozlM+iVKRu940gJg IRCT9XM+ZrcytwWm89uaiyfEvx2sQemnumL+sajXe/0pjcIicj5Rx+Ax8 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704476" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704476" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735081" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735081" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:32 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Shailendra Bhatnagar Subject: [PATCH 05/14] common/idpf/base: add some adi specific fields Date: Wed, 9 Aug 2023 01:32:59 +0000 Message-Id: <20230809013308.1449103-6-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su a) Add maximum ADI count in capabilities message b) Add PF side ADI index to create_adi message c) Define another constant to indicate 'Function active' state of ADI Signed-off-by: Shailendra Bhatnagar Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/virtchnl2.h | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index f23f8fecfa..3879b5a33f 100644 --- a/.mailmap +++ b/.mailmap @@ -1642,3 +1642,4 @@ Jayaprakash Shanmugam Zhenning Xiao Josh Hay Madhu Chittim +Shailendra Bhatnagar diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 320430df6f..7a099f5148 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -294,6 +294,7 @@ /* These messages are only sent to PF from CP */ #define VIRTCHNL2_EVENT_START_RESET_ADI 2 #define VIRTCHNL2_EVENT_FINISH_RESET_ADI 3 +#define VIRTCHNL2_EVENT_ADI_ACTIVE 4 /* VIRTCHNL2_QUEUE_TYPE * Transmit and Receive queue types are valid in legacy as well as split queue @@ -547,7 +548,8 @@ struct virtchnl2_get_capabilities { u8 max_sg_bufs_per_tx_pkt; u8 reserved1; - __le16 pad1; + /* upper bound of number of ADIs supported */ + __le16 max_adis; /* version of Control Plane that is running */ __le16 oem_cp_ver_major; @@ -1076,10 +1078,12 @@ struct virtchnl2_create_adi { __le16 mbx_id; /* PF sends mailbox vector id to CP */ __le16 mbx_vec_id; + /* PF populates this ADI index */ + __le16 adi_index; /* CP populates ADI id */ __le16 adi_id; u8 reserved[64]; - u8 pad[6]; + u8 pad[4]; /* CP populates queue chunks */ struct virtchnl2_queue_reg_chunks chunks; /* PF sends vector chunks to CP */ From patchwork Wed Aug 9 01:33:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130000 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84D6A43011; Wed, 9 Aug 2023 03:34:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EAF8543266; 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08 Aug 2023 18:33:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735104" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735104" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:35 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Julianx Grajkowski Subject: [PATCH 06/14] common/idpf/base: add necessary check Date: Wed, 9 Aug 2023 01:33:00 +0000 Message-Id: <20230809013308.1449103-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Add necessary check for payload and message buffer. Signed-off-by: Julianx Grajkowski Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/idpf_common.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index 3879b5a33f..7400692544 100644 --- a/.mailmap +++ b/.mailmap @@ -1643,3 +1643,4 @@ Zhenning Xiao Josh Hay Madhu Chittim Shailendra Bhatnagar +Julianx Grajkowski diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index fbf71416fd..9610916aa9 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -239,8 +239,10 @@ int idpf_clean_arq_element(struct idpf_hw *hw, e->desc.ret_val = msg.status; e->desc.datalen = msg.data_len; if (msg.data_len > 0) { - if (!msg.ctx.indirect.payload) - return -EINVAL; + if (!msg.ctx.indirect.payload || !msg.ctx.indirect.payload->va || + !e->msg_buf) { + return -EFAULT; + } e->buf_len = msg.data_len; msg_data_len = msg.data_len; idpf_memcpy(e->msg_buf, msg.ctx.indirect.payload->va, msg_data_len, From patchwork Wed Aug 9 01:33:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130001 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5421343011; Wed, 9 Aug 2023 03:34:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 086A643274; Wed, 9 Aug 2023 03:33:43 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id F088A43273 for ; Wed, 9 Aug 2023 03:33:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544821; x=1723080821; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oeKc1PZCZY6SLiiJeUZpb52XDoUwTODKMH+oohYH9EE=; b=UKs8ajZMT5r6A8LL2Bk0QKepS9mAXqgen0JkiVTLaZYYbGS7+pWKA1Uq uMH5czbLHv0Q2D+6mmRQH9eA0UvSdaJKNBNI/8uSo0VRxJg/EhrRJPQcR zdn5M0CuLhPVVg6UnthxofDQs26e109wVbC/JMR9HKfNFY+54u9V0Apx4 XGoL/HVIn5YzVrjoAcPJRPhIcxT8m9mo/RaOG4BsYBfxeo+Tr0ztjz7Vo U2wAOWw8AvHplbfFDrvF1jRobzWtj2J/U98VyW88y4m4Gc+dZjR+jS41m /0jl0uj66te0kgoFC4YMyyl2kX8l2YCR5kuRqzrOxMIpJJzQRjM6xSJcM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704487" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704487" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735114" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735114" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:37 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Alan Brady Subject: [PATCH 07/14] common/idpf/base: add union for SW cookie fields in ctlq msg Date: Wed, 9 Aug 2023 01:33:01 +0000 Message-Id: <20230809013308.1449103-8-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Instead of using something like a byte offset, we can add a union to the struct here to enable direct addressing. Signed-off-by: Alan Brady Signed-off-by: Simei Su --- .mailmap | 1 + drivers/common/idpf/base/idpf_controlq_api.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/.mailmap b/.mailmap index 7400692544..ff96bc7d0e 100644 --- a/.mailmap +++ b/.mailmap @@ -1644,3 +1644,4 @@ Josh Hay Madhu Chittim Shailendra Bhatnagar Julianx Grajkowski +Alan Brady diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 3780304256..f4e7b53ac9 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -77,6 +77,11 @@ struct idpf_ctlq_msg { u8 context[IDPF_INDIRECT_CTX_SIZE]; struct idpf_dma_mem *payload; } indirect; + struct { + u32 rsvd; + u16 data; + u16 flags; + } sw_cookie; } ctx; }; From patchwork Wed Aug 9 01:33:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130002 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 67C5F43011; Wed, 9 Aug 2023 03:34:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C67343276; Wed, 9 Aug 2023 03:33:45 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id A5A8043255 for ; Wed, 9 Aug 2023 03:33:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544823; x=1723080823; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GB0ma8kaZ5985o2MMh0tU/vZuHrdKpYTWbesq6MSJdk=; b=G3c2btUyrOF7VVKpRjTy+Xj8OzlIi+xHV4Yamy9/X5W3S5gkk0mKVq3Q fP+9uqho8n18noErA347m55JeLWsBW+mHVxaK9WJp7fKDUo+abS+GzA6P mBsouwKjKYgz54v0TWbL93YXT3suBfs0Daay40V/HsEsj/0IpMd4Uy5SO WEthj6YpyfV2P+5sBSy6hYZ4MBIiXgWY7hWNY+MsNQR7iF8UyuJSj3676 IjWKyJjZCmL+nLEUL/Svo+K9VwFRidMmfdle61twNK0Qt+JONPdRXPDp6 imXjAOkHyxDqEBfCrK7RRjYwo3QAntJM6EfuI8IHeRJ4B6CnGFMu3h1gk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704493" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704493" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735124" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735124" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:40 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Shailendra Bhatnagar Subject: [PATCH 08/14] common/idpf/base: define non-flexible size structure for ADI Date: Wed, 9 Aug 2023 01:33:02 +0000 Message-Id: <20230809013308.1449103-9-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Customer has a requirement to use the legacy fixed size, single chunk structure for ADI creation - one chunk for queue and one chunk for vector. This is described in detail in customer case https://issuetracker.google.com/issues/270157802. On the other hand, upstream code review patch has been posted with flex-array definitions. To accommodate the old style, the single chunk structures are being renamed so that merger of upstream patches with current code does not impact the existing workflows of the customer. a) Define virtchnl2_non_flex_queue_reg_chunks with a single chunk in it. b) Define virtchnl2_non_flex_vector_chunks with a single chunk in it. c) Rename and modify virtchnl2_create_adi to use the above 2 new structs. New structure is virtchnl2_non_flex_create_adi. Signed-off-by: Shailendra Bhatnagar Signed-off-by: Simei Su --- drivers/common/idpf/base/virtchnl2.h | 66 ++++++++++++++++++---------- 1 file changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 7a099f5148..a19bb193c9 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -89,8 +89,8 @@ * VIRTCHNL2_OP_GET_PTYPE_INFO_RAW */ /* opcodes 529, 530, and 531 are reserved */ -#define VIRTCHNL2_OP_CREATE_ADI 532 -#define VIRTCHNL2_OP_DESTROY_ADI 533 +#define VIRTCHNL2_OP_NON_FLEX_CREATE_ADI 532 +#define VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI 533 #define VIRTCHNL2_OP_LOOPBACK 534 #define VIRTCHNL2_OP_ADD_MAC_ADDR 535 #define VIRTCHNL2_OP_DEL_MAC_ADDR 536 @@ -1061,14 +1061,34 @@ struct virtchnl2_sriov_vfs_info { VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_sriov_vfs_info); -/* VIRTCHNL2_OP_CREATE_ADI +/* structure to specify single chunk of queue */ +/* 'chunks' is fixed size(not flexible) and will be deprecated at some point */ +struct virtchnl2_non_flex_queue_reg_chunks { + __le16 num_chunks; + u8 reserved[6]; + struct virtchnl2_queue_reg_chunk chunks[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(40, virtchnl2_non_flex_queue_reg_chunks); + +/* structure to specify single chunk of interrupt vector */ +/* 'vchunks' is fixed size(not flexible) and will be deprecated at some point */ +struct virtchnl2_non_flex_vector_chunks { + __le16 num_vchunks; + u8 reserved[14]; + struct virtchnl2_vector_chunk vchunks[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(48, virtchnl2_non_flex_vector_chunks); + +/* VIRTCHNL2_OP_NON_FLEX_CREATE_ADI * PF sends this message to CP to create ADI by filling in required - * fields of virtchnl2_create_adi structure. - * CP responds with the updated virtchnl2_create_adi structure containing the - * necessary fields followed by chunks which in turn will have an array of + * fields of virtchnl2_non_flex_create_adi structure. + * CP responds with the updated virtchnl2_non_flex_create_adi structure containing + * the necessary fields followed by chunks which in turn will have an array of * num_chunks entries of virtchnl2_queue_chunk structures. */ -struct virtchnl2_create_adi { +struct virtchnl2_non_flex_create_adi { /* PF sends PASID to CP */ __le32 pasid; /* @@ -1085,24 +1105,24 @@ struct virtchnl2_create_adi { u8 reserved[64]; u8 pad[4]; /* CP populates queue chunks */ - struct virtchnl2_queue_reg_chunks chunks; + struct virtchnl2_non_flex_queue_reg_chunks chunks; /* PF sends vector chunks to CP */ - struct virtchnl2_vector_chunks vchunks; + struct virtchnl2_non_flex_vector_chunks vchunks; }; -VIRTCHNL2_CHECK_STRUCT_LEN(168, virtchnl2_create_adi); +VIRTCHNL2_CHECK_STRUCT_LEN(168, virtchnl2_non_flex_create_adi); -/* VIRTCHNL2_OP_DESTROY_ADI +/* VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI * PF sends this message to CP to destroy ADI by filling * in the adi_id in virtchnl2_destropy_adi structure. * CP responds with the status of the requested operation. */ -struct virtchnl2_destroy_adi { +struct virtchnl2_non_flex_destroy_adi { __le16 adi_id; u8 reserved[2]; }; -VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_destroy_adi); +VIRTCHNL2_CHECK_STRUCT_LEN(4, virtchnl2_non_flex_destroy_adi); /* Based on the descriptor type the PF supports, CP fills ptype_id_10 or * ptype_id_8 for flex and base descriptor respectively. If ptype_id_10 value @@ -1566,10 +1586,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_EVENT"; case VIRTCHNL2_OP_RESET_VF: return "VIRTCHNL2_OP_RESET_VF"; - case VIRTCHNL2_OP_CREATE_ADI: - return "VIRTCHNL2_OP_CREATE_ADI"; - case VIRTCHNL2_OP_DESTROY_ADI: - return "VIRTCHNL2_OP_DESTROY_ADI"; + case VIRTCHNL2_OP_NON_FLEX_CREATE_ADI: + return "VIRTCHNL2_OP_NON_FLEX_CREATE_ADI"; + case VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI: + return "VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI"; case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: @@ -1624,11 +1644,11 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_queue_reg_chunk); } break; - case VIRTCHNL2_OP_CREATE_ADI: - valid_len = sizeof(struct virtchnl2_create_adi); + case VIRTCHNL2_OP_NON_FLEX_CREATE_ADI: + valid_len = sizeof(struct virtchnl2_non_flex_create_adi); if (msglen >= valid_len) { - struct virtchnl2_create_adi *cadi = - (struct virtchnl2_create_adi *)msg; + struct virtchnl2_non_flex_create_adi *cadi = + (struct virtchnl2_non_flex_create_adi *)msg; if (cadi->chunks.num_chunks == 0) { /* zero chunks is allowed as input */ @@ -1645,8 +1665,8 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_vector_chunk); } break; - case VIRTCHNL2_OP_DESTROY_ADI: - valid_len = sizeof(struct virtchnl2_destroy_adi); + case VIRTCHNL2_OP_NON_FLEX_DESTROY_ADI: + valid_len = sizeof(struct virtchnl2_non_flex_destroy_adi); break; case VIRTCHNL2_OP_DESTROY_VPORT: case VIRTCHNL2_OP_ENABLE_VPORT: From patchwork Wed Aug 9 01:33:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130003 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C7C5843011; Wed, 9 Aug 2023 03:34:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C83643279; Wed, 9 Aug 2023 03:33:48 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 2C57343279 for ; Wed, 9 Aug 2023 03:33:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544826; x=1723080826; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rAnqoUL21lfWu5qDFi+dNdsgHRQlXuoVWGayih/1j+M=; b=SfYSQ1dOZQRWLWbiL6rd9jO7Wb3JndEcs6bHxq74MIytoN4UHRabM+xj XXFuCB2cDy3P5w9c/Ib4C4kNrFIUuO8lrX036UPRFqNLl1bidiGycoi2p u5fbrqF3XVP02X9N50Nu3c0r0AxLCoayCjFvgRgOOB0GrVEg7PXZpH54N A7CJeFIyDjgF13XCIZ1+t8O3rXGhd5cpLvum1s/3vCjibxl6fVsMQDdIW FMkv2JVgrBoCxHbKXXY6+ckjBK+DFf1FVia4wy0PtADTvv78N/jfOy25I /O6/6jHIrSG+ek8IhJLsBprYRNuDiZ+X8XfO+PE+xRQigFRZZ+bvLjv+C g==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704503" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704503" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735131" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735131" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:43 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 09/14] common/idpf/base: use local pointer before updating 'CQ out' Date: Wed, 9 Aug 2023 01:33:03 +0000 Message-Id: <20230809013308.1449103-10-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Instead of updating directly to 'cq_out' double pointer, use a local pointer and update only when we return success. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_controlq.c | 43 +++++++++++++----------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 6815153e1d..b84a1ea046 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -137,6 +137,7 @@ int idpf_ctlq_add(struct idpf_hw *hw, struct idpf_ctlq_create_info *qinfo, struct idpf_ctlq_info **cq_out) { + struct idpf_ctlq_info *cq; bool is_rxq = false; int status = 0; @@ -145,26 +146,26 @@ int idpf_ctlq_add(struct idpf_hw *hw, qinfo->buf_size > IDPF_CTLQ_MAX_BUF_LEN) return -EINVAL; - *cq_out = (struct idpf_ctlq_info *) - idpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info)); - if (!(*cq_out)) + cq = (struct idpf_ctlq_info *) + idpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info)); + if (!cq) return -ENOMEM; - (*cq_out)->cq_type = qinfo->type; - (*cq_out)->q_id = qinfo->id; - (*cq_out)->buf_size = qinfo->buf_size; - (*cq_out)->ring_size = qinfo->len; + (cq)->cq_type = qinfo->type; + (cq)->q_id = qinfo->id; + (cq)->buf_size = qinfo->buf_size; + (cq)->ring_size = qinfo->len; - (*cq_out)->next_to_use = 0; - (*cq_out)->next_to_clean = 0; - (*cq_out)->next_to_post = (*cq_out)->ring_size - 1; + (cq)->next_to_use = 0; + (cq)->next_to_clean = 0; + (cq)->next_to_post = cq->ring_size - 1; switch (qinfo->type) { case IDPF_CTLQ_TYPE_MAILBOX_RX: is_rxq = true; /* fallthrough */ case IDPF_CTLQ_TYPE_MAILBOX_TX: - status = idpf_ctlq_alloc_ring_res(hw, *cq_out); + status = idpf_ctlq_alloc_ring_res(hw, cq); break; default: status = -EINVAL; @@ -175,33 +176,35 @@ int idpf_ctlq_add(struct idpf_hw *hw, goto init_free_q; if (is_rxq) { - idpf_ctlq_init_rxq_bufs(*cq_out); + idpf_ctlq_init_rxq_bufs(cq); } else { /* Allocate the array of msg pointers for TX queues */ - (*cq_out)->bi.tx_msg = (struct idpf_ctlq_msg **) + cq->bi.tx_msg = (struct idpf_ctlq_msg **) idpf_calloc(hw, qinfo->len, sizeof(struct idpf_ctlq_msg *)); - if (!(*cq_out)->bi.tx_msg) { + if (!cq->bi.tx_msg) { status = -ENOMEM; goto init_dealloc_q_mem; } } - idpf_ctlq_setup_regs(*cq_out, qinfo); + idpf_ctlq_setup_regs(cq, qinfo); - idpf_ctlq_init_regs(hw, *cq_out, is_rxq); + idpf_ctlq_init_regs(hw, cq, is_rxq); - idpf_init_lock(&(*cq_out)->cq_lock); + idpf_init_lock(&(cq->cq_lock)); - LIST_INSERT_HEAD(&hw->cq_list_head, (*cq_out), cq_list); + LIST_INSERT_HEAD(&hw->cq_list_head, cq, cq_list); + *cq_out = cq; return status; init_dealloc_q_mem: /* free ring buffers and the ring itself */ - idpf_ctlq_dealloc_ring_res(hw, *cq_out); + idpf_ctlq_dealloc_ring_res(hw, cq); init_free_q: - idpf_free(hw, *cq_out); + idpf_free(hw, cq); + cq = NULL; return status; } From patchwork Wed Aug 9 01:33:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEC9043011; 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a="374704507" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704507" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735143" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735143" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:45 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 10/14] common/idpf/base: use 'void' return type Date: Wed, 9 Aug 2023 01:33:04 +0000 Message-Id: <20230809013308.1449103-11-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su As idpf_ctlq_deinit always returns success, make it 'void' instead of returning only success. This also changes the return type for idpf_deinit_hw as 'void'. Based on the upstream comments, explicit __le16 typecasting is not necessary as CPU_TO_LE16 is already being used. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_common.c | 4 ++-- drivers/common/idpf/base/idpf_controlq.c | 7 ++----- drivers/common/idpf/base/idpf_controlq_api.h | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 9610916aa9..7181a7f14c 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -262,12 +262,12 @@ int idpf_clean_arq_element(struct idpf_hw *hw, * idpf_deinit_hw - shutdown routine * @hw: pointer to the hardware structure */ -int idpf_deinit_hw(struct idpf_hw *hw) +void idpf_deinit_hw(struct idpf_hw *hw) { hw->asq = NULL; hw->arq = NULL; - return idpf_ctlq_deinit(hw); + idpf_ctlq_deinit(hw); } /** diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index b84a1ea046..7b12dfab18 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -75,7 +75,7 @@ static void idpf_ctlq_init_rxq_bufs(struct idpf_ctlq_info *cq) desc->flags = CPU_TO_LE16(IDPF_CTLQ_FLAG_BUF | IDPF_CTLQ_FLAG_RD); desc->opcode = 0; - desc->datalen = (__le16)CPU_TO_LE16(bi->size); + desc->datalen = CPU_TO_LE16(bi->size); desc->ret_val = 0; desc->cookie_high = 0; desc->cookie_low = 0; @@ -264,16 +264,13 @@ int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q, * idpf_ctlq_deinit - destroy all control queues * @hw: pointer to hw struct */ -int idpf_ctlq_deinit(struct idpf_hw *hw) +void idpf_ctlq_deinit(struct idpf_hw *hw) { struct idpf_ctlq_info *cq = NULL, *tmp = NULL; - int ret_code = 0; LIST_FOR_EACH_ENTRY_SAFE(cq, tmp, &hw->cq_list_head, idpf_ctlq_info, cq_list) idpf_ctlq_remove(hw, cq); - - return ret_code; } /** diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index f4e7b53ac9..78a54f6b4c 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -205,6 +205,6 @@ int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_dma_mem **buffs); /* Will destroy all q including the default mb */ -int idpf_ctlq_deinit(struct idpf_hw *hw); +void idpf_ctlq_deinit(struct idpf_hw *hw); #endif /* _IDPF_CONTROLQ_API_H_ */ diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 988ff00506..e2f090a9e3 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -20,7 +20,7 @@ #define APF int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size); -int idpf_deinit_hw(struct idpf_hw *hw); +void idpf_deinit_hw(struct idpf_hw *hw); int idpf_clean_arq_element(struct idpf_hw *hw, struct idpf_arq_event_info *e, From patchwork Wed Aug 9 01:33:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130005 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E39F43011; 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a="374704509" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704509" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735152" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735152" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:48 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 11/14] common/idpf/base: refactor descriptor 'ret val' stripping Date: Wed, 9 Aug 2023 01:33:05 +0000 Message-Id: <20230809013308.1449103-12-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Conditional check is not necessary to strip and get status bits from the descriptor. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_controlq.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 7b12dfab18..da5c930578 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -426,11 +426,8 @@ static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, if (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) break; - desc_err = LE16_TO_CPU(desc->ret_val); - if (desc_err) { - /* strip off FW internal code */ - desc_err &= 0xff; - } + /* strip off FW internal code */ + desc_err = LE16_TO_CPU(desc->ret_val) & 0xff; msg_status[i] = cq->bi.tx_msg[ntc]; if (!msg_status[i]) From patchwork Wed Aug 9 01:33:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130006 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B7B443011; Wed, 9 Aug 2023 03:34:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB4354328B; Wed, 9 Aug 2023 03:33:54 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id A51C04328B for ; Wed, 9 Aug 2023 03:33:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544833; x=1723080833; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VqHOrZKQG985ssEmaOes61pf5x23W7Qlsr6Dyf6Sc28=; b=OLV9lfvk9o3tPVj3LI9Mt9lVQYuFAcaBqRyBGoBpq/stRo11a++3wfJs UFP4KMrhIPM3SF3ARWOsYsOzPn2Z04NcJ1Jvc8GBA7M0mmURb58zu+9W/ quhWkxwq/HVXnd9s5I1TUpBUz58ylUG6QjmwpVVUP4++VnWF+jDEFFJpV blXYjMJMf6MpwWAfOSnxuHbE1QQStTB9wKQeFHsx8OhEQwXbqq6Ca4Ru9 reYV0rm6ETHguGvF5Vxd37qqUntEtLM5zedNepaOJkmvow/+UPUKy+1Ec I30pSJ1voIFbHukrO2WdfAtzdxDq693kY01xaeZoQ4OJn/f3QI2oB/IBc g==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704511" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704511" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735164" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735164" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:50 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 12/14] common/idpf/base: refine comments and alignment Date: Wed, 9 Aug 2023 01:33:06 +0000 Message-Id: <20230809013308.1449103-13-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Refine the macros and definitions by using 'tab' spaces and new lines whereever necessary. Also refine the comment in 'idpf_ctlq_setup_regs'. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_controlq.c | 2 +- drivers/common/idpf/base/idpf_controlq_api.h | 10 +---- drivers/common/idpf/base/idpf_lan_pf_regs.h | 7 ++-- drivers/common/idpf/base/idpf_lan_txrx.h | 43 ++++++++++---------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 25 ++++++++---- 5 files changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index da5c930578..c24bfd23ef 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -13,7 +13,7 @@ static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, struct idpf_ctlq_create_info *q_create_info) { - /* set head and tail registers in our local struct */ + /* set control queue registers in our local struct */ cq->reg.head = q_create_info->reg.head; cq->reg.tail = q_create_info->reg.tail; cq->reg.len = q_create_info->reg.len; diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 78a54f6b4c..38f5d2df3c 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -21,10 +21,7 @@ enum idpf_ctlq_type { IDPF_CTLQ_TYPE_RDMA_COMPL = 7 }; -/* - * Generic Control Queue Structures - */ - +/* Generic Control Queue Structures */ struct idpf_ctlq_reg { /* used for queue tracking */ u32 head; @@ -157,10 +154,7 @@ enum idpf_mbx_opc { idpf_mbq_opc_send_msg_to_peer_drv = 0x0804, }; -/* - * API supported for control queue management - */ - +/* API supported for control queue management */ /* Will init all required q including default mb. "q_info" is an array of * create_info structs equal to the number of control queues to be created. */ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 8542620e01..e47afad6e9 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -80,10 +80,11 @@ /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is * spacing b/w itrn registers of the same vector. */ -#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ -#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) +#define PF_GLINT_ITR(_ITR, _INT) \ + (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 #define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 7b03693eb1..cc8f1cd2a5 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -8,9 +8,9 @@ #include "idpf_osdep.h" enum idpf_rss_hash { - /* Values 0 - 28 are reserved for future use */ - IDPF_HASH_INVALID = 0, - IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, + IDPF_HASH_INVALID = 0, + /* Values 1 - 28 are reserved for future use */ + IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29, IDPF_HASH_NONF_MULTICAST_IPV4_UDP, IDPF_HASH_NONF_IPV4_UDP, IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK, @@ -19,7 +19,7 @@ enum idpf_rss_hash { IDPF_HASH_NONF_IPV4_OTHER, IDPF_HASH_FRAG_IPV4, /* Values 37-38 are reserved */ - IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, + IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39, IDPF_HASH_NONF_MULTICAST_IPV6_UDP, IDPF_HASH_NONF_IPV6_UDP, IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK, @@ -32,22 +32,23 @@ enum idpf_rss_hash { IDPF_HASH_NONF_FCOE_RX, IDPF_HASH_NONF_FCOE_OTHER, /* Values 51-62 are reserved */ - IDPF_HASH_L2_PAYLOAD = 63, + IDPF_HASH_L2_PAYLOAD = 63, + IDPF_HASH_MAX }; /* Supported RSS offloads */ -#define IDPF_DEFAULT_RSS_HASH ( \ - BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ - BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ +#define IDPF_DEFAULT_RSS_HASH \ + (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV4) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \ + BIT_ULL(IDPF_HASH_FRAG_IPV6) | \ BIT_ULL(IDPF_HASH_L2_PAYLOAD)) /* TODO: Wrap below comment under internal flag @@ -55,11 +56,11 @@ enum idpf_rss_hash { * They are supported by FPK and future products */ #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \ - BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ - BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ - BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \ + BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \ + BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \ BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index b5ff9b2cc9..4c5249129e 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -94,14 +94,23 @@ * b/w itrn registers of the same vector */ #define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) -#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ - ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) -/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */ -#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) -/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */ -#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) -/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */ -#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) +#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) +/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x40 and base register offset is 0x00002800 + */ +#define VF_INT_ITRN(_INT, _ITR) \ + (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) +/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x100 and base register offset is 0x00002C00 + */ +#define VF_INT_ITRN_64(_INT, _ITR) \ + (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) +/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing + * is 0x2000 and base register offset is 0x00072000 + */ +#define VF_INT_ITRN_2K(_INT, _ITR) \ + (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 #define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) From patchwork Wed Aug 9 01:33:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130007 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB21043011; Wed, 9 Aug 2023 03:34:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A62D4328E; Wed, 9 Aug 2023 03:33:58 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 7F59F4328C for ; Wed, 9 Aug 2023 03:33:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544836; x=1723080836; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aJYpCNqPpujuEZACey0RvkxBsvaohjc94Ltqd9xAfUE=; b=HYYh6UjfotyliQ24Rz0aJIM+0ErTw1+bS3nFyDnyjQZs/lQ+SpY64g3h ttRNcBMh/BfIbTl8RIULjPQHjo3o5jCKtre+m8qLrBkv8HQYPGshBjCro HHWDf8Xw0m+SVN+pH/4he547kHzBXun6yHt4gwotkUrphlnY5zNAeY0QM CEvS2lZ0OL6OoYoB1TBKuifQ0eIIwhonojgrYN/qMMnzBjiHhud/3H68h 280X3hyG5sqM0uo7B5TwVom8sIIBpsju/ZroVbvGdED+xhwPHRWZGGkWN 6rLNuldFtBM5kIcto8Yon1G26fpE5qYXy/OUV5s7pv+UVAqkK7oOxxRxX Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704515" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704515" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735177" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735177" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:53 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 13/14] common/idpf/base: use GENMASK macro Date: Wed, 9 Aug 2023 01:33:07 +0000 Message-Id: <20230809013308.1449103-14-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Instead of using a custom defined macro for generating a mask, use the standard GENMASK macro. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 ++--- drivers/common/idpf/base/idpf_lan_txrx.h | 116 +++++++++----------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +-- drivers/common/idpf/base/idpf_osdep.h | 7 ++ 4 files changed, 80 insertions(+), 85 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index e47afad6e9..b9d82592c0 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -24,7 +24,7 @@ #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) #define PF_FW_ARQLEN_ARQLEN_S 0 -#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) +#define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) #define PF_FW_ARQLEN_ARQVFE_S 28 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) #define PF_FW_ARQLEN_ARQOVFL_S 29 @@ -35,14 +35,14 @@ #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) #define PF_FW_ARQH (PF_FW_BASE + 0xC) #define PF_FW_ARQH_ARQH_S 0 -#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S) +#define PF_FW_ARQH_ARQH_M GENMASK(12, 0) #define PF_FW_ARQT (PF_FW_BASE + 0x10) #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) #define PF_FW_ATQLEN_ATQLEN_S 0 -#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S) +#define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) #define PF_FW_ATQLEN_ATQVFE_S 28 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) #define PF_FW_ATQLEN_ATQOVFL_S 29 @@ -53,7 +53,7 @@ #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) #define PF_FW_ATQH (PF_FW_BASE + 0x20) #define PF_FW_ATQH_ATQH_S 0 -#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S) +#define PF_FW_ATQH_ATQH_M GENMASK(9, 0) #define PF_FW_ATQT (PF_FW_BASE + 0x24) /* Interrupts */ @@ -66,7 +66,7 @@ #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 -#define PF_GLINT_DYN_CTL_ITR_INDX_M IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) +#define PF_GLINT_DYN_CTL_ITR_INDX_M GENMASK(4, 3) #define PF_GLINT_DYN_CTL_INTERVAL_S 5 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 @@ -87,13 +87,13 @@ (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 -#define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) +#define PF_GLINT_ITR_INTERVAL_M GENMASK(11, 0) /* Timesync registers */ #define PF_TIMESYNC_BASE 0x08404000 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 -#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) +#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M GENMASK(1, 0) #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) @@ -105,23 +105,23 @@ /* Generic registers */ #define PF_INT_DIR_OICR_ENA 0x08406000 #define PF_INT_DIR_OICR_ENA_S 0 -#define PF_INT_DIR_OICR_ENA_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) +#define PF_INT_DIR_OICR_ENA_M GENMASK(31, 0) #define PF_INT_DIR_OICR 0x08406004 #define PF_INT_DIR_OICR_TSYN_EVNT 0 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) #define PF_INT_DIR_OICR_CAUSE 0x08406008 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 -#define PF_INT_DIR_OICR_CAUSE_CAUSE_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) +#define PF_INT_DIR_OICR_CAUSE_CAUSE_M GENMASK(31, 0) #define PF_INT_PBA_CLEAR 0x0840600C #define PF_FUNC_RID 0x08406010 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 -#define PF_FUNC_RID_FUNCTION_NUMBER_M IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) +#define PF_FUNC_RID_FUNCTION_NUMBER_M GENMASK(2, 0) #define PF_FUNC_RID_DEVICE_NUMBER_S 3 -#define PF_FUNC_RID_DEVICE_NUMBER_M IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) +#define PF_FUNC_RID_DEVICE_NUMBER_M GENMASK(7, 3) #define PF_FUNC_RID_BUS_NUMBER_S 8 -#define PF_FUNC_RID_BUS_NUMBER_M IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S) +#define PF_FUNC_RID_BUS_NUMBER_M GENMASK(15, 8) /* Reset registers */ #define PFGEN_RTRIG 0x08407000 @@ -133,7 +133,7 @@ #define PFGEN_RTRIG_IMCR_M BIT(2) #define PFGEN_RSTAT 0x08407008 /* PFR Status */ #define PFGEN_RSTAT_PFR_STATE_S 0 -#define PFGEN_RSTAT_PFR_STATE_M IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S) +#define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) #define PFGEN_CTRL 0x0840700C #define PFGEN_CTRL_PFSWR BIT(0) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index cc8f1cd2a5..523394e4c0 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -64,65 +64,54 @@ enum idpf_rss_hash { BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP)) /* For idpf_splitq_base_tx_compl_desc */ -#define IDPF_TXD_COMPLQ_GEN_S 15 +#define IDPF_TXD_COMPLQ_GEN_S 15 #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 -#define IDPF_TXD_COMPLQ_COMPL_TYPE_M \ - IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) -#define IDPF_TXD_COMPLQ_QID_S 0 -#define IDPF_TXD_COMPLQ_QID_M IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) +#define IDPF_TXD_COMPLQ_COMPL_TYPE_M GENMASK_ULL(13, 11) +#define IDPF_TXD_COMPLQ_QID_S 0 +#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0) /* For base mode TX descriptors */ -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 -#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 -#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \ - (0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S) -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 -#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \ - (0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S) +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23 +#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M \ + BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S) +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19 +#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M GENMASK_ULL(22, 19) +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12 +#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M GENMASK_ULL(18, 12) #define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11 -#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ +#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \ BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S) #define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \ IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M -#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 -#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S) -#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S) +#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9 +#define IDPF_TXD_CTX_QW0_TUNN_NATT_M GENMASK_ULL(10, 9) +#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(9) +#define IDPF_TXD_CTX_GRE_TUNNELING BIT_ULL(10) #define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \ - (0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S) -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 -#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \ - (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S) - -#define IDPF_TXD_CTX_QW1_MSS_S 50 -#define IDPF_TXD_CTX_QW1_MSS_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) -#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 -#define IDPF_TXD_CTX_QW1_TSO_LEN_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) -#define IDPF_TXD_CTX_QW1_CMD_S 4 -#define IDPF_TXD_CTX_QW1_CMD_M \ - IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) -#define IDPF_TXD_CTX_QW1_DTYPE_S 0 -#define IDPF_TXD_CTX_QW1_DTYPE_M \ - IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) -#define IDPF_TXD_QW1_L2TAG1_S 48 -#define IDPF_TXD_QW1_L2TAG1_M \ - IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) -#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 -#define IDPF_TXD_QW1_TX_BUF_SZ_M \ - IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) -#define IDPF_TXD_QW1_OFFSET_S 16 -#define IDPF_TXD_QW1_OFFSET_M \ - IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) -#define IDPF_TXD_QW1_CMD_S 4 -#define IDPF_TXD_QW1_CMD_M IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S) -#define IDPF_TXD_QW1_DTYPE_S 0 -#define IDPF_TXD_QW1_DTYPE_M IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M GENMASK_ULL(7, 2) +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0 +#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M GENMASK_ULL(1, 0) + +#define IDPF_TXD_CTX_QW1_MSS_S 50 +#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50) +#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 +#define IDPF_TXD_CTX_QW1_TSO_LEN_M GENMASK_ULL(47, 30) +#define IDPF_TXD_CTX_QW1_CMD_S 4 +#define IDPF_TXD_CTX_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_CTX_QW1_DTYPE_S 0 +#define IDPF_TXD_CTX_QW1_DTYPE_M GENMASK_ULL(3, 0) +#define IDPF_TXD_QW1_L2TAG1_S 48 +#define IDPF_TXD_QW1_L2TAG1_M GENMASK_ULL(63, 48) +#define IDPF_TXD_QW1_TX_BUF_SZ_S 34 +#define IDPF_TXD_QW1_TX_BUF_SZ_M GENMASK_ULL(47, 34) +#define IDPF_TXD_QW1_OFFSET_S 16 +#define IDPF_TXD_QW1_OFFSET_M GENMASK_ULL(33, 16) +#define IDPF_TXD_QW1_CMD_S 4 +#define IDPF_TXD_QW1_CMD_M GENMASK_ULL(15, 4) +#define IDPF_TXD_QW1_DTYPE_S 0 +#define IDPF_TXD_QW1_DTYPE_M GENMASK_ULL(3, 0) /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH 0 @@ -173,10 +162,10 @@ enum idpf_tx_desc_len_fields { IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; -#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) -#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) -#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) -#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_MACLEN_M GENMASK_ULL(6, 0) +#define IDPF_TXD_QW1_IPLEN_M GENMASK_ULL(13, 7) +#define IDPF_TXD_QW1_L4LEN_M GENMASK_ULL(17, 14) +#define IDPF_TXD_QW1_FCLEN_M GENMASK_ULL(17, 14) enum idpf_tx_base_desc_cmd_bits { IDPF_TX_DESC_CMD_EOP = 0x0001, @@ -242,11 +231,10 @@ struct idpf_flex_tx_desc { __le64 buf_addr; /* Packet buffer address */ struct { __le16 cmd_dtype; -#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 -#define IDPF_FLEX_TXD_QW1_DTYPE_M \ - IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) +#define IDPF_FLEX_TXD_QW1_DTYPE_S 0 +#define IDPF_FLEX_TXD_QW1_DTYPE_M GENMASK(4, 0) #define IDPF_FLEX_TXD_QW1_CMD_S 5 -#define IDPF_FLEX_TXD_QW1_CMD_M IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_FLEX_TXD_QW1_CMD_M GENMASK(15, 5) union { /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ u8 raw[4]; @@ -388,9 +376,9 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF #define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VF 0 +#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV BIT(14) +#define IDPF_TXD_FLEX_CTX_FTYPE_PF BIT(15) u8 hdr_len; u8 ptag; } tso; @@ -407,10 +395,10 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S) #define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 -#define IDPF_TXD_FLEX_CTX_QW1_TPH \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S) +#define IDPF_TXD_FLEX_CTX_QW1_TPH \ + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_TPH_S) #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ @@ -418,7 +406,7 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) + BIT_ULL(IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 4c5249129e..f394a0d67a 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -9,7 +9,7 @@ /* Reset */ #define VFGEN_RSTAT 0x00008800 #define VFGEN_RSTAT_VFR_STATE_S 0 -#define VFGEN_RSTAT_VFR_STATE_M IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S) +#define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0) /* Control(VF Mailbox) Queue */ #define VF_BASE 0x00006000 @@ -18,7 +18,7 @@ #define VF_ATQBAH (VF_BASE + 0x1800) #define VF_ATQLEN (VF_BASE + 0x0800) #define VF_ATQLEN_ATQLEN_S 0 -#define VF_ATQLEN_ATQLEN_M IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S) +#define VF_ATQLEN_ATQLEN_M GENMASK(9, 0) #define VF_ATQLEN_ATQVFE_S 28 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) #define VF_ATQLEN_ATQOVFL_S 29 @@ -29,14 +29,14 @@ #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) #define VF_ATQH (VF_BASE + 0x0400) #define VF_ATQH_ATQH_S 0 -#define VF_ATQH_ATQH_M IDPF_M(0x3FF, VF_ATQH_ATQH_S) +#define VF_ATQH_ATQH_M GENMASK(9, 0) #define VF_ATQT (VF_BASE + 0x2400) #define VF_ARQBAL (VF_BASE + 0x0C00) #define VF_ARQBAH (VF_BASE) #define VF_ARQLEN (VF_BASE + 0x2000) #define VF_ARQLEN_ARQLEN_S 0 -#define VF_ARQLEN_ARQLEN_M IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S) +#define VF_ARQLEN_ARQLEN_M GENMASK(9, 0) #define VF_ARQLEN_ARQVFE_S 28 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) #define VF_ARQLEN_ARQOVFL_S 29 @@ -47,7 +47,7 @@ #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) #define VF_ARQH (VF_BASE + 0x1400) #define VF_ARQH_ARQH_S 0 -#define VF_ARQH_ARQH_M IDPF_M(0x1FFF, VF_ARQH_ARQH_S) +#define VF_ARQH_ARQH_M GENMASK(12, 0) #define VF_ARQT (VF_BASE + 0x1000) /* Transmit queues */ @@ -69,7 +69,7 @@ #define VF_INT_DYN_CTL0_INTENA_S 0 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) #define VF_INT_DYN_CTL0_ITR_INDX_S 3 -#define VF_INT_DYN_CTL0_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) +#define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_INTENA_S 0 @@ -79,7 +79,7 @@ #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) #define VF_INT_DYN_CTLN_ITR_INDX_S 3 -#define VF_INT_DYN_CTLN_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) +#define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3) #define VF_INT_DYN_CTLN_INTERVAL_S 5 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 @@ -113,7 +113,7 @@ (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 -#define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) +#define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0) #define VF_INT_PBA_CLEAR 0x00008900 #define VF_INT_ICR0_ENA1 0x00005000 diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 2a817a9807..74a376cb13 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -48,6 +48,13 @@ typedef struct idpf_lock idpf_lock; #define IDPF_M(m, s) ((m) << (s)) +#define BITS_PER_LONG (8 * sizeof(long)) +#define BITS_PER_LONG_LONG (8 * sizeof(long long)) +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + #ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 #endif From patchwork Wed Aug 9 01:33:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 130008 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: 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hP/7Rx6sN9CPNbNfidfJGG/OScGWgOGkjB0FCWkoDCtnD3a+ct43mOg1M Z/AQf64tOZ+4LLNb32gFaLbEy475grAxQ9jw9OlCpZs/vdBqYLzznbJ6U w3JTqn+Atn6/34DBL9mts7GEHQPGAuaOF/043LhcGN6e8T+hcLBnGqQua Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704519" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704519" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735185" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735185" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:56 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Pavan Kumar Linga Subject: [PATCH 14/14] common/idpf/base: use 'type functionname(args)' style Date: Wed, 9 Aug 2023 01:33:08 +0000 Message-Id: <20230809013308.1449103-15-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Instead of splitting the function name and function type into multiple lines, use then in a single line. Signed-off-by: Pavan Kumar Linga Signed-off-by: Simei Su --- drivers/common/idpf/base/idpf_controlq.c | 5 ++--- drivers/common/idpf/base/idpf_controlq_setup.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index c24bfd23ef..07bbec91b9 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -9,9 +9,8 @@ * @cq: pointer to the specific control queue * @q_create_info: structs containing info for each queue to be initialized */ -static void -idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, - struct idpf_ctlq_create_info *q_create_info) +static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq, + struct idpf_ctlq_create_info *q_create_info) { /* set control queue registers in our local struct */ cq->reg.head = q_create_info->reg.head; diff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c index 0f1b52a7e9..21f43c74f5 100644 --- a/drivers/common/idpf/base/idpf_controlq_setup.c +++ b/drivers/common/idpf/base/idpf_controlq_setup.c @@ -11,9 +11,8 @@ * @hw: pointer to hw struct * @cq: pointer to the specific Control queue */ -static int -idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw, - struct idpf_ctlq_info *cq) +static int idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw, + struct idpf_ctlq_info *cq) { size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc);