From patchwork Tue Jun 6 06:12:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Bhansali X-Patchwork-Id: 128163 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9392B42C3C; Tue, 6 Jun 2023 08:12:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C50C40A84; Tue, 6 Jun 2023 08:12:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 92F8C406B7 for ; Tue, 6 Jun 2023 08:12:57 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3563hTC9023740 for ; Mon, 5 Jun 2023 23:12:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=SwPt8N7Dl+u0fb8L319lma0GXpELuJ+zLE4FvoPDThs=; b=SnJtM7UdVK0x7vHs04yc4j+Oua3A+s/cMiXKrVKDK4OV/FSWyQp/iRLsxA3eBYZkGESe M2dpDdbuiD2gnhL03bMpQoqJ67bgpIJ4UyshI46xeun3Od6+DevhU/CA28MKxKs/2A7S cpCvT9LYidmnJKjFfkVC6HXrH1ns9thJH7gjlrI1+avcAnDYA02m2hilSRHzvQXos46h On+ggyVtRnAda5Ey90PXa4jXnwhP+G59jB9FdD6StRise0+P9JewCrHAafFKSz294xon eIZVz4EWkFyFvEVdRpcRHytrgLoEIn5RlraQvmg1zIlDmPufjTGM1fW/vZ8bN4LzhpWy Qw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r1kpkaaws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 05 Jun 2023 23:12:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 5 Jun 2023 23:12:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 5 Jun 2023 23:12:54 -0700 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id 9F3D43F7050; Mon, 5 Jun 2023 23:12:52 -0700 (PDT) From: Rahul Bhansali To: , Nithin Kumar Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH] net/cnxk: add atomic fc check in poll mode Tx path Date: Tue, 6 Jun 2023 11:42:49 +0530 Message-ID: <20230606061249.833290-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rjIoUTJ3dYQ0AXrjS9IJ0Ldi-qGnJupF X-Proofpoint-GUID: rjIoUTJ3dYQ0AXrjS9IJ0Ldi-qGnJupF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-06_03,2023-06-05_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a support of atomic fc check in poll mode Tx path. This atomic check is useful if multiple threads are using the same Tx queue. This will be enabled when Tx offload RTE_ETH_TX_OFFLOAD_MT_LOCKFREE is set. Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_ethdev.c | 3 ++ drivers/net/cnxk/cn10k_rxtx.h | 1 + drivers/net/cnxk/cn10k_tx.h | 61 ++++++++++++++++++++++++++------- 3 files changed, 52 insertions(+), 13 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 792c1b1970..4c4acc7cf0 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -241,6 +241,9 @@ cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, return rc; } + /* Set Txq flag for MT_LOCKFREE */ + txq->flag = !!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MT_LOCKFREE); + /* Store lmt base in tx queue for easy access */ txq->lmt_base = nix->lmt_base; txq->io_addr = sq->io_addr; diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.h index 65dd57494a..b4287e2864 100644 --- a/drivers/net/cnxk/cn10k_rxtx.h +++ b/drivers/net/cnxk/cn10k_rxtx.h @@ -51,6 +51,7 @@ struct cn10k_eth_txq { rte_iova_t io_addr; uint16_t sqes_per_sqb_log2; int16_t nb_sqb_bufs_adj; + uint8_t flag; rte_iova_t cpt_io_addr; uint64_t sa_base; uint64_t *cpt_fc; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 4f23a8dfc3..17793493cc 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -47,6 +47,47 @@ } \ } while (0) +#define NIX_XMIT_FC_OR_RETURN_MTS(txq, pkts) \ + do { \ + int64_t *fc_cache = &(txq)->fc_cache_pkts; \ + uint8_t retry_count = 8; \ + int64_t val, newval; \ + retry: \ + /* Reduce the cached count */ \ + val = (int64_t)__atomic_fetch_sub(fc_cache, pkts, __ATOMIC_RELAXED); \ + val -= pkts; \ + /* Cached value is low, Update the fc_cache_pkts */ \ + if (unlikely(val < 0)) { \ + /* Multiply with sqe_per_sqb to express in pkts */ \ + newval = txq->nb_sqb_bufs_adj - __atomic_load_n(txq->fc_mem, \ + __ATOMIC_RELAXED); \ + newval = (newval << (txq)->sqes_per_sqb_log2) - newval; \ + newval -= pkts; \ + if (!__atomic_compare_exchange_n(fc_cache, &val, newval, false, \ + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) { \ + if (retry_count) { \ + retry_count--; \ + goto retry; \ + } else \ + return 0; \ + } \ + /* Update and check it again for the room */ \ + if (unlikely(newval < 0)) \ + return 0; \ + } \ + } while (0) + +#define NIX_XMIT_FC_CHECK_RETURN(txq, pkts) \ + do { \ + if (unlikely((txq)->flag)) \ + NIX_XMIT_FC_OR_RETURN_MTS(txq, pkts); \ + else { \ + NIX_XMIT_FC_OR_RETURN(txq, pkts); \ + /* Reduce the cached count */ \ + txq->fc_cache_pkts -= pkts; \ + } \ + } while (0) + /* Encoded number of segments to number of dwords macro, each value of nb_segs * is encoded as 4bits. */ @@ -1174,11 +1215,9 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts, if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F && txq->tx_compl.ena) handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); - if (!(flags & NIX_TX_VWQE_F)) { - NIX_XMIT_FC_OR_RETURN(txq, pkts); - /* Reduce the cached count */ - txq->fc_cache_pkts -= pkts; - } + if (!(flags & NIX_TX_VWQE_F)) + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); + /* Get cmd skeleton */ cn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F)); @@ -1323,11 +1362,9 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws, if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F && txq->tx_compl.ena) handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); - if (!(flags & NIX_TX_VWQE_F)) { - NIX_XMIT_FC_OR_RETURN(txq, pkts); - /* Reduce the cached count */ - txq->fc_cache_pkts -= pkts; - } + if (!(flags & NIX_TX_VWQE_F)) + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); + /* Get cmd skeleton */ cn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F)); @@ -1879,11 +1916,9 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); if (!(flags & NIX_TX_VWQE_F)) { - NIX_XMIT_FC_OR_RETURN(txq, pkts); scalar = pkts & (NIX_DESCS_PER_LOOP - 1); pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP); - /* Reduce the cached count */ - txq->fc_cache_pkts -= pkts; + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); } else { scalar = pkts & (NIX_DESCS_PER_LOOP - 1); pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);