From patchwork Fri May 19 03:42:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 127065 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6E4742B42; Fri, 19 May 2023 05:42:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 77D7840A82; Fri, 19 May 2023 05:42:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A5919406B5 for ; Fri, 19 May 2023 05:42:27 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34IHgCNS012880 for ; Thu, 18 May 2023 20:42:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3R6YLguKW23L9Cwf6Xxwgmuy/cicxQU+O8R/QFaK3Mc=; b=B+UBCHAieTwElmRCzYM/B+Oy0ry43E4uIpHdwhL542mjt09p16zS5B62YImuFRatIy8P 3TkU49mjvRD4z03FFHBbaPAOQmIDx+scs7DNl1L20fZElyGkoXe1ptlqMLFMe55HyYas dQUFF8eY8XEg5Y7K6JImd/Ri4/x+QJ8ndbxqCgRYMHPX2uAiejVeoMZzX6VNRXYfC7gH ekMFZMmaVq2/wF4aMj/71j0Kj2LTpCEfEuQY8kF2IZ92bldklsJIYMOM9q0mXHo1WlBp R7szFul29r+LAOVYzcTE4k769rM5mRNGP0l0KfmtOOdWEY0GvHw3Ng+z+Gzhdnpe9LoT VQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qn7jbedge-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 May 2023 20:42:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 18 May 2023 20:42:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 18 May 2023 20:42:24 -0700 Received: from satheeshpaullabpc.. (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 095F23F7085; Thu, 18 May 2023 20:42:22 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Subject: [dpdk-dev] [PATCH 1/2] common/cnxk: support Tx queue flow pattern in ROC API Date: Fri, 19 May 2023 09:12:18 +0530 Message-ID: <20230519034219.2209868-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Proofpoint-GUID: X96Hzek3iUbRHx64LZBELa0y-k5XwuLf X-Proofpoint-ORIG-GUID: X96Hzek3iUbRHx64LZBELa0y-k5XwuLf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-19_01,2023-05-17_02,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satheesh Paul Added ROC API changes to support Tx queue flow pattern item. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar K --- Depends-on: series-28056 ("ethdev: add Tx queue flow matching item") drivers/common/cnxk/roc_npc.c | 16 +++++--- drivers/common/cnxk/roc_npc.h | 1 + drivers/common/cnxk/roc_npc_mcam.c | 61 +++++++++++++++++++++++------ drivers/common/cnxk/roc_npc_parse.c | 52 ++++++++++++++++++++++++ drivers/common/cnxk/roc_npc_priv.h | 2 + 5 files changed, 115 insertions(+), 17 deletions(-) diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c index ba75207955..4b5be65b72 100644 --- a/drivers/common/cnxk/roc_npc.c +++ b/drivers/common/cnxk/roc_npc.c @@ -779,11 +779,10 @@ npc_parse_pattern(struct npc *npc, const struct roc_npc_item_info pattern[], struct roc_npc_flow *flow, struct npc_parse_state *pst) { npc_parse_stage_func_t parse_stage_funcs[] = { - npc_parse_meta_items, npc_parse_mark_item, npc_parse_pre_l2, - npc_parse_cpt_hdr, npc_parse_higig2_hdr, npc_parse_la, - npc_parse_lb, npc_parse_lc, npc_parse_ld, - npc_parse_le, npc_parse_lf, npc_parse_lg, - npc_parse_lh, + npc_parse_meta_items, npc_parse_mark_item, npc_parse_pre_l2, npc_parse_cpt_hdr, + npc_parse_higig2_hdr, npc_parse_tx_queue, npc_parse_la, npc_parse_lb, + npc_parse_lc, npc_parse_ld, npc_parse_le, npc_parse_lf, + npc_parse_lg, npc_parse_lh, }; uint8_t layer = 0; int key_offset; @@ -792,9 +791,9 @@ npc_parse_pattern(struct npc *npc, const struct roc_npc_item_info pattern[], if (pattern == NULL) return NPC_ERR_PARAM; - memset(pst, 0, sizeof(*pst)); pst->npc = npc; pst->flow = flow; + pst->nix_intf = flow->nix_intf; /* Use integral byte offset */ key_offset = pst->npc->keyx_len[flow->nix_intf]; @@ -864,8 +863,12 @@ npc_parse_rule(struct roc_npc *roc_npc, const struct roc_npc_attr *attr, struct npc_parse_state *pst) { struct npc *npc = roc_npc_to_npc_priv(roc_npc); + struct roc_nix *roc_nix = roc_npc->roc_nix; + struct nix *nix = roc_nix_to_nix_priv(roc_nix); int err; + pst->nb_tx_queues = nix->nb_tx_queues; + /* Check attr */ err = npc_parse_attr(npc, attr, flow); if (err) @@ -1425,6 +1428,7 @@ roc_npc_flow_create(struct roc_npc *roc_npc, const struct roc_npc_attr *attr, return NULL; } memset(flow, 0, sizeof(*flow)); + memset(&parse_state, 0, sizeof(parse_state)); rc = npc_parse_rule(roc_npc, attr, pattern, actions, flow, &parse_state); diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index 26a43c12cb..5984da1c1a 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -39,6 +39,7 @@ enum roc_npc_item_type { ROC_NPC_ITEM_TYPE_QINQ, ROC_NPC_ITEM_TYPE_RAW, ROC_NPC_ITEM_TYPE_MARK, + ROC_NPC_ITEM_TYPE_TX_QUEUE, ROC_NPC_ITEM_TYPE_END, }; diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index 72892be300..e0019818c7 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -587,9 +587,47 @@ npc_mcam_set_channel(struct roc_npc_flow *flow, flow->mcam_mask[0] |= (uint64_t)mask; } +static int +npc_mcam_set_pf_func(struct npc *npc, struct roc_npc_flow *flow, uint16_t pf_func) +{ +#define NPC_PF_FUNC_WIDTH 2 +#define NPC_KEX_PF_FUNC_MASK 0xFFFF + uint16_t nr_bytes, hdr_offset, key_offset, pf_func_offset; + uint8_t *flow_mcam_data, *flow_mcam_mask; + struct npc_lid_lt_xtract_info *xinfo; + bool pffunc_found = false; + uint16_t mask = 0xFFFF; + int i; + + flow_mcam_data = (uint8_t *)flow->mcam_data; + flow_mcam_mask = (uint8_t *)flow->mcam_mask; + + xinfo = &npc->prx_dxcfg[NIX_INTF_TX][NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER]; + + for (i = 0; i < NPC_MAX_LD; i++) { + nr_bytes = xinfo->xtract[i].len; + hdr_offset = xinfo->xtract[i].hdr_off; + key_offset = xinfo->xtract[i].key_off; + + if (hdr_offset > 0 || nr_bytes < NPC_PF_FUNC_WIDTH) + continue; + else + pffunc_found = true; + + pf_func_offset = key_offset + nr_bytes - NPC_PF_FUNC_WIDTH; + memcpy((void *)&flow_mcam_data[pf_func_offset], (uint8_t *)&pf_func, + NPC_PF_FUNC_WIDTH); + memcpy((void *)&flow_mcam_mask[pf_func_offset], (uint8_t *)&mask, + NPC_PF_FUNC_WIDTH); + } + if (!pffunc_found) + return -EINVAL; + + return 0; +} + int -npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, - struct npc_parse_state *pst) +npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, struct npc_parse_state *pst) { struct npc_mcam_write_entry_req *req; struct nix_inl_dev *inl_dev = NULL; @@ -668,6 +706,16 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, */ req->entry_data.vtag_action = flow->vtag_action; + if (flow->nix_intf == NIX_INTF_TX) { + uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; + + pf_func = plt_cpu_to_be_16(pf_func); + + rc = npc_mcam_set_pf_func(npc, flow, pf_func); + if (rc) + return rc; + } + for (idx = 0; idx < ROC_NPC_MAX_MCAM_WIDTH_DWORDS; idx++) { req->entry_data.kw[idx] = flow->mcam_data[idx]; req->entry_data.kw_mask[idx] = flow->mcam_mask[idx]; @@ -718,15 +766,6 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, flow->mcam_mask[0] |= (0x7ULL << la_offset); } } - } else { - uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; - - pf_func = plt_cpu_to_be_16(pf_func); - req->entry_data.kw[0] |= ((uint64_t)pf_func << 32); - req->entry_data.kw_mask[0] |= ((uint64_t)0xffff << 32); - - flow->mcam_data[0] |= ((uint64_t)pf_func << 32); - flow->mcam_mask[0] |= ((uint64_t)0xffff << 32); } rc = mbox_process_msg(mbox, (void *)&rsp); diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c index f746b9cb6d..126bbd5358 100644 --- a/drivers/common/cnxk/roc_npc_parse.c +++ b/drivers/common/cnxk/roc_npc_parse.c @@ -180,6 +180,58 @@ npc_parse_higig2_hdr(struct npc_parse_state *pst) return npc_update_parse_state(pst, &info, lid, lt, 0); } +int +npc_parse_tx_queue(struct npc_parse_state *pst) +{ + struct nix_inst_hdr_s nix_inst_hdr, nix_inst_hdr_mask; + uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN]; + struct npc_parse_item_info parse_info; + const uint16_t *send_queue; + int lid, lt, rc = 0; + + memset(&nix_inst_hdr, 0, sizeof(nix_inst_hdr)); + memset(&nix_inst_hdr_mask, 0, sizeof(nix_inst_hdr_mask)); + memset(&parse_info, 0, sizeof(parse_info)); + + if (pst->pattern->type != ROC_NPC_ITEM_TYPE_TX_QUEUE) + return 0; + + if (pst->flow->nix_intf != NIX_INTF_TX) + return NPC_ERR_INVALID_SPEC; + + lid = NPC_LID_LA; + lt = NPC_LT_LA_IH_NIX_ETHER; + send_queue = (const uint16_t *)pst->pattern->spec; + + if (*send_queue >= pst->nb_tx_queues) + return NPC_ERR_INVALID_SPEC; + + nix_inst_hdr.sq = *send_queue; + nix_inst_hdr_mask.sq = 0xFFFF; + + parse_info.def_mask = NULL; + parse_info.spec = &nix_inst_hdr; + parse_info.mask = &nix_inst_hdr_mask; + parse_info.len = sizeof(nix_inst_hdr); + parse_info.def_mask = NULL; + parse_info.hw_hdr_len = 0; + + memset(hw_mask, 0, sizeof(hw_mask)); + + parse_info.hw_mask = &hw_mask; + npc_get_hw_supp_mask(pst, &parse_info, lid, lt); + + rc = npc_mask_is_supported(parse_info.mask, parse_info.hw_mask, parse_info.len); + if (!rc) + return NPC_ERR_INVALID_MASK; + + rc = npc_update_parse_state(pst, &parse_info, lid, lt, 0); + if (rc) + return rc; + + return 0; +} + int npc_parse_la(struct npc_parse_state *pst) { diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index 714dcb09c9..6f41df18bb 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -200,6 +200,7 @@ struct npc_parse_state { bool set_ipv6ext_ltype_mask; bool is_second_pass_rule; bool has_eth_type; + uint16_t nb_tx_queues; }; enum npc_kpu_parser_flag { @@ -448,6 +449,7 @@ int npc_parse_mark_item(struct npc_parse_state *pst); int npc_parse_pre_l2(struct npc_parse_state *pst); int npc_parse_higig2_hdr(struct npc_parse_state *pst); int npc_parse_cpt_hdr(struct npc_parse_state *pst); +int npc_parse_tx_queue(struct npc_parse_state *pst); int npc_parse_la(struct npc_parse_state *pst); int npc_parse_lb(struct npc_parse_state *pst); int npc_parse_lc(struct npc_parse_state *pst); From patchwork Fri May 19 03:42:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 127066 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43A4042B42; Fri, 19 May 2023 05:42:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E50542B8B; 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(unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 6BA563F7081; Thu, 18 May 2023 20:42:27 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Subject: [dpdk-dev] [PATCH 2/2] net/cnxk: support Tx queue flow pattern item Date: Fri, 19 May 2023 09:12:19 +0530 Message-ID: <20230519034219.2209868-2-psatheesh@marvell.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230519034219.2209868-1-psatheesh@marvell.com> References: <20230519034219.2209868-1-psatheesh@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 3cfwPcbJuhhuZFGVLGdq0FU8-3QPh4Ur X-Proofpoint-ORIG-GUID: 3cfwPcbJuhhuZFGVLGdq0FU8-3QPh4Ur X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-19_01,2023-05-17_02,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satheesh Paul Added support for Tx queue flow pattern item. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar K --- drivers/net/cnxk/cnxk_flow.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cnxk_flow.c b/drivers/net/cnxk/cnxk_flow.c index f13d8e5582..9595fe9386 100644 --- a/drivers/net/cnxk/cnxk_flow.c +++ b/drivers/net/cnxk/cnxk_flow.c @@ -58,7 +58,9 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW, sizeof(struct rte_flow_item_raw)}, [RTE_FLOW_ITEM_TYPE_MARK] = {ROC_NPC_ITEM_TYPE_MARK, - sizeof(struct rte_flow_item_mark)}}; + sizeof(struct rte_flow_item_mark)}, + [RTE_FLOW_ITEM_TYPE_TX_QUEUE] = {ROC_NPC_ITEM_TYPE_TX_QUEUE, + sizeof(struct rte_flow_item_tx_queue)}}; static int npc_rss_action_validate(struct rte_eth_dev *eth_dev,