From patchwork Thu May 18 15:16:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126995 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 733EB42AF1; Thu, 18 May 2023 17:34:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C23E842BFE; Thu, 18 May 2023 17:34:24 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 0B5914282D for ; Thu, 18 May 2023 17:34:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424063; x=1715960063; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ItzsL8iVrtPTT040biVYKQTbAPsDHRK2M4P3KOzopBg=; b=eO+Sl+SplBWC8ZJil+eRufKZWVM7TNkTjleswvxbr21Lmaop+gzp3wG6 59Evgp90sQrc8bGqkqK9uY5/FkAPUaNRL+tYGXOXaeQIwhe2ur0kDDTew wjiwcH7u+D15T8TZyzqPr2+w3bkRG3DtuBI2TFCZ3rljYRgDuknMLxyC1 YVDcKCZOQskv5hT9cKqfqSn5pkX/xcnIltdk7oqyx2jHAC9npMHuIE7jS Lrh1M/J0/QVu2KlOCAfAyZexxbbHqMD3ZG1t4I0O7HFeQu/ZwfJG/nfaW 7rGNSAmqEQpgOgNLI3RZw43X47Ktvwt4EIjmV/doNe4CO0HyK07EDypuH g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527620" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527620" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235034" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235034" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:20 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang Subject: [PATCH v2 01/20] net/ice/base: updated copyright Date: Thu, 18 May 2023 15:16:19 +0000 Message-Id: <20230518151638.1207021-2-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Updated copyright to 2023. Signed-off-by: Qiming Yang --- drivers/net/ice/base/README | 2 +- drivers/net/ice/base/ice_acl.c | 2 +- drivers/net/ice/base/ice_acl.h | 2 +- drivers/net/ice/base/ice_acl_ctrl.c | 2 +- drivers/net/ice/base/ice_adminq_cmd.h | 2 +- drivers/net/ice/base/ice_alloc.h | 2 +- drivers/net/ice/base/ice_bitops.h | 2 +- drivers/net/ice/base/ice_bst_tcam.c | 2 +- drivers/net/ice/base/ice_bst_tcam.h | 2 +- drivers/net/ice/base/ice_cgu_regs.h | 2 +- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_common.h | 2 +- drivers/net/ice/base/ice_controlq.c | 2 +- drivers/net/ice/base/ice_controlq.h | 2 +- drivers/net/ice/base/ice_dcb.c | 2 +- drivers/net/ice/base/ice_dcb.h | 2 +- drivers/net/ice/base/ice_ddp.c | 2 +- drivers/net/ice/base/ice_ddp.h | 2 +- drivers/net/ice/base/ice_defs.h | 2 +- drivers/net/ice/base/ice_devids.h | 2 +- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_flex_pipe.c | 2 +- drivers/net/ice/base/ice_flex_pipe.h | 2 +- drivers/net/ice/base/ice_flex_type.h | 2 +- drivers/net/ice/base/ice_flg_rd.c | 2 +- drivers/net/ice/base/ice_flg_rd.h | 2 +- drivers/net/ice/base/ice_flow.c | 2 +- drivers/net/ice/base/ice_flow.h | 2 +- drivers/net/ice/base/ice_hw_autogen.h | 2 +- drivers/net/ice/base/ice_imem.c | 2 +- drivers/net/ice/base/ice_imem.h | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 2 +- drivers/net/ice/base/ice_metainit.c | 2 +- drivers/net/ice/base/ice_metainit.h | 2 +- drivers/net/ice/base/ice_mk_grp.c | 2 +- drivers/net/ice/base/ice_mk_grp.h | 2 +- drivers/net/ice/base/ice_nvm.c | 2 +- drivers/net/ice/base/ice_nvm.h | 2 +- drivers/net/ice/base/ice_parser.c | 2 +- drivers/net/ice/base/ice_parser.h | 2 +- drivers/net/ice/base/ice_parser_rt.c | 2 +- drivers/net/ice/base/ice_parser_rt.h | 2 +- drivers/net/ice/base/ice_parser_util.h | 2 +- drivers/net/ice/base/ice_pg_cam.c | 2 +- drivers/net/ice/base/ice_pg_cam.h | 2 +- drivers/net/ice/base/ice_proto_grp.c | 2 +- drivers/net/ice/base/ice_proto_grp.h | 2 +- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_ptp_consts.h | 2 +- drivers/net/ice/base/ice_ptp_hw.c | 2 +- drivers/net/ice/base/ice_ptp_hw.h | 2 +- drivers/net/ice/base/ice_ptype_mk.c | 2 +- drivers/net/ice/base/ice_ptype_mk.h | 2 +- drivers/net/ice/base/ice_sbq_cmd.h | 2 +- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 2 +- drivers/net/ice/base/ice_status.h | 2 +- drivers/net/ice/base/ice_switch.c | 2 +- drivers/net/ice/base/ice_switch.h | 2 +- drivers/net/ice/base/ice_tmatch.h | 2 +- drivers/net/ice/base/ice_type.h | 2 +- drivers/net/ice/base/ice_vlan_mode.c | 2 +- drivers/net/ice/base/ice_vlan_mode.h | 2 +- drivers/net/ice/base/ice_xlt_kb.c | 2 +- drivers/net/ice/base/ice_xlt_kb.h | 2 +- 66 files changed, 66 insertions(+), 66 deletions(-) diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README index 0e37a5f7a1..d3b96e0fb4 100644 --- a/drivers/net/ice/base/README +++ b/drivers/net/ice/base/README @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020-2022 Intel Corporation + * Copyright(c) 2020-2023 Intel Corporation */ Intel® ICE driver diff --git a/drivers/net/ice/base/ice_acl.c b/drivers/net/ice/base/ice_acl.c index 23b6c608be..fd9c6d5c14 100644 --- a/drivers/net/ice/base/ice_acl.c +++ b/drivers/net/ice/base/ice_acl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_acl.h b/drivers/net/ice/base/ice_acl.h index b5f2ec04a4..ac703be0a1 100644 --- a/drivers/net/ice/base/ice_acl.h +++ b/drivers/net/ice/base/ice_acl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ACL_H_ diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c index 3a912f2aa0..2223a8313b 100644 --- a/drivers/net/ice/base/ice_acl_ctrl.c +++ b/drivers/net/ice/base/ice_acl_ctrl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 5a817982b4..65cba9ab37 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ADMINQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_alloc.h b/drivers/net/ice/base/ice_alloc.h index dca502ab25..6487cdc210 100644 --- a/drivers/net/ice/base/ice_alloc.h +++ b/drivers/net/ice/base/ice_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ALLOC_H_ diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index c4ae2b9c8e..5384e99415 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_BITOPS_H_ diff --git a/drivers/net/ice/base/ice_bst_tcam.c b/drivers/net/ice/base/ice_bst_tcam.c index 5cc0d12251..fbe106df60 100644 --- a/drivers/net/ice/base/ice_bst_tcam.c +++ b/drivers/net/ice/base/ice_bst_tcam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_bst_tcam.h b/drivers/net/ice/base/ice_bst_tcam.h index 292444c919..2fb2c8421e 100644 --- a/drivers/net/ice/base/ice_bst_tcam.h +++ b/drivers/net/ice/base/ice_bst_tcam.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_BST_TCAM_H_ diff --git a/drivers/net/ice/base/ice_cgu_regs.h b/drivers/net/ice/base/ice_cgu_regs.h index 6b9a359c5b..c44bfc1846 100644 --- a/drivers/net/ice/base/ice_cgu_regs.h +++ b/drivers/net/ice/base/ice_cgu_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_CGU_REGS_H_ diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 1a02aad869..fa30c50ca1 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 58260afb93..e1febfb0c4 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_COMMON_H_ diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 8971a140ef..c34407b48c 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 45fe70450e..986604ec3c 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_CONTROLQ_H_ diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index 0e604df541..2a308b02bf 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h index d010c539a6..bae033a460 100644 --- a/drivers/net/ice/base/ice_dcb.h +++ b/drivers/net/ice/base/ice_dcb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DCB_H_ diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index d1cae48047..93ff2608d4 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_ddp.h" diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 53bbbe2a5a..4896e85b91 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DDP_H_ diff --git a/drivers/net/ice/base/ice_defs.h b/drivers/net/ice/base/ice_defs.h index 6e886f6aac..210ce6263b 100644 --- a/drivers/net/ice/base/ice_defs.h +++ b/drivers/net/ice/base/ice_defs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DEFS_H_ diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 13a4b16402..f80789ebc5 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DEVIDS_H_ diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 85ca29bae5..3ed2a63b68 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index f338da38c2..81ba6008e4 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FDIR_H_ diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index b6bc0062a3..f9266447d9 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 9ba337e1fa..422d09becc 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLEX_PIPE_H_ diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 7b8f6f9049..c83479d6fa 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLEX_TYPE_H_ diff --git a/drivers/net/ice/base/ice_flg_rd.c b/drivers/net/ice/base/ice_flg_rd.c index f320958bd3..97f62e6cc4 100644 --- a/drivers/net/ice/base/ice_flg_rd.c +++ b/drivers/net/ice/base/ice_flg_rd.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flg_rd.h b/drivers/net/ice/base/ice_flg_rd.h index 8cd375f89f..c194a4f462 100644 --- a/drivers/net/ice/base/ice_flg_rd.h +++ b/drivers/net/ice/base/ice_flg_rd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLG_RD_H_ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 3483a5ed4f..5254ee27ed 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index dba71aab74..57e8e1f1df 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLOW_H_ diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 6dc77bf7cb..4610cec6a7 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ /* Machine generated file. Do not edit. */ diff --git a/drivers/net/ice/base/ice_imem.c b/drivers/net/ice/base/ice_imem.c index 277311fd20..f193aaf836 100644 --- a/drivers/net/ice/base/ice_imem.c +++ b/drivers/net/ice/base/ice_imem.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_imem.h b/drivers/net/ice/base/ice_imem.h index 06d3d5a96d..0328830b94 100644 --- a/drivers/net/ice/base/ice_imem.h +++ b/drivers/net/ice/base/ice_imem.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_IMEM_H_ diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index be6d88f0ca..d816df0ff6 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_LAN_TX_RX_H_ diff --git a/drivers/net/ice/base/ice_metainit.c b/drivers/net/ice/base/ice_metainit.c index b75d68c010..1e990c9aa0 100644 --- a/drivers/net/ice/base/ice_metainit.c +++ b/drivers/net/ice/base/ice_metainit.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_metainit.h b/drivers/net/ice/base/ice_metainit.h index dad4faf4d4..440932ae30 100644 --- a/drivers/net/ice/base/ice_metainit.h +++ b/drivers/net/ice/base/ice_metainit.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_METAINIT_H_ diff --git a/drivers/net/ice/base/ice_mk_grp.c b/drivers/net/ice/base/ice_mk_grp.c index cafe51544d..9de4527b58 100644 --- a/drivers/net/ice/base/ice_mk_grp.c +++ b/drivers/net/ice/base/ice_mk_grp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_mk_grp.h b/drivers/net/ice/base/ice_mk_grp.h index 9401647ef0..161dd724cb 100644 --- a/drivers/net/ice/base/ice_mk_grp.h +++ b/drivers/net/ice/base/ice_mk_grp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_MK_GRP_H_ diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 6550dda557..cb45cb8134 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index a8cda452db..c3e61a301f 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_NVM_H_ diff --git a/drivers/net/ice/base/ice_parser.c b/drivers/net/ice/base/ice_parser.c index a1b906d369..79c97f7903 100644 --- a/drivers/net/ice/base/ice_parser.c +++ b/drivers/net/ice/base/ice_parser.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_parser.h b/drivers/net/ice/base/ice_parser.h index b4c5e7b14d..0f64584898 100644 --- a/drivers/net/ice/base/ice_parser.h +++ b/drivers/net/ice/base/ice_parser.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_H_ diff --git a/drivers/net/ice/base/ice_parser_rt.c b/drivers/net/ice/base/ice_parser_rt.c index 215e11abd2..68c0f5d7fb 100644 --- a/drivers/net/ice/base/ice_parser_rt.c +++ b/drivers/net/ice/base/ice_parser_rt.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_parser_rt.h b/drivers/net/ice/base/ice_parser_rt.h index c1e1af0059..de851643b4 100644 --- a/drivers/net/ice/base/ice_parser_rt.h +++ b/drivers/net/ice/base/ice_parser_rt.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_RT_H_ diff --git a/drivers/net/ice/base/ice_parser_util.h b/drivers/net/ice/base/ice_parser_util.h index a33d6bf11c..9949b985ee 100644 --- a/drivers/net/ice/base/ice_parser_util.h +++ b/drivers/net/ice/base/ice_parser_util.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_UTIL_H_ diff --git a/drivers/net/ice/base/ice_pg_cam.c b/drivers/net/ice/base/ice_pg_cam.c index f06a3581a0..e6324945fb 100644 --- a/drivers/net/ice/base/ice_pg_cam.c +++ b/drivers/net/ice/base/ice_pg_cam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_pg_cam.h b/drivers/net/ice/base/ice_pg_cam.h index ac0863afb0..0412ac5ae2 100644 --- a/drivers/net/ice/base/ice_pg_cam.h +++ b/drivers/net/ice/base/ice_pg_cam.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PG_CAM_H_ diff --git a/drivers/net/ice/base/ice_proto_grp.c b/drivers/net/ice/base/ice_proto_grp.c index a9ed9e051f..94f4df0aaa 100644 --- a/drivers/net/ice/base/ice_proto_grp.c +++ b/drivers/net/ice/base/ice_proto_grp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_proto_grp.h b/drivers/net/ice/base/ice_proto_grp.h index 762d32464b..dc6d8a32a4 100644 --- a/drivers/net/ice/base/ice_proto_grp.h +++ b/drivers/net/ice/base/ice_proto_grp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PROTO_GRP_H_ diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index d17ab54bd3..eeaf044059 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PROTOCOL_TYPE_H_ diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h index ddf6242d8e..546bf8ba91 100644 --- a/drivers/net/ice/base/ice_ptp_consts.h +++ b/drivers/net/ice/base/ice_ptp_consts.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTP_CONSTS_H_ diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index a0b8af1b94..548ef5e820 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_type.h" diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 09c236e7e0..3667c9882d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTP_HW_H_ diff --git a/drivers/net/ice/base/ice_ptype_mk.c b/drivers/net/ice/base/ice_ptype_mk.c index 4cd8396167..6814095dbd 100644 --- a/drivers/net/ice/base/ice_ptype_mk.c +++ b/drivers/net/ice/base/ice_ptype_mk.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_ptype_mk.h b/drivers/net/ice/base/ice_ptype_mk.h index 3efe294dda..66427c6866 100644 --- a/drivers/net/ice/base/ice_ptype_mk.h +++ b/drivers/net/ice/base/ice_ptype_mk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTYPE_MK_H_ diff --git a/drivers/net/ice/base/ice_sbq_cmd.h b/drivers/net/ice/base/ice_sbq_cmd.h index a215303a56..4da16caf70 100644 --- a/drivers/net/ice/base/ice_sbq_cmd.h +++ b/drivers/net/ice/base/ice_sbq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SBQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index a526c8f32c..83cd152388 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_sched.h" diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 3724ef33a8..a71619ebf0 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SCHED_H_ diff --git a/drivers/net/ice/base/ice_status.h b/drivers/net/ice/base/ice_status.h index f52121c3a3..1965347a8b 100644 --- a/drivers/net/ice/base/ice_status.h +++ b/drivers/net/ice/base/ice_status.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_STATUS_H_ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e4eed66406..cd6237136e 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 949c94c0c3..7a12619459 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SWITCH_H_ diff --git a/drivers/net/ice/base/ice_tmatch.h b/drivers/net/ice/base/ice_tmatch.h index e70926acd1..a2df0c4367 100644 --- a/drivers/net/ice/base/ice_tmatch.h +++ b/drivers/net/ice/base/ice_tmatch.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_TMATCH_H_ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index bfec317b57..da813c8307 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_TYPE_H_ diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 74d414b3b8..7ee00df124 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_vlan_mode.h b/drivers/net/ice/base/ice_vlan_mode.h index 5e3f454a25..d2380eb94b 100644 --- a/drivers/net/ice/base/ice_vlan_mode.h +++ b/drivers/net/ice/base/ice_vlan_mode.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_VLAN_MODE_H_ diff --git a/drivers/net/ice/base/ice_xlt_kb.c b/drivers/net/ice/base/ice_xlt_kb.c index 59472a08d4..b8240946b4 100644 --- a/drivers/net/ice/base/ice_xlt_kb.c +++ b/drivers/net/ice/base/ice_xlt_kb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_xlt_kb.h b/drivers/net/ice/base/ice_xlt_kb.h index f870f18ed6..0cce33142a 100644 --- a/drivers/net/ice/base/ice_xlt_kb.h +++ b/drivers/net/ice/base/ice_xlt_kb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_XLT_KB_H_ From patchwork Thu May 18 15:16:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126996 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6E0542AF1; Thu, 18 May 2023 17:34:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B8ED42D39; Thu, 18 May 2023 17:34:26 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 7A9A742BAC for ; Thu, 18 May 2023 17:34:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424064; x=1715960064; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rRjXNMOWQwdabQoKOdLcfsNuLisbKRHwE5UQcnVgU1c=; b=XbKl3I7ntc32S2VJ5KlIeZfjgz6iiBAnqSPUe2k9fW96vLL5qq9Zd/+h GN8C5Pz/ZExGL82cS8PeqAaXdhuStJF22WklG7fplkyf1EO1WHY/aKRXv ggAHxl4Tiyufu0ClEiAhGfu5QAhTA3rgdPYEfi1mgYsYJn5cpy90+lpoc mqIvh/JSA0JcGg6URNEvAxnrp8djLab6fGJIyqpDP6Kr4umdFWu+MBRyd 0wcrCaD1RH5zAx2Ys5I89EbOS5CqGGTN3m/rc+NEO7e4PQFll2Zs3kDBb PgmqEyuizzN6I2Sjw3B5VqkipTbJAEks3BoNIK3spUIbT2awGDE9b+TSo Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527628" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527628" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235042" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235042" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:22 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Grzegorz Nitka Subject: [PATCH v2 02/20] net/ice/base: add NAC Topology device capability parser Date: Thu, 18 May 2023 15:16:20 +0000 Message-Id: <20230518151638.1207021-3-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define and add parsing support for new device capability ICE_AQC_CAPS_NAC_TOPOLOGY. Signed-off-by: Grzegorz Nitka Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 26 ++++++++++++++++++++++++++ drivers/net/ice/base/ice_type.h | 10 ++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index fa30c50ca1..ede46820cd 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2807,6 +2807,29 @@ ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, dev_p->num_flow_director_fltr); } +/** + * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap + * @hw: pointer to the HW struct + * @dev_p: pointer to device capabilities structure + * @cap: capability element to parse + * + * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. + */ +static void +ice_parse_nac_topo_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, + struct ice_aqc_list_caps_elem *cap) +{ + dev_p->nac_topo.mode = LE32_TO_CPU(cap->number); + dev_p->nac_topo.id = LE32_TO_CPU(cap->phys_id) & ICE_NAC_TOPO_ID_M; + + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", + dev_p->nac_topo.id); +} + /** * ice_parse_dev_caps - Parse device capabilities * @hw: pointer to the HW struct @@ -2852,6 +2875,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, case ICE_AQC_CAPS_FD: ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); break; + case ICE_AQC_CAPS_NAC_TOPOLOGY: + ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); + break; default: /* Don't list common capabilities as unknown */ if (!found) diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index da813c8307..c653c1de3e 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -693,6 +693,15 @@ struct ice_ts_dev_info { u8 ts_ll_read : 1; }; +#define ICE_NAC_TOPO_PRIMARY_M BIT(0) +#define ICE_NAC_TOPO_DUAL_M BIT(1) +#define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0) + +struct ice_nac_topology { + u32 mode; + u8 id; +}; + /* Function specific capabilities */ struct ice_hw_func_caps { struct ice_hw_common_caps common_cap; @@ -709,6 +718,7 @@ struct ice_hw_dev_caps { u32 num_flow_director_fltr; /* Number of FD filters available */ struct ice_ts_dev_info ts_dev_info; u32 num_funcs; + struct ice_nac_topology nac_topo; }; /* Information about MAC such as address, etc... */ From patchwork Thu May 18 15:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126997 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCF0042AF1; Thu, 18 May 2023 17:34:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7D35942D2F; Thu, 18 May 2023 17:34:28 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 9618242D17 for ; Thu, 18 May 2023 17:34:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424065; x=1715960065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PBl0cPz43ct1ql8cZy6r5hju3Bpjh0uqxoj0VBMzFbQ=; b=B2u8wvR55B9Bx/5zq8qo8nM3WGNhXEYMR81pZtrpONTGUzBJw1mGklXc DGfSNLXMrWlEFzohvjemB4B8EtXPWB6UGEi/3WLqqXztOPgU/+NP5hDAU 7EyIolDTo+tCer67R0xgKdfh+//Yo90Fd64ZOkO8LajBEGUrsa4SoPtCG aYW++GJfFioEdMijUDLED1+2pIR8yNT5ohhnHHA46XwJ41fAoc4JACJKq /bRyUlqGTGb8Psi8ld/4ga3AfNLbT/L9u3cfVeyS0weC9p2pUL/0eGxij j5Q7n6KYlMkF18SuNCOzAmq1bASUssn/DSxEIY/VxmyOqozL0V6rZ31AI A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527632" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527632" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235053" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235053" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:24 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Milena Olech Subject: [PATCH v2 03/20] net/ice/base: add new device for E810 Date: Thu, 18 May 2023 15:16:21 +0000 Message-Id: <20230518151638.1207021-4-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org New subsystem ID is introduced for E810 NIC Signed-off-by: Milena Olech Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 1 + drivers/net/ice/base/ice_devids.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ede46820cd..bcfd8e458d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -223,6 +223,7 @@ bool ice_is_e810t(struct ice_hw *hw) case ICE_SUBDEV_ID_E810T3: case ICE_SUBDEV_ID_E810T4: case ICE_SUBDEV_ID_E810T5: + case ICE_SUBDEV_ID_E810T7: return true; } break; diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index f80789ebc5..83af3c3b05 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -27,6 +27,7 @@ #define ICE_SUBDEV_ID_E810T4 0x02EA #define ICE_SUBDEV_ID_E810T5 0x0010 #define ICE_SUBDEV_ID_E810T6 0x0012 +#define ICE_SUBDEV_ID_E810T7 0x0011 /* Intel(R) Ethernet Controller E810-XXV for backplane */ #define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599 /* Intel(R) Ethernet Controller E810-XXV for QSFP */ From patchwork Thu May 18 15:16:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126998 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E678342AF1; Thu, 18 May 2023 17:34:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9558042D40; Thu, 18 May 2023 17:34:29 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 0D02642D3D for ; Thu, 18 May 2023 17:34:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424067; x=1715960067; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j2RayQRvfgwrkGYv1bvlbpB6m/K8gp02WOTn2xZt9Wc=; b=AjHF6ZgIQOCx1thcrEk/DNtbUqGC5vAol9PD526st4icew97MXgKZ3vo oRYZqjgk3CAA43XFvxmsKun+yuj9J8dF6xrIOiIlcbZE+sIXp6ond+Q0d xXVfTGQRzQ+ZYbRGfgoEUB7zDY4iau1TilZ6FkV2C7LaNYD43qs124tY9 gPdo9pjjPKvMNDip9cdcHu/b3DZMMZJZk5uQqI2/n0jIvEcoeYnj+SEBx Byva96xOyFe6khGkHpKZABJPGqDpAnWwf/Vhl6YKow6DNobaEw0Elrxtk /1U9TCy+AiFuDxNN3TwUbUv1ZbEV0xdK4aLl11iB7z+WCQPuudfYkN2QG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527647" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527647" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235058" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235058" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:25 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Dave Ertman Subject: [PATCH v2 04/20] net/ice/base: fix incorrect defines for DCBx Date: Thu, 18 May 2023 15:16:22 +0000 Message-Id: <20230518151638.1207021-5-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In all cases but one, CEE mode is defined as 0x01 and IEEE mode is defined as 0x02. in past these values were swapped. This is causing the DCB information sent from the FW agent to be parsed with incorrect structures and resulting in incorrect values. Change the defines to match what they are in the rest of the kernel. Fixes: 97e32e8d4870 ("net/ice/base: complete pending LLDP MIB") Signed-off-by: Dave Ertman Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 65cba9ab37..8df6ca41e9 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2002,8 +2002,8 @@ struct ice_aqc_lldp_get_mib { #define ICE_AQ_LLDP_DCBX_S 6 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S) #define ICE_AQ_LLDP_DCBX_NA 0 -#define ICE_AQ_LLDP_DCBX_IEEE 1 -#define ICE_AQ_LLDP_DCBX_CEE 2 +#define ICE_AQ_LLDP_DCBX_CEE 1 +#define ICE_AQ_LLDP_DCBX_IEEE 2 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) * and in the LLDP MIB Change Event (0x0A01). They are valid for the * Get LLDP MIB (0x0A00) response only. From patchwork Thu May 18 15:16:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126999 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C62E42AF1; Thu, 18 May 2023 17:35:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8BE142D47; Thu, 18 May 2023 17:34:30 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5268C42D2D for ; Thu, 18 May 2023 17:34:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424068; x=1715960068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IO5PT5CPJ9BSU4hdc+3VVIb1DZdKE2cky/DBcLtln7Y=; b=l5wG8TfkqBVpdfGJ2+8BLiKBPZprQTqMfeG1ielsFfkcSCL58lvmuuxK AGA+10DOiZiFg6po1j7SuXAc9FZsKwO37rPHQNCUMM3fHGTpvNcANuY0C 46WmLbV4nTcqFdK8Rihcp8A4VmPedT23nlgX4ol6QvwdZ8l5ylZcEfcnd HRRyJiyg+IqCreOHHUrXqCv7NzmmzIqpn+94ruzGEdMrg/W5Ty/e4onYt rHS3ZIIVuMbZJ5d8FaV6LMbWhkgh/q6wusF7JLfct1tTl41FzgRgi56uk JwwtdIvDmzRjpri/GRqvwjeOg8WOJsEYTLu0N2MAvXMkat7H7H1JalRyd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527655" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527655" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235070" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235070" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:26 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Wojciech Drewek Subject: [PATCH v2 05/20] net/ice/base: introduce a non-atomic function Date: Thu, 18 May 2023 15:16:23 +0000 Message-Id: <20230518151638.1207021-6-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org recipe_bitmap is not aligned to 8 bytes in ice_aqc_recipe_data_elem structure and set_bit is a atomic operation we end up with a split lock. The reason for this is that recipe_bitmap might end up being in two cache lines because it's not aligned. Fix this by introducing non-atomic function ice_set_recipe_index to replace ice_set_bit in this specific case. Signed-off-by: Wojciech Drewek Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_bitops.h | 7 +++++++ drivers/net/ice/base/ice_switch.c | 19 +++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index 5384e99415..df00c859ac 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -11,6 +11,13 @@ /* Define the size of the bitmap chunk */ typedef u32 ice_bitmap_t; +/* NOTE! + * Do not use any of the functions declared in this file + * on memory that was not declared with ice_declare_bitmap. + * Not following this rule might cause issues like split + * locks. + */ + /* Number of bits per bitmap chunk */ #define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t)) /* Determine which chunk a bit belongs in */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index cd6237136e..c71861a36d 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7163,6 +7163,17 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles, return (u16)ice_bitmap_hweight(free_idx, ICE_MAX_FV_WORDS); } +static void ice_set_recipe_index(unsigned long idx, u8 *bitmap) +{ + u32 byte = idx / BITS_PER_BYTE; + u32 bit = idx % BITS_PER_BYTE; + + if (byte >= 8) + return; + + bitmap[byte] |= 1 << bit; +} + /** * ice_add_sw_recipe - function to call AQ calls to create switch recipe * @hw: pointer to hardware structure @@ -7290,10 +7301,10 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm, } /* fill recipe dependencies */ - ice_zero_bitmap((ice_bitmap_t *)buf[recps].recipe_bitmap, - ICE_MAX_NUM_RECIPES); - ice_set_bit(buf[recps].recipe_indx, - (ice_bitmap_t *)buf[recps].recipe_bitmap); + ice_memset(buf[recps].recipe_bitmap, 0, + sizeof(buf[recps].recipe_bitmap), ICE_NONDMA_MEM); + ice_set_recipe_index(buf[recps].recipe_indx, + buf[recps].recipe_bitmap); buf[recps].content.act_ctrl_fwd_priority = rm->priority; recps++; } From patchwork Thu May 18 15:16:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127000 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F4E842AF1; Thu, 18 May 2023 17:35:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B570842D4B; Thu, 18 May 2023 17:34:31 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 9220F42D44 for ; Thu, 18 May 2023 17:34:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424070; x=1715960070; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hN6Fu8K+AMWDvv/cKpPmtPBcgZ6U0WjcmXofsz80eY4=; b=dXQed6zxbztG+cFZY9lYcsDPKgcPWIyRBg5nwbaioH8AEXV2ic7DZiPo 4QQod3ZJFkgkkvZQzzS2Bahvcp+kXLZn+Yp8Nnd0TXJhLIMlEN8Ij4YmN JD8dR9G1nXWtg5FbjXpWDITdul1Z0jKJSPYjSoRne9l+Eos9WbZzqcWyt UZlGNy9WPmZViI+8KwceKHz8HgzGfmWvMH4vj41XhgoohLcoUti1aiCfs IYSKc91M9gq/Ccc1oD273EZQ3ze2A4cBPeZO5kA+XGppM4qO39ss5x/75 UTJHalwkE5tsaTyhxDeQOzGxXqcKO8DNbZ4xHXVQcYeMehWmzygB1O3dy A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527662" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527662" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235082" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235082" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:27 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Eric Joyner Subject: [PATCH v2 06/20] net/ice/base: add missing AQ flag to AQ command Date: Thu, 18 May 2023 15:16:24 +0000 Message-Id: <20230518151638.1207021-7-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The RD flag needs to be set when virtual port rules are added since the FW needs to read the additional buffer with the mirror rule parameters. Signed-off-by: Eric Joyner Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index c71861a36d..f201c287fc 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -3134,6 +3134,8 @@ ice_aq_add_update_mir_rule(struct ice_hw *hw, u16 rule_type, u16 dest_vsi, else /* remove VSI from mirror rule */ mr_list[i] = CPU_TO_LE16(id); } + + desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); } cmd = &desc.params.add_update_rule; From patchwork Thu May 18 15:16:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127001 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9359342AF1; Thu, 18 May 2023 17:35:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA4A342D4F; Thu, 18 May 2023 17:34:32 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 6FDA742D38 for ; Thu, 18 May 2023 17:34:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424071; x=1715960071; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tbiaUYc52V1qoFex36TpdQN/1uWHmtT+l7RrCHi+2I4=; b=LtUEgwPocvyicVa7RUKh4wlIBs8g7dFsnI4LY4JZGDP3CPDz6xqNy+l/ V+BsFatwKyanVBOYcw8Nxz4xSP4kCfqAdID2wlztrXA8OilX6dVc7IQ8V mR+1LCH+aJ+KtPUevHjdWX1Uhd9ozoRFw39e4QPTEoI0Jv+fv+zOnJnOC vRJSiZuJdYIe0WsTqqg8wjWlxYY+ic9l6S8PEcQAwY2tuczaLvGUiTvgG 8jC6eoDH0+FkJpfR/0BPvRgUN5jiUNXzW2GCm+lB8xgJzo5PO0CjiIc5L Ub/oVMtpQxnLCwvvbuHZI2Wxps1VtAVjZj5v7B9xFN2WbLt8zHyjMTGCz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527670" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527670" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235089" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235089" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:29 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Martyna Szapar-Mudlaw Subject: [PATCH v2 07/20] net/ice/base: add support for inner etype in switchdev Date: Thu, 18 May 2023 15:16:25 +0000 Message-Id: <20230518151638.1207021-8-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable support for adding TC rules that filter on the inner EtherType field of tunneled packet headers. Signed-off-by: Martyna Szapar-Mudlaw Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_protocol_type.h | 2 + drivers/net/ice/base/ice_switch.c | 270 ++++++++++++++++++++++- 2 files changed, 268 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index eeaf044059..8c57cd2081 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -31,6 +31,7 @@ enum ice_protocol_type { ICE_MAC_OFOS = 0, ICE_MAC_IL, ICE_ETYPE_OL, + ICE_ETYPE_IL, ICE_VLAN_OFOS, ICE_IPV4_OFOS, ICE_IPV4_IL, @@ -197,6 +198,7 @@ enum ice_prot_id { #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 +#define ICE_ETYPE_IL_HW 10 #define ICE_VLAN_OF_HW 16 #define ICE_VLAN_OL_HW 17 #define ICE_IPV4_OFOS_HW 32 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index f201c287fc..a9f3ae5bf5 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -49,6 +49,7 @@ static const struct ice_dummy_pkt_offsets dummy_gre_tcp_packet_offsets[] = { { ICE_IPV4_OFOS, 14 }, { ICE_NVGRE, 34 }, { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, { ICE_IPV4_IL, 56 }, { ICE_TCP_IL, 76 }, { ICE_PROTOCOL_LAST, 0 }, @@ -73,7 +74,8 @@ static const u8 dummy_gre_tcp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 54 */ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, @@ -94,6 +96,7 @@ static const struct ice_dummy_pkt_offsets dummy_gre_udp_packet_offsets[] = { { ICE_IPV4_OFOS, 14 }, { ICE_NVGRE, 34 }, { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, { ICE_IPV4_IL, 56 }, { ICE_UDP_ILOS, 76 }, { ICE_PROTOCOL_LAST, 0 }, @@ -118,7 +121,8 @@ static const u8 dummy_gre_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 54 */ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, @@ -139,6 +143,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { { ICE_GENEVE, 42 }, { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, { ICE_IPV4_IL, 64 }, { ICE_TCP_IL, 84 }, { ICE_PROTOCOL_LAST, 0 }, @@ -166,7 +171,8 @@ static const u8 dummy_udp_tun_tcp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 62*/ 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_IL 64 */ 0x00, 0x01, 0x00, 0x00, @@ -190,6 +196,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = { { ICE_GENEVE, 42 }, { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, { ICE_IPV4_IL, 64 }, { ICE_UDP_ILOS, 84 }, { ICE_PROTOCOL_LAST, 0 }, @@ -217,7 +224,8 @@ static const u8 dummy_udp_tun_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 62 */ 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 64 */ 0x00, 0x01, 0x00, 0x00, @@ -229,6 +237,224 @@ static const u8 dummy_udp_tun_udp_packet[] = { 0x00, 0x08, 0x00, 0x00, }; +static const struct ice_dummy_pkt_offsets +dummy_gre_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_NVGRE, 34 }, + { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, + { ICE_IPV6_IL, 56 }, + { ICE_TCP_IL, 96 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x66, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x2F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 54 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */ + 0x00, 0x08, 0x06, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 96 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_NVGRE, 34 }, + { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, + { ICE_IPV6_IL, 56 }, + { ICE_UDP_ILOS, 96 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x5a, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x2F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 54 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */ + 0x00, 0x08, 0x11, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 96 */ + 0x00, 0x08, 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_udp_tun_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, + { ICE_IPV6_IL, 64 }, + { ICE_TCP_IL, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x6e, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x5a, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 62 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */ + 0x00, 0x08, 0x06, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 104 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const struct ice_dummy_pkt_offsets +dummy_udp_tun_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, + { ICE_IPV6_IL, 64 }, + { ICE_UDP_ILOS, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x62, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x4e, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 62 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */ + 0x00, 0x08, 0x11, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 104 */ + 0x00, 0x08, 0x00, 0x00, +}; + /* offset info for MAC + IPv4 + UDP dummy packet */ static const struct ice_dummy_pkt_offsets dummy_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, @@ -8065,6 +8291,7 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, const struct ice_dummy_pkt_offsets **offsets) { bool tcp = false, udp = false, outer_ipv6 = false, vlan = false; + bool inner_ipv6 = false; bool cvlan = false; bool gre = false, mpls = false; u16 i; @@ -8088,6 +8315,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, lkups[i].m_u.ethertype.ethtype_id == CPU_TO_BE16(0xFFFF)) outer_ipv6 = true; + else if (lkups[i].type == ICE_ETYPE_IL && + lkups[i].h_u.ethertype.ethtype_id == + CPU_TO_BE16(ICE_IPV6_ETHER_ID) && + lkups[i].m_u.ethertype.ethtype_id == + CPU_TO_BE16(0xFFFF)) + inner_ipv6 = true; else if (lkups[i].type == ICE_IPV4_OFOS && lkups[i].h_u.ipv4_hdr.protocol == ICE_IPV4_NVGRE_PROTO_ID && @@ -8441,6 +8674,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } if (tun_type == ICE_SW_TUN_NVGRE || gre) { + if (tcp && inner_ipv6) { + *pkt = dummy_gre_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_gre_ipv6_tcp_packet); + *offsets = dummy_gre_ipv6_tcp_packet_offsets; + return; + } + if (tcp) { *pkt = dummy_gre_tcp_packet; *pkt_len = sizeof(dummy_gre_tcp_packet); @@ -8448,6 +8688,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (inner_ipv6) { + *pkt = dummy_gre_ipv6_udp_packet; + *pkt_len = sizeof(dummy_gre_ipv6_udp_packet); + *offsets = dummy_gre_ipv6_udp_packet_offsets; + return; + } + *pkt = dummy_gre_udp_packet; *pkt_len = sizeof(dummy_gre_udp_packet); *offsets = dummy_gre_udp_packet_offsets; @@ -8458,6 +8705,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, tun_type == ICE_SW_TUN_VXLAN_GPE || tun_type == ICE_SW_TUN_UDP || tun_type == ICE_SW_TUN_GENEVE_VLAN || tun_type == ICE_SW_TUN_VXLAN_VLAN) { + if (tcp && inner_ipv6) { + *pkt = dummy_udp_tun_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_tcp_packet); + *offsets = dummy_udp_tun_ipv6_tcp_packet_offsets; + return; + } + if (tcp) { *pkt = dummy_udp_tun_tcp_packet; *pkt_len = sizeof(dummy_udp_tun_tcp_packet); @@ -8465,6 +8719,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (inner_ipv6) { + *pkt = dummy_udp_tun_ipv6_udp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_udp_packet); + *offsets = dummy_udp_tun_ipv6_udp_packet_offsets; + return; + } + *pkt = dummy_udp_tun_udp_packet; *pkt_len = sizeof(dummy_udp_tun_udp_packet); *offsets = dummy_udp_tun_udp_packet_offsets; @@ -8574,6 +8835,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, len = sizeof(struct ice_ether_hdr); break; case ICE_ETYPE_OL: + case ICE_ETYPE_IL: len = sizeof(struct ice_ethtype_hdr); break; case ICE_VLAN_OFOS: From patchwork Thu May 18 15:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127002 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 261FC42AF1; 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a="341527686" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527686" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235109" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235109" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:30 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Szycik , Lukasz Plachno Subject: [PATCH v2 08/20] net/ice/base: add support for PPPoE hardware offload Date: Thu, 18 May 2023 15:16:26 +0000 Message-Id: <20230518151638.1207021-9-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for creating PPPoE filters in switchdev mode. Add support for parsing PPPoE and PPP-specific tc options: pppoe_sid and ppp_proto. Signed-off-by: Marcin Szycik Signed-off-by: Lukasz Plachno Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_bitops.h | 2 +- drivers/net/ice/base/ice_ddp.c | 4 ++- drivers/net/ice/base/ice_switch.c | 46 +++++++++++++++++++++++-------- 3 files changed, 38 insertions(+), 14 deletions(-) diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index df00c859ac..3b71c1b7f5 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -433,7 +433,7 @@ ice_bitmap_hweight(ice_bitmap_t *bm, u16 size) } /** - * ice_cmp_bitmaps - compares two bitmaps. + * ice_cmp_bitmap - compares two bitmaps. * @bmp1: the bitmap to compare * @bmp2: the bitmap to compare with bmp1 * @size: Size of the bitmaps in bits diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 93ff2608d4..3e18f2bc70 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -1623,8 +1623,10 @@ ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, } } } while (fv); - if (LIST_EMPTY(fv_list)) + if (LIST_EMPTY(fv_list)) { + ice_warn(hw, "Required profiles not found in currently loaded DDP package"); return ICE_ERR_CFG; + } return ICE_SUCCESS; err: diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index a9f3ae5bf5..e290a845bc 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1775,7 +1775,7 @@ static const u8 dummy_pppoe_ipv6_packet[] = { }; static const -struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_tcp_offsets[] = { +struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_tcp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_VLAN_OFOS, 12 }, { ICE_ETYPE_OL, 16 }, @@ -1820,7 +1820,7 @@ static const u8 dummy_pppoe_ipv6_tcp_packet[] = { }; static const -struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_udp_offsets[] = { +struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_VLAN_OFOS, 12 }, { ICE_ETYPE_OL, 16 }, @@ -8291,7 +8291,7 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, const struct ice_dummy_pkt_offsets **offsets) { bool tcp = false, udp = false, outer_ipv6 = false, vlan = false; - bool inner_ipv6 = false; + bool inner_ipv6 = false, pppoe = false; bool cvlan = false; bool gre = false, mpls = false; u16 i; @@ -8321,18 +8321,20 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, lkups[i].m_u.ethertype.ethtype_id == CPU_TO_BE16(0xFFFF)) inner_ipv6 = true; + else if (lkups[i].type == ICE_PPPOE) { + pppoe = true; + if (lkups[i].h_u.pppoe_hdr.ppp_prot_id == + CPU_TO_BE16(ICE_PPP_IPV6_PROTO_ID) && + lkups[i].m_u.pppoe_hdr.ppp_prot_id == + CPU_TO_BE16(0xFFFF)) + outer_ipv6 = true; + } else if (lkups[i].type == ICE_IPV4_OFOS && lkups[i].h_u.ipv4_hdr.protocol == ICE_IPV4_NVGRE_PROTO_ID && lkups[i].m_u.ipv4_hdr.protocol == 0xFF) gre = true; - else if (lkups[i].type == ICE_PPPOE && - lkups[i].h_u.pppoe_hdr.ppp_prot_id == - CPU_TO_BE16(ICE_PPP_IPV6_PROTO_ID) && - lkups[i].m_u.pppoe_hdr.ppp_prot_id == - 0xFFFF) - outer_ipv6 = true; else if (lkups[i].type == ICE_IPV4_IL && lkups[i].h_u.ipv4_hdr.protocol == ICE_TCP_PROTO_ID && @@ -8627,14 +8629,14 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, if (tun_type == ICE_SW_TUN_PPPOE_IPV6_TCP) { *pkt = dummy_pppoe_ipv6_tcp_packet; *pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet); - *offsets = dummy_pppoe_packet_ipv6_tcp_offsets; + *offsets = dummy_pppoe_ipv6_tcp_packet_offsets; return; } if (tun_type == ICE_SW_TUN_PPPOE_IPV6_UDP) { *pkt = dummy_pppoe_ipv6_udp_packet; *pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet); - *offsets = dummy_pppoe_packet_ipv6_udp_offsets; + *offsets = dummy_pppoe_ipv6_udp_packet_offsets; return; } @@ -8738,6 +8740,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_udp_packet); *offsets = dummy_vlan_udp_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv4_udp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv4_udp_packet); + *offsets = dummy_pppoe_ipv4_udp_packet_offsets; + return; } *pkt = dummy_udp_packet; *pkt_len = sizeof(dummy_udp_packet); @@ -8749,6 +8756,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_udp_ipv6_packet); *offsets = dummy_vlan_udp_ipv6_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv6_udp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet); + *offsets = dummy_pppoe_ipv6_udp_packet_offsets; + return; } *pkt = dummy_udp_ipv6_packet; *pkt_len = sizeof(dummy_udp_ipv6_packet); @@ -8760,6 +8772,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_tcp_ipv6_packet); *offsets = dummy_vlan_tcp_ipv6_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet); + *offsets = dummy_pppoe_ipv6_tcp_packet_offsets; + return; } *pkt = dummy_tcp_ipv6_packet; *pkt_len = sizeof(dummy_tcp_ipv6_packet); @@ -8771,7 +8788,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt = dummy_vlan_tcp_packet; *pkt_len = sizeof(dummy_vlan_tcp_packet); *offsets = dummy_vlan_tcp_packet_offsets; - } else if (mpls) { + } else if (pppoe) { + *pkt = dummy_pppoe_ipv4_tcp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv4_tcp_packet); + *offsets = dummy_pppoe_ipv4_tcp_packet_offsets; + return; + } else if (mpls) { *pkt = dummy_mpls_packet; *pkt_len = sizeof(dummy_mpls_packet); *offsets = dummy_mpls_packet_offsets; From patchwork Thu May 18 15:16:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127003 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A3C4642AF1; Thu, 18 May 2023 17:35:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2398542D69; Thu, 18 May 2023 17:34:36 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 98AD44014F for ; Thu, 18 May 2023 17:34:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; 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d="scan'208";a="705235115" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:32 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Szycik Subject: [PATCH v2 09/20] net/ice/base: remove direction metadata for switchdev Date: Thu, 18 May 2023 15:16:27 +0000 Message-Id: <20230518151638.1207021-10-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ICE_SW_TUN_AND_NON_TUN tunnel type is used by switchdev for default MAC rules. Currently a "special word" is added to recipes for such tunnels, specifying that rule should work only in ingress direction. Because of this, all egress traffic from VF is being dropped. To fix that, add a field add_dir_lkup to ice_adv_rule_info struct (will be set in CORE before calling ice_add_adv_rule()). Signed-off-by: Marcin Szycik Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 20 +++++++++++++------- drivers/net/ice/base/ice_switch.h | 1 + 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e290a845bc..c5951b5d40 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7754,13 +7754,14 @@ ice_get_fv(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, /** * ice_tun_type_match_word - determine if tun type needs a match mask - * @tun_type: tunnel type + * @rinfo: other information regarding the rule e.g. priority and action info * @off: offset of packet flag * @mask: mask to be used for the tunnel */ -static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, u16 *mask) +static bool +ice_tun_type_match_word(struct ice_adv_rule_info *rinfo, u16 *off, u16 *mask) { - switch (tun_type) { + switch (rinfo->tun_type) { case ICE_SW_TUN_VXLAN_GPE: case ICE_SW_TUN_GENEVE: case ICE_SW_TUN_VXLAN: @@ -7778,9 +7779,14 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, return true; case ICE_SW_TUN_AND_NON_TUN: - *mask = ICE_DIR_FLAG_MASK; - *off = ICE_TUN_FLAG_MDID_OFF(0); - return true; + if (rinfo->add_dir_lkup) { + *mask = ICE_DIR_FLAG_MASK; + *off = ICE_TUN_FLAG_MDID_OFF(0); + return true; + } + *mask = 0; + *off = 0; + return false; case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: @@ -7811,7 +7817,7 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, * tunnel bit in the packet metadata flags. If this is a tun_and_non_tun * packet, then add recipe index to match the direction bit in the flag. */ - if (ice_tun_type_match_word(rinfo->tun_type, &off, &mask)) { + if (ice_tun_type_match_word(rinfo, &off, &mask)) { if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) { u8 word = lkup_exts->n_val_words++; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 7a12619459..7421e02466 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -311,6 +311,7 @@ struct ice_adv_rule_info { struct ice_sw_act_ctrl sw_act; u32 priority; u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */ + u8 add_dir_lkup; u16 fltr_rule_id; u16 lg_id; struct ice_adv_rule_flags_info flags_info; From patchwork Thu May 18 15:16:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA42042AF1; Thu, 18 May 2023 17:35:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C7CD42D73; Thu, 18 May 2023 17:34:37 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E3ACF42D65 for ; Thu, 18 May 2023 17:34:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424076; x=1715960076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lb333tuOyBEOQbOnkVopabBBEkYV2Wf9LkCqHnXVZ3E=; b=ihuk8J4F6JvsQq0nhckteDMoAADdGF8M/rV7t9i/cCe7k0SO5t06BjcA NveVdHrQoaM2QUnF6J0INKtGTpsY05ZokAXWmlPjO2l3C8+u2J4ndzDlK 7+EASfB4mnjbW+FPOzSO00UdhfYSi0XeMWOonNNG7SXDbWOAaF5+1Aegy ynWCL8lae0o7ObO8FY8qc/2KKYKGbBn+u20FwJlrRhW3o14layTNgy6KZ yr2FrISZHrMDDMlRyY9muH98emFC8WjBYadJelcSTjoIheXlC727QXEZ1 UvoO19hjMG1GrzDyfI+PX0VS3wWqFrMxEfqAUHRbsbDEaoexOrQdw5Nc3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527700" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527700" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235127" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235127" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:34 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jacob Keller Subject: [PATCH v2 10/20] net/ice/base: reduce time to read Option data Date: Thu, 18 May 2023 15:16:28 +0000 Message-Id: <20230518151638.1207021-11-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Re-write ice_get_orom_civd_data to allocate memory to store the Option ROM data. This change significantly reduces the time to read the Option ROM CIVD section from ~10 seconds down to ~1 second. Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_nvm.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index cb45cb8134..e46aded12a 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -724,43 +724,67 @@ static enum ice_status ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_civd_info *civd) { - struct ice_orom_civd_info tmp; + u8 *orom_data; + enum ice_status status; u32 offset; /* The CIVD section is located in the Option ROM aligned to 512 bytes. * The first 4 bytes must contain the ASCII characters "$CIV". * A simple modulo 256 sum of all of the bytes of the structure must * equal 0. + * + * The exact location is unknown and varies between images but is + * usually somewhere in the middle of the bank. We need to scan the + * Option ROM bank to locate it. + * + * It's significantly faster to read the entire Option ROM up front + * using the maximum page size, than to read each possible location + * with a separate firmware command. */ + orom_data = (u8 *)ice_calloc(hw, hw->flash.banks.orom_size, sizeof(u8)); + if (!orom_data) + return ICE_ERR_NO_MEMORY; + + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0, + orom_data, hw->flash.banks.orom_size); + if (status) { + ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n"); + return status; + } + + /* Scan the memory buffer to locate the CIVD data section */ for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { - enum ice_status status; + struct ice_orom_civd_info *tmp; u8 sum = 0, i; - status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, - offset, (u8 *)&tmp, sizeof(tmp)); - if (status) { - ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n"); - return status; - } + tmp = (struct ice_orom_civd_info *)&orom_data[offset]; /* Skip forward until we find a matching signature */ - if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0) + if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0) continue; + ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n", + offset); + /* Verify that the simple checksum is zero */ - for (i = 0; i < sizeof(tmp); i++) - sum += ((u8 *)&tmp)[i]; + for (i = 0; i < sizeof(*tmp); i++) + sum += ((u8 *)tmp)[i]; if (sum) { ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n", sum); - return ICE_ERR_NVM; + goto err_invalid_checksum; } - *civd = tmp; + *civd = *tmp; + ice_free(hw, orom_data); return ICE_SUCCESS; } + ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n"); + +err_invalid_checksum: + ice_free(hw, orom_data); return ICE_ERR_NVM; } From patchwork Thu May 18 15:16:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127005 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CA21B42AF1; Thu, 18 May 2023 17:35:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D42D42D75; Thu, 18 May 2023 17:34:39 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 76DFC42D17 for ; Thu, 18 May 2023 17:34:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424077; x=1715960077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RjueX4W3CIbMEYqetrZH8/H9PXcaVsCET4gOcEuhnow=; b=VW1ZhS9pd6vrttBclIFfth3C29SCtT72UeocdqHU/c+fyNV0g3WpdBpD WhqXKv1oc7sv6yb0/JECd3K6lS4AyuPRkcInUtjD3UGNVv90Q3DgyQAU8 dTxu/PHfFet2ZG3IDxGBmZuPvVOWfdWCZPhn5ejvackQ2UdFpQrE3FMR9 BpcLUJSlAKFJDpO9UnBTGHW4x3w/HYDrfY9PM6J257rGa3GQfyEow3nQs jXevuAPmi1r+as+ANUqpVHpoGjtI1brGPTWBh5E4EkHKQ4OHfj6b0fL0W ur2kB2n562wOpO9kHf24SyMZAOnmNkA49FADJhm4rra+NyWVmsTRZMoby A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527705" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527705" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235146" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235146" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:35 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Martyna Szapar-Mudlaw Subject: [PATCH v2 11/20] net/ice/base: add support for VLAN TPID filters Date: Thu, 18 May 2023 15:16:29 +0000 Message-Id: <20230518151638.1207021-12-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable support for adding TC rules that filter on the VLAN tag type in switchdev mode. Signed-off-by: Martyna Szapar-Mudlaw Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_protocol_type.h | 6 ++- drivers/net/ice/base/ice_switch.c | 59 ++++++++++++++++++++++-- drivers/net/ice/base/ice_switch.h | 1 + drivers/net/ice/base/ice_vlan_mode.c | 1 - 4 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 8c57cd2081..05a89050fe 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -219,7 +219,7 @@ enum ice_prot_id { */ #define ICE_UDP_OF_HW 52 /* UDP Tunnels */ #define ICE_GRE_OF_HW 64 /* NVGRE */ -#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */ +#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel and VLAN type */ #define ICE_MDID_SIZE 2 #define ICE_TUN_FLAG_MDID 20 @@ -229,6 +229,10 @@ enum ice_prot_id { #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 +#define ICE_VLAN_FLAG_MDID 20 +#define ICE_VLAN_FLAG_MDID_OFF (ICE_MDID_SIZE * ICE_VLAN_FLAG_MDID) +#define ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK 0xD000 + #define ICE_PROTOCOL_MAX_ENTRIES 16 /* Mapping of software defined protocol ID to hardware defined protocol ID */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index c5951b5d40..c86d68d543 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7805,10 +7805,11 @@ ice_tun_type_match_word(struct ice_adv_rule_info *rinfo, u16 *off, u16 *mask) * ice_add_special_words - Add words that are not protocols, such as metadata * @rinfo: other information regarding the rule e.g. priority and action info * @lkup_exts: lookup word structure + * @dvm_ena: is double VLAN mode enabled */ static enum ice_status ice_add_special_words(struct ice_adv_rule_info *rinfo, - struct ice_prot_lkup_ext *lkup_exts) + struct ice_prot_lkup_ext *lkup_exts, bool dvm_ena) { u16 mask; u16 off; @@ -7829,6 +7830,19 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, } } + if (rinfo->vlan_type != 0 && dvm_ena) { + if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) { + u8 word = lkup_exts->n_val_words++; + + lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW; + lkup_exts->fv_words[word].off = ICE_VLAN_FLAG_MDID_OFF; + lkup_exts->field_mask[word] = + ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK; + } else { + return ICE_ERR_MAX_LIMIT; + } + } + return ICE_SUCCESS; } @@ -8155,7 +8169,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Create any special protocol/offset pairs, such as looking at tunnel * bits by extracting metadata */ - status = ice_add_special_words(rinfo, lkup_exts); + status = ice_add_special_words(rinfo, lkup_exts, ice_is_dvm_ena(hw)); if (status) goto err_free_lkup_exts; @@ -8995,6 +9009,36 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type, return ICE_ERR_CFG; } +/** + * ice_fill_adv_packet_vlan - fill dummy packet with VLAN tag type + * @vlan_type: VLAN tag type + * @pkt: dummy packet to fill in + * @offsets: offset info for the dummy packet + */ +static enum ice_status +ice_fill_adv_packet_vlan(u16 vlan_type, u8 *pkt, + const struct ice_dummy_pkt_offsets *offsets) +{ + u16 i; + + /* Find VLAN header and insert VLAN TPID */ + for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) { + if (offsets[i].type == ICE_VLAN_OFOS || + offsets[i].type == ICE_VLAN_EX) { + struct ice_vlan_hdr *hdr; + u16 offset; + + offset = offsets[i].offset; + hdr = (struct ice_vlan_hdr *)&pkt[offset]; + hdr->type = CPU_TO_BE16(vlan_type); + + return ICE_SUCCESS; + } + } + + return ICE_ERR_CFG; +} + /** * ice_find_adv_rule_entry - Search a rule entry * @hw: pointer to the hardware structure @@ -9030,6 +9074,7 @@ ice_find_adv_rule_entry(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } if (rinfo->sw_act.flag == list_itr->rule_info.sw_act.flag && rinfo->tun_type == list_itr->rule_info.tun_type && + rinfo->vlan_type == list_itr->rule_info.vlan_type && lkups_matched) return list_itr; } @@ -9481,6 +9526,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_ice_add_adv_rule; } + if (rinfo->vlan_type != 0 && ice_is_dvm_ena(hw)) { + status = ice_fill_adv_packet_vlan(rinfo->vlan_type, + s_rule->pdata.lkup_tx_rx.hdr, + pkt_offsets); + if (status) + goto err_ice_add_adv_rule; + } + rx_tx = s_rule; if (rinfo->sw_act.fltr_act == ICE_SET_MARK) { lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(nb_lg_acts_mark); @@ -9686,7 +9739,7 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Create any special protocol/offset pairs, such as looking at tunnel * bits by extracting metadata */ - status = ice_add_special_words(rinfo, &lkup_exts); + status = ice_add_special_words(rinfo, &lkup_exts, ice_is_dvm_ena(hw)); if (status) return status; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 7421e02466..7a6944893d 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -314,6 +314,7 @@ struct ice_adv_rule_info { u8 add_dir_lkup; u16 fltr_rule_id; u16 lg_id; + u16 vlan_type; struct ice_adv_rule_flags_info flags_info; }; diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 7ee00df124..33759e4b8a 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -201,7 +201,6 @@ static bool ice_is_dvm_supported(struct ice_hw *hw) #define ICE_SW_LKUP_VLAN_PKT_FLAGS_LKUP_IDX 2 #define ICE_SW_LKUP_PROMISC_VLAN_LOC_LKUP_IDX 2 #define ICE_PKT_FLAGS_0_TO_15_FV_IDX 1 -#define ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK 0xD000 static struct ice_update_recipe_lkup_idx_params ice_dvm_dflt_recipes[] = { { /* Update recipe ICE_SW_LKUP_VLAN to filter based on the From patchwork Thu May 18 15:16:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127006 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03F4B42AF1; Thu, 18 May 2023 17:35:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2914F42D81; Thu, 18 May 2023 17:34:40 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E53BD42D17 for ; Thu, 18 May 2023 17:34:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424079; x=1715960079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=elweG41cSNwvTrz7x1Itx6y+sd0tWhuXoFR1AlAHZnc=; b=EFZpmcOLDlPqelOFUH6wMR17hoX3nJGJmwkyn1EMIFBMH0TVPersiyKc mg3KhijS8Fw1Fun4AmT/myaZBPqC5L1MQYIXgsyGmDTjE0Or08cUBvWz5 6vbmwgejIkTVAan+jxe2Y60bK8eu8jW7z/y4LRTMBO1SKGWh9HvZ7jIZU ptVpmyhYv7yPbfPLF924Qs/ZrLWL2F7vs2obiuWKAPWgSozWC56W8jURH OzAdVrmashJVKNac6b1PNwtu5f8Q1/IQ9O0LsHC/u2FNr71bE/4t4fU2+ LzOSJ7A6M1nYAFCoPHIRQ1eZXtim30lZ+GabjbCBytBPbqdSogyH69gAO A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527714" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527714" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235158" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235158" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:37 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Grzegorz Nitka Subject: [PATCH v2 12/20] net/ice/base: add C825-X device ID Date: Thu, 18 May 2023 15:16:30 +0000 Message-Id: <20230518151638.1207021-13-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add the device ID for the Intel(R) Ethernet Connection C825-X. Signed-off-by: Grzegorz Nitka Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 6 +++--- drivers/net/ice/base/ice_devids.h | 7 ++----- drivers/net/ice/base/ice_type.h | 1 + drivers/net/ice/ice_ethdev.c | 4 ++-- 4 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index bcfd8e458d..a958ecef83 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -171,9 +171,9 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E825C_BACKPLANE: case ICE_DEV_ID_E825C_QSFP: case ICE_DEV_ID_E825C_SFP: - case ICE_DEV_ID_E825C_1GBE: - case ICE_DEV_ID_E825X: - hw->mac_type = ICE_MAC_GENERIC; + case ICE_DEV_ID_C825X: + case ICE_DEV_ID_E825C_SGMII: + hw->mac_type = ICE_MAC_GENERIC_3K_E825; break; default: hw->mac_type = ICE_MAC_UNKNOWN; diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 83af3c3b05..19478d2db1 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -73,9 +73,6 @@ /* Intel(R) Ethernet Connection E825-C for SFP */ #define ICE_DEV_ID_E825C_SFP 0x579E /* Intel(R) Ethernet Connection E825-C 1GbE */ -#define ICE_DEV_ID_E825C_1GBE 0x579F -/* Intel(R) Ethernet Connection E825-X */ -#define ICE_DEV_ID_E825X 0x0DCD - - +#define ICE_DEV_ID_E825C_SGMII 0x579F +#define ICE_DEV_ID_C825X 0x0DCD #endif /* _ICE_DEVIDS_H_ */ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index c653c1de3e..d13105070b 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -206,6 +206,7 @@ enum ice_mac_type { ICE_MAC_E810, ICE_MAC_GENERIC, ICE_MAC_GENERIC_3K, + ICE_MAC_GENERIC_3K_E825, }; /* Media Types */ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9a88cf9796..a696e70d91 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -196,8 +196,8 @@ static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SFP) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_1GBE) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825X) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C825X) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SGMII ) }, { .vendor_id = 0, /* sentinel */ }, }; From patchwork Thu May 18 15:16:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127007 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60B8D42AF1; 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a="341527728" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527728" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235163" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235163" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:38 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Yahui Cao Subject: [PATCH v2 13/20] net/ice/base: add function to get rxq context Date: Thu, 18 May 2023 15:16:31 +0000 Message-Id: <20230518151638.1207021-14-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch exports rxq context which is consumed by linux live migration driver to save device state. Signed-off-by: Yahui Cao Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 67 ++++++++++++++++++++++++++++--- drivers/net/ice/base/ice_common.h | 7 +++- 2 files changed, 67 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a958ecef83..9992d0ad4d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1381,6 +1381,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) return ICE_SUCCESS; } +/** + * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW + * @hw: pointer to the hardware structure + * @ice_rxq_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Copies rxq context from HW register space to dense structure + */ +static enum ice_status +ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) +{ + u8 i; + + if (!ice_rxq_ctx) + return ICE_ERR_BAD_PTR; + + if (rxq_index > QRX_CTRL_MAX_INDEX) + return ICE_ERR_PARAM; + + /* Copy each dword separately from HW */ + for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { + u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32))); + + *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); + + ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); + } + + return ICE_SUCCESS; +} + /* LAN Rx Queue Context */ static const struct ice_ctx_ele ice_rlan_ctx_info[] = { /* Field Width LSB */ @@ -1432,6 +1463,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } +/** + * ice_read_rxq_ctx - Read rxq context from HW + * @hw: pointer to the hardware structure + * @rlan_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Read rxq context from HW register space and then converts it from dense + * structure to sparse + */ +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index) +{ + u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; + enum ice_status status; + + if (!rlan_ctx) + return ICE_ERR_BAD_PTR; + + status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index); + if (status) + return status; + + return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info); +} + /** * ice_clear_rxq_ctx * @hw: pointer to the hardware structure @@ -4824,7 +4881,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, * @ce_info: a description of the struct to be filled */ static void -ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u8 dest_byte, mask; u8 *src, *target; @@ -4860,7 +4917,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u16 dest_word, mask; u8 *src, *target; @@ -4903,7 +4960,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u32 dest_dword, mask; __le32 src_dword; @@ -4954,7 +5011,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u64 dest_qword, mask; __le64 src_qword; @@ -5005,7 +5062,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the structure to be read from */ enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { int f; diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index e1febfb0c4..aff361e5aa 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -86,6 +86,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index); enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); enum ice_status ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); @@ -128,6 +131,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[]; enum ice_status ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); +enum ice_status +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); enum ice_status ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, @@ -221,8 +226,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, u32 start_address, u8 *buf, u8 buf_size, struct ice_sq_cd *cd); -enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); enum ice_status ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, u16 *q_handle, u16 *q_ids, u32 *q_teids, From patchwork Thu May 18 15:16:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127008 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5EF5642AF1; Thu, 18 May 2023 17:36:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9DAD542D9C; Thu, 18 May 2023 17:34:44 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id B62F042D46 for ; Thu, 18 May 2023 17:34:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424081; x=1715960081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mzQOERMGypxJoQsco10SV5AiB+4C53hjbLbQKM9A/Kc=; b=KjxP9sNxuLyf1ZtP3fOZGUUmJRdx9ZSiP8LPDitSPEU+KOhTLbKTM/72 avTNLUbepUayT1cAd0wz1v2A3vpIq/R3ns3/k7KcHJUHLNQToBbCazRlB qnmMroS8by/JeQlabmlyOGDX2LlDuL54Y0BVZbAZv/fPrnrIeIwoW/EEC 5RnOug/y2S6aod5FL+FdrSjENUmlyvO9hZhSaADPy5QcVYAsUZUJTJwS9 wbD7Cbfc6OVtWGMP5Qpy5eIPUOIQHhS0vJA8H1QRQCE4JILOhF1ZYAByW itqt7QCkB2qlBJb3UHs2BgeCWxglJT/gljN8KjGtSqZBnFahCLppsmA/O Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527743" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527743" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235178" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235178" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:40 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Domagala Subject: [PATCH v2 14/20] net/ice/base: modify tunnel match mask Date: Thu, 18 May 2023 15:16:32 +0000 Message-Id: <20230518151638.1207021-15-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Tunneled packets with VLAN inside were not detected by filter. This patch fix it by modifying tunnel flag match mask. As a result both type of packets (tunneled VLAN, tunneled non-VLAN) will be detected by filter. Signed-off-by: Marcin Domagala Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 4 +++- drivers/net/ice/base/ice_protocol_type.h | 1 + drivers/net/ice/base/ice_switch.c | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 9992d0ad4d..67203cb932 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1510,7 +1510,9 @@ enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) return ICE_SUCCESS; } -/* LAN Tx Queue Context */ +/* LAN Tx Queue Context used for set Tx config by ice_aqc_opc_add_txqs, + * Bit[0-175] is valid + */ const struct ice_ctx_ele ice_tlan_ctx_info[] = { /* Field Width LSB */ ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 05a89050fe..d2d3f75fc2 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -226,6 +226,7 @@ enum ice_prot_id { #define ICE_TUN_FLAG_MDID_OFF(word) (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) #define ICE_TUN_FLAG_MASK 0xFF #define ICE_DIR_FLAG_MASK 0x10 +#define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */ #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index c86d68d543..06665a29db 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7790,7 +7790,8 @@ ice_tun_type_match_word(struct ice_adv_rule_info *rinfo, u16 *off, u16 *mask) case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: - *mask = ICE_TUN_FLAG_MASK & ~ICE_TUN_FLAG_VLAN_MASK; + *mask = ICE_TUN_FLAG_MASK & ~(ICE_TUN_FLAG_VLAN_MASK | + ICE_TUN_FLAG_IN_VLAN_MASK); *off = ICE_TUN_FLAG_MDID_OFF(1); return true; From patchwork Thu May 18 15:16:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127009 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0304142AF1; Thu, 18 May 2023 17:36:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9C76E42DA4; Thu, 18 May 2023 17:34:45 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 10A0842D9B for ; Thu, 18 May 2023 17:34:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424083; x=1715960083; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qOrryRfocNYxpzvtwNi4mSEKYKrSIK1AOwHqzWP/Kok=; b=BoEwXhlFUWetonzSEMJZ5yupIv6XHcU1EOmzpeawuLFqwDNBirrsi5uc pb8NnqXrDnYMNVxkWkvAuU8tuLCkKsS3JyStSzdOrPXCSltCqj/E4tnv6 beq07e3pqPxGbUkmjuGJkjLpD5/kkc8Ced/88fPi4JETUi4OnFh+0sPiy rNgZnt8S8API7yR/EA4vLZ2JSVG/VvjjUv0p4WDohnp467uIfy7/jnmHp gf7qWu1fQLU7MZalbghZDSYhCJoXzB5OlHfQICiUrPmEfqDcl22JRWTSf EkUYKth0kTKj9bejiidpXCUR4af7LuzOIW5S2/OgegccvPBWsq3djni50 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527753" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527753" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235206" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235206" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:41 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Benjamin Mikailenko Subject: [PATCH v2 15/20] net/ice/base: check VSIG before disassociating VSI Date: Thu, 18 May 2023 15:16:33 +0000 Message-Id: <20230518151638.1207021-16-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add checking if the VSIG group exists when iterating through all flow profiles and disassociating them from the VSI. Signed-off-by: Benjamin Mikailenko Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_flow.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 5254ee27ed..7f1490de50 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -3856,6 +3856,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) const enum ice_block blk = ICE_BLK_RSS; struct ice_flow_prof *p, *t; enum ice_status status = ICE_SUCCESS; + u16 vsig; if (!ice_is_vsi_valid(hw, vsi_handle)) return ICE_ERR_PARAM; @@ -3865,7 +3866,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) ice_acquire_lock(&hw->rss_locks); LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof, - l_entry) + l_entry) { + int ret; + + /* check if vsig is already removed */ + ret = ice_vsig_find_vsi(hw, blk, + ice_get_hw_vsi_num(hw, vsi_handle), + &vsig); + if (!ret && !vsig) + break; + if (ice_is_bit_set(p->vsis, vsi_handle)) { status = ice_flow_disassoc_prof(hw, blk, p, vsi_handle); if (status) @@ -3877,6 +3887,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) break; } } + } ice_release_lock(&hw->rss_locks); return status; From patchwork Thu May 18 15:16:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127010 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 415D242AF1; Thu, 18 May 2023 17:36:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 99D1F42DA9; Thu, 18 May 2023 17:34:46 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 5DD9242D88 for ; Thu, 18 May 2023 17:34:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424084; x=1715960084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jFULjqhPqwdGRx+31NdQzWwIG9/wnMemQCl30O4O0MI=; b=djpUlar2Gzhmz7pJbiPFO0CsYULaJ7+5Cip3m1GVXSMG4M26O5pmR14n sIJSk1fTymgegxeXm/hPB+blRLvXXg7lMfpw3sjFxFKtCkny5aBkxTE7I kLF50CiCUymnDHUVvmo67NCk1BkkxA/tuT377FiCBUHgr4E6sBVm5vUoL PIMB19WaYuUpAiPMGLcJ3HsbO0gw8d9H8Z7j1lb+7gIZEoY5cSQEC5MG3 PXnw5I8ajTIFGFhOxnjEv3fQI9PS2gDgVGWodDlSNQTFzYgybuRmBx2I6 ZEWv0nJ59ALY7+nZAMpqlQdLlGirNcGi09hYCNKoZdSYu4qL6muKOuqr3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527769" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527769" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235214" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235214" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:42 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Szycik Subject: [PATCH v2 16/20] net/ice/base: delete get field vector function Date: Thu, 18 May 2023 15:16:34 +0000 Message-Id: <20230518151638.1207021-17-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently ice_get_fv() is only used inside ice_get_sw_fv_list(). Remove ice_get_fv() and call ice_get_sw_fv_list() directly. Signed-off-by: Marcin Szycik Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ddp.c | 3 +++ drivers/net/ice/base/ice_switch.c | 23 ++--------------------- 2 files changed, 5 insertions(+), 21 deletions(-) diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 3e18f2bc70..d88c417faf 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -1579,6 +1579,9 @@ ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, struct ice_fv *fv; u32 offset; + if (!lkups->n_val_words) + return ICE_SUCCESS; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); if (!lkups->n_val_words || !hw->seg) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 06665a29db..1f391002b8 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7733,25 +7733,6 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm, return status; } -/** - * ice_get_fv - get field vectors/extraction sequences for spec. lookup types - * @hw: pointer to hardware structure - * @lkups: lookup elements or match criteria for the advanced recipe, one - * structure per protocol header - * @bm: bitmap of field vectors to consider - * @fv_list: pointer to a list that holds the returned field vectors - */ -static enum ice_status -ice_get_fv(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, - ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list) -{ - if (!lkups->n_val_words) - return ICE_SUCCESS; - - /* Find field vectors that include all specified protocol types */ - return ice_get_sw_fv_list(hw, lkups, bm, fv_list); -} - /** * ice_tun_type_match_word - determine if tun type needs a match mask * @rinfo: other information regarding the rule e.g. priority and action info @@ -8159,11 +8140,11 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Get bitmap of field vectors (profiles) that are compatible with the * rule request; only these will be searched in the subsequent call to - * ice_get_fv. + * ice_get_sw_fv_list. */ ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap); - status = ice_get_fv(hw, lkup_exts, fv_bitmap, &rm->fv_list); + status = ice_get_sw_fv_list(hw, lkup_exts, fv_bitmap, &rm->fv_list); if (status) goto err_unroll; From patchwork Thu May 18 15:16:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127011 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8F3042AF1; Thu, 18 May 2023 17:36:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A78EC42D62; Thu, 18 May 2023 17:34:47 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id D092E42D86 for ; Thu, 18 May 2023 17:34:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424086; x=1715960086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x5+kojpkXSbWYl0/P+RkNRMOnI6adVMLI5vCZ/0aMYc=; b=nYoZarsxGG6YIfpjHFFYdOW/Q+C5dPgSEMbtpuNba0ida4a8WuOXbdlr XCRpYcebVhTRt6eMPNi8nNNnyuTuV+XCm2QKywynEbG70mx5AmxeeCjK1 tyqSKIQ7baGhVjZoYMK8jS5cjlZvp+c0wONUwDO8bkefgm+KdKDdtIn+o 5J/vZ3rtlzDB714aqpyhG2Y3IJqZNtzjzTMOFSBgZ4EipdEVuMJjXy+cE BEYYmnRxzyiqEPZpd7Q8yN342Yb+DEDHZJ/hWZjJ874aB0FkrP06thi+T /1mOlPQ1D63fnAK+uvYUImHEyZoGqAXhtYcrrVIiU80F22aC+Vt5W4tI0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527783" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527783" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235236" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235236" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:44 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Grzegorz Nitka Subject: [PATCH v2 17/20] net/ice/base: update 3k-sign DDP support for E825C Date: Thu, 18 May 2023 15:16:35 +0000 Message-Id: <20230518151638.1207021-18-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The original DDP specification has been changed in terms of Signature Type ID definition for E825-C. Signed-off-by: Grzegorz Nitka Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 3 ++- drivers/net/ice/base/ice_ddp.c | 4 ++++ drivers/net/ice/base/ice_ddp.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 67203cb932..f253e2f213 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -193,7 +193,8 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) bool ice_is_generic_mac(struct ice_hw *hw) { return (hw->mac_type == ICE_MAC_GENERIC || - hw->mac_type == ICE_MAC_GENERIC_3K); + hw->mac_type == ICE_MAC_GENERIC_3K || + hw->mac_type == ICE_MAC_GENERIC_3K_E825); } /** diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index d88c417faf..ffcd5a9394 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -441,6 +441,7 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type) switch (mac_type) { case ICE_MAC_GENERIC: case ICE_MAC_GENERIC_3K: + case ICE_MAC_GENERIC_3K_E825: default: seg_id = SEGMENT_TYPE_ICE_E810; break; @@ -461,6 +462,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type) case ICE_MAC_GENERIC_3K: sign_type = SEGMENT_SIGN_TYPE_RSA3K; break; + case ICE_MAC_GENERIC_3K_E825: + sign_type = SEGMENT_SIGN_TYPE_RSA3K_E825; + break; case ICE_MAC_GENERIC: default: sign_type = SEGMENT_SIGN_TYPE_RSA2K; diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 4896e85b91..1e02adf0db 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -99,6 +99,7 @@ struct ice_pkg_hdr { #define SEGMENT_SIGN_TYPE_RSA2K 0x00000001 #define SEGMENT_SIGN_TYPE_RSA3K 0x00000002 #define SEGMENT_SIGN_TYPE_RSA3K_SBB 0x00000003 /* Secure Boot Block */ +#define SEGMENT_SIGN_TYPE_RSA3K_E825 0x00000005 /* generic segment */ struct ice_generic_seg_hdr { From patchwork Thu May 18 15:16:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127012 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7765342AF1; Thu, 18 May 2023 17:36:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A280342DB9; Thu, 18 May 2023 17:34:49 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 4DE5D42DAD for ; Thu, 18 May 2023 17:34:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424088; x=1715960088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HghU0ET1o7wgN6VtGDNkwkZAz19S08X2oOFz4NSDY5w=; b=Ndqz5ef3ip5VABfUmoCTjQKuAOGSwSg72RsOPdx2yze+mEnJH+n+BH1/ CgxUaPck/z4Il2ahBU5PGPsu7mADNVFZjOSzQ60cuOVTbhY2FNIMtAXii NTFghqMNH9d2zuLEr+3coZsZFWrkNdwf6B5IoC/E2Ko/VzFUR0EACt9Za 2KrTzw3OusKJ5NhCEcbbtGseXNWML/iCPnHZML2YEs2tHiOoOMI5DTBGs H5DtgoCwuyUqx5/2b+SMXN/SlTGKkxkz0+4IODIbHRoYjZ/Hlncgxuhlv 0m6FSLiMbzrmDcYzCcL6Txm7JGRUOJBsjTRPvyif+fYjRia3ke3R/4qSu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527799" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527799" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235257" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235257" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:45 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Vignesh Sridhar Subject: [PATCH v2 18/20] net/ice/base: fix static analyzer bug Date: Thu, 18 May 2023 15:16:36 +0000 Message-Id: <20230518151638.1207021-19-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The default condition in the switch statement in ice_sched_get_psm_clk_freq() is an unreachable code. The variable clk_src is restricted to values 0 to 3 with the bit mask and shift values set. Fixes: 76ac9d771c97 ("net/ice/base: read PSM clock frequency from register") Signed-off-by: Vignesh Sridhar Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_sched.c | 16 ++++++---------- drivers/net/ice/base/ice_sched.h | 5 +++++ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 83cd152388..f558eccb93 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1417,11 +1417,6 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; -#define PSM_CLK_SRC_367_MHZ 0x0 -#define PSM_CLK_SRC_416_MHZ 0x1 -#define PSM_CLK_SRC_446_MHZ 0x2 -#define PSM_CLK_SRC_390_MHZ 0x3 - switch (clk_src) { case PSM_CLK_SRC_367_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; @@ -1435,11 +1430,12 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) case PSM_CLK_SRC_390_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; break; - default: - ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", - clk_src); - /* fall back to a safe default */ - hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; + + /* default condition is not required as clk_src is restricted + * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask. + * The above switch statements cover the possible values of + * this variable. + */ } } diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index a71619ebf0..c54f5ca9a0 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -38,6 +38,11 @@ #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 +#define PSM_CLK_SRC_367_MHZ 0x0 +#define PSM_CLK_SRC_416_MHZ 0x1 +#define PSM_CLK_SRC_446_MHZ 0x2 +#define PSM_CLK_SRC_390_MHZ 0x3 + struct rl_profile_params { u32 bw; /* in Kbps */ u16 rl_multiplier; From patchwork Thu May 18 15:16:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127013 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE33E42AF1; Thu, 18 May 2023 17:36:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E839A42F8A; Thu, 18 May 2023 17:34:50 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id E650142DB7 for ; Thu, 18 May 2023 17:34:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424089; x=1715960089; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sKgGRNyDtUYH8/088YHo8s2gI8KM/3VbHCXWntBZc/w=; b=YVHMhTSoPOEpoBOlyQ2jH+gtUU7Q7kb7t39JNydF76aKodzI5UvKNsYu xQ8duUCXsQi4bEMmskIP2NOKog3Aqf4R0iq/0CnQVwKAHn5YhXUUB6Kd/ lHiuiCDFZ8Cesj+j0vHRmLExgs/DyjD5NezWEacwgTrUmiXJpF6QMtjp1 7PLl3UxvvuV81s4NT0O/ZoQzbl3AVXMGHHSGvxvJE4ZpmIMaNs537cs9p cfffC0F+KESprI05ozXcQCTcDF2Zjm4vMXF9+RWVWW9vxDs5582oCQXl+ qNUPS/Eg+6jhxbyqCfbLOKkIWIvGpXOZ6Hy3HkvXjixR5BR/PUSGxkmy/ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527814" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527814" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235272" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235272" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:47 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Michal Wilczynski Subject: [PATCH v2 19/20] net/ice/base: offer memory config for schedual node Date: Thu, 18 May 2023 15:16:37 +0000 Message-Id: <20230518151638.1207021-20-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add an option to pre-allocate memory for ice_sched_node struct. Add new arguments to ice_sched_add() and ice_sched_add_elems() that allow for pre-allocation of memory for ice_sched_node struct. Signed-off-by: Michal Wilczynski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_dcb.c | 2 +- drivers/net/ice/base/ice_sched.c | 24 ++++++++++++++++++------ drivers/net/ice/base/ice_sched.h | 3 ++- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index f253e2f213..f7f43cd7e0 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -5210,7 +5210,7 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, q_ctx->q_teid = LE32_TO_CPU(node.node_teid); /* add a leaf node into scheduler tree queue layer */ - status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); + status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); if (!status) status = ice_sched_replay_q_bw(pi, q_ctx); diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index 2a308b02bf..cc4e28a702 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1624,7 +1624,7 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi, /* new TC */ status = ice_sched_query_elem(pi->hw, teid2, &elem); if (!status) - status = ice_sched_add_node(pi, 1, &elem); + status = ice_sched_add_node(pi, 1, &elem, NULL); if (status) break; /* update the TC number */ diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index f558eccb93..a4d31647fe 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -143,12 +143,14 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, * @pi: port information structure * @layer: Scheduler layer of the node * @info: Scheduler element information from firmware + * @prealloc_node: preallocated ice_sched_node struct for SW DB * * This function inserts a scheduler node to the SW DB. */ enum ice_status ice_sched_add_node(struct ice_port_info *pi, u8 layer, - struct ice_aqc_txsched_elem_data *info) + struct ice_aqc_txsched_elem_data *info, + struct ice_sched_node *prealloc_node) { struct ice_aqc_txsched_elem_data elem; struct ice_sched_node *parent; @@ -176,7 +178,11 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer, status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem); if (status) return status; - node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); + + if (prealloc_node) + node = prealloc_node; + else + node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); if (!node) return ICE_ERR_NO_MEMORY; if (hw->max_children[layer]) { @@ -901,13 +907,15 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, * @num_nodes: number of nodes * @num_nodes_added: pointer to num nodes added * @first_node_teid: if new nodes are added then return the TEID of first node + * @prealloc_nodes: preallocated nodes struct for software DB * * This function add nodes to HW as well as to SW DB for a given layer */ static enum ice_status ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, struct ice_sched_node *parent, u8 layer, u16 num_nodes, - u16 *num_nodes_added, u32 *first_node_teid) + u16 *num_nodes_added, u32 *first_node_teid, + struct ice_sched_node **prealloc_nodes) { struct ice_sched_node *prev, *new_node; struct ice_aqc_add_elem *buf; @@ -953,7 +961,11 @@ ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, *num_nodes_added = num_nodes; /* add nodes to the SW DB */ for (i = 0; i < num_nodes; i++) { - status = ice_sched_add_node(pi, layer, &buf->generic[i]); + if (prealloc_nodes) + status = ice_sched_add_node(pi, layer, &buf->generic[i], prealloc_nodes[i]); + else + status = ice_sched_add_node(pi, layer, &buf->generic[i], NULL); + if (status != ICE_SUCCESS) { ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", status); @@ -1032,7 +1044,7 @@ ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, } return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, - num_nodes_added, first_node_teid); + num_nodes_added, first_node_teid, NULL); } /** @@ -1292,7 +1304,7 @@ enum ice_status ice_sched_init_port(struct ice_port_info *pi) ICE_AQC_ELEM_TYPE_ENTRY_POINT) hw->sw_entry_point_layer = j; - status = ice_sched_add_node(pi, j, &buf[i].generic[j]); + status = ice_sched_add_node(pi, j, &buf[i].generic[j], NULL); if (status) goto err_init_port; } diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index c54f5ca9a0..4b68f3f535 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -117,7 +117,8 @@ ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); /* Add a scheduling node into SW DB for given info */ enum ice_status ice_sched_add_node(struct ice_port_info *pi, u8 layer, - struct ice_aqc_txsched_elem_data *info); + struct ice_aqc_txsched_elem_data *info, + struct ice_sched_node *prealloc_node); void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); struct ice_sched_node * From patchwork Thu May 18 15:16:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 127014 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 338E642AF1; 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a="341527827" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527827" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235281" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235281" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:48 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Domagala , Eric Joyner Subject: [PATCH v2 20/20] net/ice/base: add new AQ ro read HW sensors Date: Thu, 18 May 2023 15:16:38 +0000 Message-Id: <20230518151638.1207021-21-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds new helper function to read from HW sensors via a new AQ command "Get Sensor Reading (0x0632)". Currently, this AQ command only supports reading the temperature from E810 devices with a supported firmware, but in the future it could be extended to read other sensors. Signed-off-by: Marcin Domagala Signed-off-by: Eric Joyner Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 29 +++++++++++++++++++++ drivers/net/ice/base/ice_common.c | 36 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 4 +++ 3 files changed, 69 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 8df6ca41e9..844e90bbce 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1666,6 +1666,32 @@ struct ice_aqc_set_mac_lb { u8 reserved[15]; }; +/* Get sensor reading (direct 0x0632) */ +struct ice_aqc_get_sensor_reading { + u8 sensor; +#define ICE_AQC_INT_TEMP_SENSOR 0x0 + u8 format; +#define ICE_AQC_INT_TEMP_FORMAT 0x0 + u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +}; + +/* Get sensor reading response (direct 0x0632) */ +struct ice_aqc_get_sensor_reading_resp { + union { + u8 raw[8]; + /* Output data for sensor 0x00, format 0x00 */ + struct { + s8 temp; + u8 temp_warning_threshold; + u8 temp_critical_threshold; + u8 temp_fatal_threshold; + u8 reserved[4]; + } s0f0; + } data; +}; + struct ice_aqc_link_topo_params { u8 lport_num; u8 lport_num_valid; @@ -3004,6 +3030,8 @@ struct ice_aq_desc { struct ice_aqc_get_phy_caps get_phy; struct ice_aqc_set_phy_cfg set_phy; struct ice_aqc_restart_an restart_an; + struct ice_aqc_get_sensor_reading get_sensor_reading; + struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; struct ice_aqc_i2c read_write_i2c; struct ice_aqc_read_i2c_resp read_i2c_resp; struct ice_aqc_gpio read_write_gpio; @@ -3253,6 +3281,7 @@ enum ice_adminq_opc { ice_aqc_opc_get_link_status = 0x0607, ice_aqc_opc_set_event_mask = 0x0613, ice_aqc_opc_set_mac_lb = 0x0620, + ice_aqc_opc_get_sensor_reading = 0x0632, ice_aqc_opc_get_link_topo = 0x06E0, ice_aqc_opc_get_link_topo_pin = 0x06E1, ice_aqc_opc_read_i2c = 0x06E2, diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index f7f43cd7e0..0f26f1d854 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -5359,6 +5359,42 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, ICE_SCHED_NODE_OWNER_LAN); } +/** + * ice_aq_get_sensor_reading + * @hw: pointer to the HW struct + * @sensor: sensor type + * @format: requested response format + * @data: pointer to data to be read from the sensor + * @cd: pointer to command details structure or NULL + * + * Get sensor reading (0x0632) + */ +enum ice_status +ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, + struct ice_aqc_get_sensor_reading_resp *data, + struct ice_sq_cd *cd) +{ + struct ice_aqc_get_sensor_reading *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + if (!data) + return ICE_ERR_PARAM; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); + cmd = &desc.params.get_sensor_reading; + cmd->sensor = sensor; + cmd->format = format; + + status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); + + if (!status) + ice_memcpy(data, &desc.params.get_sensor_reading_resp, + sizeof(*data), ICE_NONDMA_TO_NONDMA); + + return status; +} + /** * ice_is_main_vsi - checks whether the VSI is main VSI * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index aff361e5aa..0f1be917db 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -249,6 +249,10 @@ enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw, void ice_sbq_lock(struct ice_hw *hw); void ice_sbq_unlock(struct ice_hw *hw); enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in); +enum ice_status +ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, + struct ice_aqc_get_sensor_reading_resp *data, + struct ice_sq_cd *cd); void ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat);