From patchwork Thu May 18 11:29:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 126984 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0BF6042B3A; Thu, 18 May 2023 13:32:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A39242D17; Thu, 18 May 2023 13:32:02 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 9765140E25; Thu, 18 May 2023 13:31:59 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4QMSSN6C4fzsSTt; Thu, 18 May 2023 19:29:56 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 19:31:57 +0800 From: Dongdong Liu To: , , , , CC: , , , Subject: [PATCH 1/5] net/hns3: fix never set MAC flow control Date: Thu, 18 May 2023 19:29:40 +0800 Message-ID: <20230518112944.32276-2-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230518112944.32276-1-liudongdong3@huawei.com> References: <20230518112944.32276-1-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li When some hardware and firmware support speed auto-negotiation but do not support flow control auto-negotiation, driver can never successfully set MAC flow control by flow_ctrl_set() API. So only tell user driver doesn't support flow control autoneg when user enable it. Fixes: 1f411e31a826 ("net/hns3: support flow control autoneg for copper port") Cc: stable@dpdk.org Signed-off-by: Huisong Li Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_ethdev.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index d97280e647..8f819d5f23 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5304,16 +5304,7 @@ hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) if (!pf->support_fc_autoneg) { if (autoneg != 0) { - hns3_err(hw, "unsupported fc auto-negotiation setting."); - return -EOPNOTSUPP; - } - - /* - * Flow control auto-negotiation of the NIC is not supported, - * but other auto-negotiation features may be supported. - */ - if (autoneg != hw->mac.link_autoneg) { - hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); + hns3_err(hw, "unsupported fc auto-negotiation."); return -EOPNOTSUPP; } From patchwork Thu May 18 11:29:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 126987 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83E9342B3A; Thu, 18 May 2023 13:32:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 11DB142D4D; Thu, 18 May 2023 13:32:07 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 4E64E4282D; Thu, 18 May 2023 13:32:01 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.56]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4QMST83prNzLmN9; Thu, 18 May 2023 19:30:36 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 19:31:57 +0800 From: Dongdong Liu To: , , , , CC: , , , Subject: [PATCH 2/5] net/hns3: add flow control autoneg for fiber and backplane port Date: Thu, 18 May 2023 19:29:41 +0800 Message-ID: <20230518112944.32276-3-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230518112944.32276-1-liudongdong3@huawei.com> References: <20230518112944.32276-1-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li This patch support flow control autoneg for fiber and backplane port. And it depends on the capability of firmware. Signed-off-by: Huisong Li Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_cmd.c | 30 +++++++++++++++++- drivers/net/hns3/hns3_cmd.h | 20 +++++++++++- drivers/net/hns3/hns3_dump.c | 1 + drivers/net/hns3/hns3_ethdev.c | 58 ++++++++-------------------------- drivers/net/hns3/hns3_ethdev.h | 1 + 5 files changed, 63 insertions(+), 47 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index d530650452..d0a3853656 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -428,7 +428,8 @@ hns3_get_caps_name(uint32_t caps_id) { HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" }, { HNS3_CAPS_RAS_IMP_B, "ras_imp" }, { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" }, - { HNS3_CAPS_TM_B, "tm_capability" } + { HNS3_CAPS_TM_B, "tm_capability" }, + { HNS3_CAPS_FC_AUTO_B, "fc_autoneg" } }; uint32_t i; @@ -510,6 +511,8 @@ hns3_parse_capability(struct hns3_hw *hw, hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1); if (hns3_get_bit(caps, HNS3_CAPS_TM_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_FC_AUTO_B)) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_FC_AUTO_B, 1); } static uint32_t @@ -613,9 +616,31 @@ hns3_update_dev_lsc_cap(struct hns3_hw *hw, int fw_compact_cmd_result) } } +static void +hns3_set_fc_autoneg_cap(struct hns3_adapter *hns, int fw_compact_cmd_result) +{ + struct hns3_hw *hw = &hns->hw; + struct hns3_mac *mac = &hw->mac; + + if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { + hns->pf.support_fc_autoneg = true; + return; + } + + /* + * Flow control auto-negotiation requires the cooperation of the driver + * and firmware. + */ + hns->pf.support_fc_autoneg = (hns3_dev_get_support(hw, FC_AUTO) && + fw_compact_cmd_result == 0) ? + true : false; +} + static int hns3_apply_fw_compat_cmd_result(struct hns3_hw *hw, int result) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + if (result != 0 && hns3_dev_get_support(hw, COPPER)) { hns3_err(hw, "firmware fails to initialize the PHY, ret = %d.", result); @@ -623,6 +648,7 @@ hns3_apply_fw_compat_cmd_result(struct hns3_hw *hw, int result) } hns3_update_dev_lsc_cap(hw, result); + hns3_set_fc_autoneg_cap(hns, result); return 0; } @@ -642,6 +668,8 @@ hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init) hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0); if (hns3_dev_get_support(hw, COPPER)) hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1); + if (hns3_dev_get_support(hw, FC_AUTO)) + hns3_set_bit(compat, HNS3_MAC_FC_AUTONEG_EN_B, 1); } req->compat = rte_cpu_to_le_32(compat); diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 4abe0f1d13..d78c1b401e 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -323,6 +323,7 @@ enum HNS3_CAPS_BITS { HNS3_CAPS_RAS_IMP_B, HNS3_CAPS_RXD_ADV_LAYOUT_B = 15, HNS3_CAPS_TM_B = 19, + HNS3_CAPS_FC_AUTO_B = 30, }; /* Capabilities of VF dependent on the PF */ @@ -666,6 +667,9 @@ enum hns3_promisc_type { #define HNS3_LINK_EVENT_REPORT_EN_B 0 #define HNS3_NCSI_ERROR_REPORT_EN_B 1 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 + +#define HNS3_MAC_FC_AUTONEG_EN_B 6 + struct hns3_firmware_compat_cmd { uint32_t compat; uint8_t rsv[20]; @@ -680,6 +684,7 @@ struct hns3_firmware_compat_cmd { #define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6) #define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13) #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14) +#define HNS3_PHY_LINK_MODE_PAUSE_S 13 #define HNS3_PHY_PARAM_CFG_BD_NUM 2 struct hns3_phy_params_bd0_cmd { @@ -789,6 +794,17 @@ struct hns3_sfp_type { #define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) #define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) +/* Flags for pause status field */ +#define HNS3_FIBER_LOCAL_PAUSE_BIT BIT(0) +#define HNS3_FIBER_LOCAL_ASYM_PAUSE_BIT BIT(1) +#define HNS3_FIBER_LP_PAUSE_BIT BIT(2) +#define HNS3_FIBER_LP_ASYM_PAUSE_BIT BIT(3) +#define HNS3_FIBER_LOCAL_PAUSE_MASK (HNS3_FIBER_LOCAL_PAUSE_BIT | \ + HNS3_FIBER_LOCAL_ASYM_PAUSE_BIT) +#define HNS3_FIBER_LP_PAUSE_MASK (HNS3_FIBER_LP_PAUSE_BIT | \ + HNS3_FIBER_LP_ASYM_PAUSE_BIT) +#define HNS3_FIBER_LP_PAUSE_S 2 + struct hns3_sfp_info_cmd { uint32_t sfp_speed; uint8_t query_type; /* 0: sfp speed, 1: active */ @@ -798,7 +814,9 @@ struct hns3_sfp_info_cmd { uint8_t autoneg_ability; uint32_t supported_speed; /* speed supported by current media */ uint32_t module_type; - uint8_t rsv1[8]; + uint8_t rsv[2]; + uint8_t pause_status; + uint8_t rsv1[5]; }; #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0 diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c index 0af3c2ce09..c0839380ea 100644 --- a/drivers/net/hns3/hns3_dump.c +++ b/drivers/net/hns3/hns3_dump.c @@ -104,6 +104,7 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw) {HNS3_DEV_SUPPORT_RAS_IMP_B, "RAS IMP"}, {HNS3_DEV_SUPPORT_TM_B, "TM"}, {HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, "VF VLAN FILTER MOD"}, + {HNS3_DEV_SUPPORT_FC_AUTO_B, "FC AUTO"} }; uint32_t i; diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 8f819d5f23..5ef66f96c6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3975,6 +3975,7 @@ static int hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) { struct hns3_sfp_info_cmd *resp; + uint32_t local_pause, lp_pause; struct hns3_cmd_desc desc; int ret; @@ -4011,6 +4012,13 @@ hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) mac_info->support_autoneg = resp->autoneg_ability; mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG; + local_pause = resp->pause_status & HNS3_FIBER_LOCAL_PAUSE_MASK; + lp_pause = (resp->pause_status & HNS3_FIBER_LP_PAUSE_MASK) >> + HNS3_FIBER_LP_PAUSE_S; + mac_info->advertising = + local_pause << HNS3_PHY_LINK_MODE_PAUSE_S; + mac_info->lp_advertising = + lp_pause << HNS3_PHY_LINK_MODE_PAUSE_S; } else { mac_info->query_type = HNS3_DEFAULT_QUERY; } @@ -4093,6 +4101,8 @@ hns3_update_fiber_link_info(struct hns3_hw *hw) mac->supported_speed = mac_info.supported_speed; mac->support_autoneg = mac_info.support_autoneg; mac->link_autoneg = mac_info.link_autoneg; + mac->advertising = mac_info.advertising; + mac->lp_advertising = mac_info.lp_advertising; return 0; } @@ -4495,24 +4505,6 @@ hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) return 0; } -static void -hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) -{ - struct hns3_mac *mac = &hns->hw.mac; - - if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { - hns->pf.support_fc_autoneg = true; - return; - } - - /* - * Flow control auto-negotiation requires the cooperation of the driver - * and firmware. Currently, the optical port does not support flow - * control auto-negotiation. - */ - hns->pf.support_fc_autoneg = false; -} - static int hns3_init_pf(struct rte_eth_dev *eth_dev) { @@ -4615,8 +4607,6 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_supported_speed; } - hns3_get_fc_autoneg_capability(hns); - hns3_tm_conf_init(eth_dev); return 0; @@ -5181,8 +5171,7 @@ hns3_dev_close(struct rte_eth_dev *eth_dev) } static void -hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, - bool *tx_pause) +hns3_get_autoneg_rxtx_pause(struct hns3_hw *hw, bool *rx_pause, bool *tx_pause) { struct hns3_mac *mac = &hw->mac; uint32_t advertising = mac->advertising; @@ -5193,8 +5182,7 @@ hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { *rx_pause = true; *tx_pause = true; - } else if (advertising & lp_advertising & - HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { + } else if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) *rx_pause = true; else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) @@ -5209,26 +5197,7 @@ hns3_get_autoneg_fc_mode(struct hns3_hw *hw) bool rx_pause = false; bool tx_pause = false; - switch (hw->mac.media_type) { - case HNS3_MEDIA_TYPE_COPPER: - hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); - break; - - /* - * Flow control auto-negotiation is not supported for fiber and - * backplane media type. - */ - case HNS3_MEDIA_TYPE_FIBER: - case HNS3_MEDIA_TYPE_BACKPLANE: - hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); - current_mode = hw->requested_fc_mode; - goto out; - default: - hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", - hw->mac.media_type); - current_mode = HNS3_FC_NONE; - goto out; - } + hns3_get_autoneg_rxtx_pause(hw, &rx_pause, &tx_pause); if (rx_pause && tx_pause) current_mode = HNS3_FC_FULL; @@ -5239,7 +5208,6 @@ hns3_get_autoneg_fc_mode(struct hns3_hw *hw) else current_mode = HNS3_FC_NONE; -out: return current_mode; } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 8268dba788..88146f5054 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -892,6 +892,7 @@ enum hns3_dev_cap { HNS3_DEV_SUPPORT_RAS_IMP_B, HNS3_DEV_SUPPORT_TM_B, HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, + HNS3_DEV_SUPPORT_FC_AUTO_B, }; #define hns3_dev_get_support(hw, _name) \ From patchwork Thu May 18 11:29:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 126985 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA2DE42B3A; Thu, 18 May 2023 13:32:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7266642BDA; Thu, 18 May 2023 13:32:04 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 60C6B4014F; Thu, 18 May 2023 13:32:00 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4QMSPh4rqyzqSQL; Thu, 18 May 2023 19:27:36 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 19:31:58 +0800 From: Dongdong Liu To: , , , , CC: , , , Subject: [PATCH 3/5] net/hns3: fix loop code variable type mismatch Date: Thu, 18 May 2023 19:29:42 +0800 Message-ID: <20230518112944.32276-4-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230518112944.32276-1-liudongdong3@huawei.com> References: <20230518112944.32276-1-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang Loop conditions are compared with different variable types, which may cause overflow risks. Signed-off-by: Dengdui Huang Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_regs.c | 3 ++- drivers/net/hns3/hns3_stats.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c index 33392fd1f0..5d6f92e4bb 100644 --- a/drivers/net/hns3/hns3_regs.c +++ b/drivers/net/hns3/hns3_regs.c @@ -294,8 +294,9 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); uint32_t *origin_data_ptr = data; uint32_t reg_offset; - uint16_t i, j; size_t reg_num; + uint16_t j; + size_t i; /* fetching per-PF registers values from PF PCIe register space */ reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index bad65fcbed..c2e692a2c5 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -317,7 +317,7 @@ hns3_update_mac_stats(struct hns3_hw *hw) uint32_t stats_iterms; uint64_t *desc_data; uint32_t desc_num; - uint16_t i; + uint32_t i; int ret; /* The first desc has a 64-bit header, so need to consider it. */ From patchwork Thu May 18 11:29:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 126986 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB50742B3A; Thu, 18 May 2023 13:32:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B384542D44; Thu, 18 May 2023 13:32:05 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 53E0442B71; Thu, 18 May 2023 13:32:01 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.54]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4QMST92mgdzLmNV; Thu, 18 May 2023 19:30:37 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 19:31:58 +0800 From: Dongdong Liu To: , , , , CC: , , , Subject: [PATCH 4/5] net/hns3: fix receive multiple firmware reset interrupts Date: Thu, 18 May 2023 19:29:43 +0800 Message-ID: <20230518112944.32276-5-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230518112944.32276-1-liudongdong3@huawei.com> References: <20230518112944.32276-1-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Chengwen Feng In the firmware (also known as IMP) reset scenario, driver interrupt processing and firmware watchdog initialization are asynchronous. If the driver interrupt processing is faster than firmware watchdog initialization (that is, the driver clears the firmware reset interrupt source before the firmware watchdog is initialized), the driver will receive multiple firmware reset interrupts. In the Kunpeng 920 platform, the above situation does not exist. But it does on the newer platforms. So we add 5ms delay before drivers clears the IMP reset interrupt source. As for the impact of 5ms, the number of PFs managed by a firmware is limited. Therefore, even if a DPDK process takes over all the PFs which managed by the firmware, the delay is controllable. Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_ethdev.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 5ef66f96c6..664226a6ef 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -286,6 +286,19 @@ hns3_handle_mac_tnl(struct hns3_hw *hw) } } +static void +hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) +{ +#define IMPRESET_WAIT_MS_TIME 5 + + if (event_type == HNS3_VECTOR0_EVENT_RST && + regclr & BIT(HNS3_VECTOR0_IMPRESET_INT_B) && + hw->revision >= PCI_REVISION_ID_HIP09_A) { + rte_delay_ms(IMPRESET_WAIT_MS_TIME); + hns3_dbg(hw, "wait firmware watchdog initialization completed."); + } +} + static void hns3_interrupt_handler(void *param) { @@ -305,6 +318,7 @@ hns3_interrupt_handler(void *param) vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + hns3_delay_before_clear_event_cause(hw, event_cause, clearval); hns3_clear_event_cause(hw, event_cause, clearval); /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { From patchwork Thu May 18 11:29:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 126988 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B63DC42B3A; Thu, 18 May 2023 13:32:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8A37642D56; Thu, 18 May 2023 13:32:08 +0200 (CEST) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 3730E42D32; Thu, 18 May 2023 13:32:06 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4QMSSW1gMxzsSST; Thu, 18 May 2023 19:30:03 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 18 May 2023 19:32:03 +0800 From: Dongdong Liu To: , , , , CC: , , , Subject: [PATCH 5/5] net/hns3: add Tx/Rx descriptor logs Date: Thu, 18 May 2023 19:29:44 +0800 Message-ID: <20230518112944.32276-6-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20230518112944.32276-1-liudongdong3@huawei.com> References: <20230518112944.32276-1-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dengdui Huang Add Tx/Rx descriptor logs, controlled by 'RTE_ETHDEV_DEBUG_RX/TX' compile time flag with 'pmd.net.hns3.rx/tx' log type. Signed-off-by: Dengdui Huang Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_ethdev.c | 6 ++++++ drivers/net/hns3/hns3_logs.h | 18 ++++++++++++++++++ drivers/net/hns3/hns3_rxtx.c | 4 ++++ drivers/net/hns3/hns3_rxtx.h | 29 +++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 664226a6ef..07d907d6a1 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6625,3 +6625,9 @@ RTE_PMD_REGISTER_PARAM_STRING(net_hns3, HNS3_DEVARG_MBX_TIME_LIMIT_MS "= "); RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); +#ifdef RTE_ETHDEV_DEBUG_RX +RTE_LOG_REGISTER_SUFFIX(hns3_logtype_rx, rx, DEBUG); +#endif +#ifdef RTE_ETHDEV_DEBUG_TX +RTE_LOG_REGISTER_SUFFIX(hns3_logtype_tx, tx, DEBUG); +#endif diff --git a/drivers/net/hns3/hns3_logs.h b/drivers/net/hns3/hns3_logs.h index c880f752ab..47d3a13220 100644 --- a/drivers/net/hns3/hns3_logs.h +++ b/drivers/net/hns3/hns3_logs.h @@ -31,4 +31,22 @@ extern int hns3_logtype_driver; #define hns3_dbg(hw, fmt, args...) \ PMD_DRV_LOG_RAW(hw, RTE_LOG_DEBUG, fmt "\n", ## args) +#ifdef RTE_ETHDEV_DEBUG_RX +extern int hns3_logtype_rx; +#define PMD_RX_LOG(hw, level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, hns3_logtype_rx, "%s %s(): " fmt "\n", \ + (hw)->data->name, __func__, ## args) +#else +#define PMD_RX_LOG(hw, level, fmt, args...) do { } while (0) +#endif + +#ifdef RTE_ETHDEV_DEBUG_TX +extern int hns3_logtype_tx; +#define PMD_TX_LOG(hw, level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, hns3_logtype_tx, "%s %s(): " fmt "\n", \ + (hw)->data->name, __func__, ## args) +#else +#define PMD_TX_LOG(hw, level, fmt, args...) do { } while (0) +#endif + #endif /* HNS3_LOGS_H */ diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 8c3355bbde..6468da903e 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2618,6 +2618,7 @@ hns3_recv_scattered_pkts(void *rx_queue, */ rxd = rxdp[(bd_base_info & (1u << HNS3_RXD_VLD_B)) - (1u << HNS3_RXD_VLD_B)]; + RX_BD_LOG(&rxq->hns->hw, DEBUG, &rxd); nmb = hns3_rx_alloc_buffer(rxq); if (unlikely(nmb == NULL)) { @@ -4274,6 +4275,8 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) tx_next_use = 0; tx_bak_pkt = txq->sw_ring; } + if (m_seg != NULL) + TX_BD_LOG(&txq->hns->hw, DEBUG, desc); i++; } while (m_seg != NULL); @@ -4281,6 +4284,7 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) /* Add end flag for the last Tx Buffer Descriptor */ desc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_FE_B)); + TX_BD_LOG(&txq->hns->hw, DEBUG, desc); /* Increment bytes counter */ txq->basic_stats.bytes += tx_pkt->pkt_len; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 7685ac2ea3..b6a6513307 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -553,6 +553,35 @@ struct hns3_tx_queue { bool enabled; /* indicate if Tx queue has been enabled */ }; +#define RX_BD_LOG(hw, level, rxdp) \ + PMD_RX_LOG(hw, level, "Rx descriptor: " \ + "l234_info=%#x pkt_len=%u size=%u rss_hash=%#x fd_id=%u vlan_tag=%u " \ + "o_dm_vlan_id_fb=%#x ot_vlan_tag=%u bd_base_info=%#x", \ + rte_le_to_cpu_32((rxdp)->rx.l234_info), \ + rte_le_to_cpu_16((rxdp)->rx.pkt_len), \ + rte_le_to_cpu_16((rxdp)->rx.size), \ + rte_le_to_cpu_32((rxdp)->rx.rss_hash), \ + rte_le_to_cpu_16((rxdp)->rx.fd_id), \ + rte_le_to_cpu_16((rxdp)->rx.vlan_tag), \ + rte_le_to_cpu_16((rxdp)->rx.o_dm_vlan_id_fb), \ + rte_le_to_cpu_16((rxdp)->rx.ot_vlan_tag), \ + rte_le_to_cpu_32((rxdp)->rx.bd_base_info)) + +#define TX_BD_LOG(hw, level, txdp) \ + PMD_TX_LOG(hw, level, "Tx descriptor: " \ + "vlan_tag=%u send_size=%u type_cs_vlan_tso_len=%#x outer_vlan_tag=%u " \ + "tv=%#x ol_type_vlan_len_msec=%#x paylen_fd_dop_ol4cs=%#x " \ + "tp_fe_sc_vld_ra_ri=%#x ckst_mss=%u", \ + rte_le_to_cpu_16((txdp)->tx.vlan_tag), \ + rte_le_to_cpu_16((txdp)->tx.send_size), \ + rte_le_to_cpu_32((txdp)->tx.type_cs_vlan_tso_len), \ + rte_le_to_cpu_16((txdp)->tx.outer_vlan_tag), \ + rte_le_to_cpu_16((txdp)->tx.tv), \ + rte_le_to_cpu_32((txdp)->tx.ol_type_vlan_len_msec), \ + rte_le_to_cpu_32((txdp)->tx.paylen_fd_dop_ol4cs), \ + rte_le_to_cpu_16((txdp)->tx.tp_fe_sc_vld_ra_ri), \ + rte_le_to_cpu_16((txdp)->tx.ckst_mss)) + #define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \ ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)