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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 20:25:19.6773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d9c35ee-24c3-47f3-1770-08db5714d5a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4167 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds querying the HCA capabilities for maximum supported pattern length for Header Modify Pattern objects. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 14 ++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 3 ++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index d0907fcd49..95d86d9573 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1086,6 +1086,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, flow_counter_access_aso); attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, flow_access_aso_opc_mod); + attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, + wqe_based_flow_table_update_cap); /* * Flex item support needs max_num_prog_sample_field * from the Capabilities 2 table for PARSE_GRAPH_NODE @@ -1293,6 +1295,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->rss_ind_tbl_cap = MLX5_GET (per_protocol_networking_offload_caps, hcattr, rss_ind_tbl_cap); + if (attr->wqe_based_flow_table_sup) { + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { + DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); + return rc; + } + attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, + hcattr, + max_header_modify_pattern_length); + } /* Query HCA attribute for ROCE. */ if (attr->roce) { hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index ce173bc36a..410ada31b8 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -299,6 +299,8 @@ struct mlx5_hca_attr { uint32_t flow_access_aso_opc_mod:8; uint32_t cross_vhca:1; uint32_t lag_rx_port_affinity:1; + uint32_t wqe_based_flow_table_sup:1; + uint8_t max_header_modify_pattern_length; }; /* LAG Context. */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ed3d5efbb7..8cf9316589 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2289,7 +2289,8 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits { u8 rtc_index_mode[0x5]; u8 reserved_at_58[0x3]; u8 rtc_log_depth_max[0x5]; - u8 reserved_at_60[0x10]; + u8 reserved_at_60[0x8]; + u8 max_header_modify_pattern_length[0x8]; u8 ste_format[0x10]; u8 stc_action_type[0x80]; u8 header_insert_type[0x10]; From patchwork Wed May 17 20:24:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 126951 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 179B942B2F; Wed, 17 May 2023 22:25:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7534742D37; Wed, 17 May 2023 22:25:26 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2074.outbound.protection.outlook.com [40.107.223.74]) by mails.dpdk.org (Postfix) with ESMTP id 9FBBC42B8B for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 20:25:23.2967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6380ae1-d314-49b3-fc4a-08db5714d7ce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4221 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds validation for the number of modify field actions, when working with HW Steering. If translation of modify field actions generated more HW commands than supported by the FW, then proper error is returned. Additionally, number of generated commands is logged, along with a number of NOP commands added. This validation is only valid for HWS template tables, in groups > 0. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_hw.c | 51 +++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 7e0ee8d883..0a7416c7a1 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1086,6 +1086,53 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev, return 0; } +static uint32_t +flow_hw_count_nop_modify_field(struct mlx5_hw_modify_header_action *mhdr) +{ + uint32_t i; + uint32_t nops = 0; + + for (i = 0; i < mhdr->mhdr_cmds_num; ++i) { + struct mlx5_modification_cmd cmd = mhdr->mhdr_cmds[i]; + + cmd.data0 = rte_be_to_cpu_32(cmd.data0); + if (cmd.action_type == MLX5_MODIFICATION_TYPE_NOP) + ++nops; + } + return nops; +} + +static int +flow_hw_validate_compiled_modify_field(struct rte_eth_dev *dev, + const struct mlx5_flow_template_table_cfg *cfg, + struct mlx5_hw_modify_header_action *mhdr, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; + + /* + * Header modify pattern length limitation is only valid for HWS groups, i.e. groups > 0. + * In group 0, MODIFY_FIELD actions are handled with header modify actions + * managed by rdma-core. + */ + if (cfg->attr.flow_attr.group != 0 && + mhdr->mhdr_cmds_num > hca_attr->max_header_modify_pattern_length) { + uint32_t nops = flow_hw_count_nop_modify_field(mhdr); + + DRV_LOG(ERR, "Too many modify header commands generated from " + "MODIFY_FIELD actions. " + "Generated HW commands = %u (amount of NOP commands = %u). " + "Maximum supported = %u.", + mhdr->mhdr_cmds_num, nops, + hca_attr->max_header_modify_pattern_length); + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "Number of MODIFY_FIELD actions exceeds maximum " + "supported limit of actions"); + } + return 0; +} + static int flow_hw_represented_port_compile(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -1704,6 +1751,10 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev, uint32_t bulk_size; size_t mhdr_len; + if (flow_hw_validate_compiled_modify_field(dev, cfg, &mhdr, error)) { + __flow_hw_action_template_destroy(dev, acts); + return -rte_errno; + } acts->mhdr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*acts->mhdr), 0, SOCKET_ID_ANY); if (!acts->mhdr)