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Mon, 15 May 2023 23:37:54 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v1 1/7] doc: fix blank lines in modify field action description Date: Tue, 16 May 2023 09:37:41 +0300 Message-ID: <20230516063747.3047758-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E644:EE_|LV8PR12MB9109:EE_ X-MS-Office365-Filtering-Correlation-Id: abec1f8a-9831-4e89-9a3c-08db55d81635 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ejvw639fQvrjpLrCLrKWt1uEMdLhwEXBMjXUL1eh8WPJGNxyLoClFhLKGoMfn8uUTmVOToYKXIyBKboPkLICCAa3wMkuQcl+liqTGbzQibQZQxT2dgSxVIBMTgNTnqh5x+4whs3yLQv4mDX4RKq7cZMAvRkCO5nLnYLaM4hkXifeamFoH9NOzK1QZ+v2xa3EtewofzOcUQPU048fgRzVJxNQreL5QmWzljv1DuJVHL+X0vw3mj13nMlsjKuOHf8EmGjpLm15t85XEQGbyd2NjcGA/L0VK0YfXXGQtU1mBt4rvFIVZ/oRqTYW11PvFHygIah9zaM63OGK5StH5lDDXs9OCuFz5Cig42Bd8RCfe/EtHA73VCMpS4jWsOOxwm0uITFtdmoNdmgGmdZxTABesYBIoV//0d21/N71lsQDoeBIqcjU2Y83eNGDMtbgUy8LgKvfHxvJi6IxAuX/ckw+8RUDSR64GkAZZSIZITnmEMsJP4VCMsonK6s0LT5p+n7rHQgKd82AxCH/9nAaHXyJbZjjnr/dqDCKEMQBXOmvAuJkJYI1qwVkyPykXmJ5qbghDu2rE1uJ9BEDahsMKsYML68pKys+4W3vw2gGKhcY2xeP7XvjhEvWzmESRhkUkYGGDEdBKSbh84gv7D7zyL6w3XgvJGIa2Jm20uwQJpywcwAxQ+ULXALkEglKkUooM0wKqJX39sfWO0h2xIONkSFFYVnp0w1nn7V/ytlTRIXnquA= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199021)(46966006)(40470700004)(36840700001)(40480700001)(7636003)(86362001)(40460700003)(478600001)(54906003)(82310400005)(55016003)(7696005)(6666004)(36756003)(356005)(186003)(26005)(1076003)(6286002)(5660300002)(70206006)(70586007)(2906002)(83380400001)(6916009)(4326008)(316002)(82740400003)(8936002)(8676002)(426003)(336012)(2616005)(41300700001)(36860700001)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 06:37:57.5559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abec1f8a-9831-4e89-9a3c-08db55d81635 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E644.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9109 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The modify field action description inside "Generic flow API (rte_flow)" documentation, lists all operations supported for a destination field. In addition, it lists the values supported for a encapsulation level field. Before the lists, in both cases, miss a blank line causing them to look regular text lines. This patch adds the blank lines. Fixes: 73b68f4c54a0 ("ethdev: introduce generic modify flow action") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum --- doc/guides/prog_guide/rte_flow.rst | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 32fc45516a..e7faa368a1 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2917,20 +2917,23 @@ The immediate value ``RTE_FLOW_FIELD_VALUE`` (or a pointer to it ``RTE_FLOW_FIELD_START`` is used to point to the beginning of a packet. See ``enum rte_flow_field_id`` for the list of supported fields. -``op`` selects the operation to perform on a destination field. +``op`` selects the operation to perform on a destination field: + - ``set`` copies the data from ``src`` field to ``dst`` field. - ``add`` adds together ``dst`` and ``src`` and stores the result into ``dst``. -- ``sub`` subtracts ``src`` from ``dst`` and stores the result into ``dst`` +- ``sub`` subtracts ``src`` from ``dst`` and stores the result into ``dst``. ``width`` defines a number of bits to use from ``src`` field. ``level`` is used to access any packet field on any encapsulation level -as well as any tag element in the tag array. -- ``0`` means the default behaviour. Depending on the packet type, it can -mean outermost, innermost or anything in between. +as well as any tag element in the tag array: + +- ``0`` means the default behaviour. Depending on the packet type, + it can mean outermost, innermost or anything in between. - ``1`` requests access to the outermost packet encapsulation level. - ``2`` and subsequent values requests access to the specified packet -encapsulation level, from outermost to innermost (lower to higher values). + encapsulation level, from outermost to innermost (lower to higher values). + For the tag array (in case of multiple tags are supported and present) ``level`` translates directly into the array index. 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Mon, 15 May 2023 23:37:56 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v1 2/7] doc: fix blank line in asynchronous operations description Date: Tue, 16 May 2023 09:37:42 +0300 Message-ID: <20230516063747.3047758-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C984:EE_|IA0PR12MB7530:EE_ X-MS-Office365-Filtering-Correlation-Id: 333d81e6-3be2-4347-9dac-08db55d8176d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4dUKhSZopRldg2Y1f0o3rhZibeSnWuhk9MNjS0zTnKRRtPO5Te0+rE60x8QVkgt8zpi6QqZPCQpZfjsutnd4x5yF2BEBFOjzITHoRbJvkGzfgxi5t6pIHEsxJLBQaVYJ5TRf/33L9BQUDTgnkI0LnJoEsUn2kYHurX8Bb0qAoRqWSxjY0TWU8m8/i45DKOO2ABXBhk154embBgJwSCor50x//FH0FNYwFLIwFb7Xp1+Rn9OWqc7PsKOVFktb0i6/fVlsVtUZFgcntpPqhZcIB0IKuon0c4OJuyog+uy7GQsY1V3G6vL5QNfaYtL2TlGB0hfj4cSlqTzbq98sLQENNVNRLtcLGLF1KSN84Z/ZyoX0H5jiP1wL8INq0SmXT6Go8feFHxUh2XcHZIFsa8PKSADvJ6WpXe4gpm7j2eLuaAAkjTQGfjD9U7lJ26ZjoZvOS0dgfCMwCFn39KVG92ci90ZulrqC0wPp1oquaVahyRQ4RvlMp5Lf68TRKnRL89SbGIgCKQ0p0WizaT4qm7OescRqnkr8E1/DqnPrPINV0iMNO0M+tTwDC6R4CU/TkMF6cZu5q0v1RVCEI3KZVrDbsHeXKM9C21kW5Hdr3FaueXrzxAbrN8Snj8lQyTMhniyQcwpqFBUMn4YXEcSyzgIk0tx4ANIslWdEVYD8aeVVJohBQm3etGTpIlq4IlSwyyfDKANNz/xFeyrQW6xIl1xcqAB829Q00cSvXA4nznaBwyIT4e3sDpWv4ffQSA+ZG9kH X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Before the first bullet, miss a blank line causing it to look a regular text line. This patch adds the blank line. Fixes: 197e820c6685 ("ethdev: bring in async queue-based flow rules operations") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index e7faa368a1..76e69190fc 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -3702,6 +3702,7 @@ Asynchronous operations ----------------------- Flow rules management can be done via special lockless flow management queues. + - Queue operations are asynchronous and not thread-safe. - Operations can thus be invoked by the app's datapath, From patchwork Tue May 16 06:37:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 126868 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E7B042B1F; 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Mon, 15 May 2023 23:38:02 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 15 May 2023 23:38:01 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Mon, 15 May 2023 23:37:59 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" , , Subject: [PATCH v1 3/7] doc: fix wrong indentation in RSS action description Date: Tue, 16 May 2023 09:37:43 +0300 Message-ID: <20230516063747.3047758-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C984:EE_|DS0PR12MB8501:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ad59209-6ed0-487a-6d05-08db55d819e5 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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For "2" value, it uses 3 spaces as an indentation instead of 2 after line breaking, causing the first line to be bold. This patch updates the number of spaces in the indentation. Fixes: 18aee2861a1f ("ethdev: add encap level to RSS flow API action") Cc: adrien.mazarguil@6wind.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 76e69190fc..25b57bf86d 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -1954,8 +1954,8 @@ Also, regarding packet encapsulation ``level``: level. - ``2`` and subsequent values request RSS to be performed on the specified - inner packet encapsulation level, from outermost to innermost (lower to - higher values). + inner packet encapsulation level, from outermost to innermost (lower to + higher values). Values other than ``0`` are not necessarily supported. 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Mon, 15 May 2023 23:38:01 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" Subject: [PATCH v1 4/7] net/mlx5: reduce modify field encapsulation level size Date: Tue, 16 May 2023 09:37:44 +0300 Message-ID: <20230516063747.3047758-5-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C984:EE_|SA1PR12MB7409:EE_ X-MS-Office365-Filtering-Correlation-Id: a577ea9c-86bf-42e5-05e7-08db55d81c24 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nZa/ZTawxvJHJ8oBH69ipkXsP7J1XK5Ijrc0ypCdfm21akeXDCYovNwiwEhaWw1Hgvh9M8itiKFfB6ekH32iPYvRQ7MnbmVkyuiP95yGSqsUKmhfmQ6D/MHa/w/tOZrWJ0C94ajRz1B7kg8Mf6UM0E/kiq53NJR052PjSoeuSvi7Dx5GVdUf55GXC7wBA31ezV5ezyzeOpQDHyiJXTdt383lHHSJbCV7hObs2FkGch1lXFZlt9sLSf+HLn443bdlJtj/vzKHozP1xeuZoKl2vKIk981N9RMdon8oRsckJYF32Fz7kaW9xz2K2CTGuPY9UpkVL51nKgCDQuPdHRdeTj+0s3ljxoqE0ODPd+K7MIDqX3KtH8Pr+bay5hwJTfzQ+T+rXwVWPmlyi656LtqiFgCCtC8f2G6QS6p62KV5F4sEN49y+hdHT7L+/SB3aHyUcU027AWzPSVE4fP0lGvPxbby3eFEkcPnS8HllnTDcMpeBpIxBtq1buMFV4zII0ei4ABoBJk4Aegeri5dvDshuXb5Pj3x2WNjVP5lrdiQum3ROM7QeOIOz/8bQKE5LcCCaVYCVsQIKgVbd/PKredlHT3z1PBnilUaAkql5OXS3E8F7p4BdcV8Z2rfRXwfdUMw96R14Ehv87JnOUxnSbHaNHjpcCv/F5HrHCa5WD/aUFxlRwyMvY5POzaS+BBmTNSuelyseqF0UKj03tnYbydO2F6QQ0nmoKqQelZ3RQo9iZA= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199021)(36840700001)(40470700004)(46966006)(83380400001)(36860700001)(47076005)(336012)(426003)(478600001)(6666004)(7696005)(54906003)(2616005)(1076003)(26005)(6286002)(186003)(40460700003)(2906002)(36756003)(4326008)(70206006)(82740400003)(6916009)(70586007)(7636003)(356005)(41300700001)(8676002)(82310400005)(8936002)(316002)(55016003)(86362001)(40480700001)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 06:38:07.5539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a577ea9c-86bf-42e5-05e7-08db55d81c24 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C984.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7409 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The type of "level" field in "rte_flow_action_modify_data" structure is uint32_t for now, but it is going to be changed to uint8_t in the next patch. For representing encapsulation level, 8 bits are more than enough and this change shouldn't affect the current implementation. However, when action template is created, the PMD requests to provide this field "fully masked" in action mask. The "fully masked" value is different between uint32_t and uint8_t types. This patch reduces all modify field encapsulation level "fully masked" initializations to use UINT8_MAX instead of UINT32_MAX. This change will avoid compilation warning after it will be changed to uint8_t by API. Signed-off-by: Michael Baum --- drivers/net/mlx5/mlx5_flow_hw.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 7e0ee8d883..1b68a19900 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3565,7 +3565,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "immediate value, pointer and hash result cannot be used as destination"); - if (mask_conf->dst.level != UINT32_MAX) + if (mask_conf->dst.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "destination encapsulation level must be fully masked"); @@ -3579,7 +3579,7 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, "destination field mask and template are not equal"); if (action_conf->src.field != RTE_FLOW_FIELD_POINTER && action_conf->src.field != RTE_FLOW_FIELD_VALUE) { - if (mask_conf->src.level != UINT32_MAX) + if (mask_conf->src.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "source encapsulation level must be fully masked"); @@ -4450,7 +4450,7 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev, .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = RTE_FLOW_FIELD_VLAN_ID, - .level = 0xffffffff, .offset = 0xffffffff, + .level = 0xff, .offset = 0xffffffff, }, .src = { .field = RTE_FLOW_FIELD_VALUE, @@ -4583,12 +4583,12 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev, .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -5653,7 +5653,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5677,12 +5677,12 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -6009,7 +6009,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -6182,12 +6182,12 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = UINT32_MAX, + .level = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, From patchwork Tue May 16 06:37:45 2023 Content-Type: text/plain; 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Mon, 15 May 2023 23:38:04 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" Subject: [PATCH v1 5/7] ethdev: add GENEVE TLV option modification support Date: Tue, 16 May 2023 09:37:45 +0300 Message-ID: <20230516063747.3047758-6-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C97E:EE_|PH7PR12MB6859:EE_ X-MS-Office365-Filtering-Correlation-Id: 62ea44ed-3348-4ec6-8191-08db55d81fbe X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RO1YfK3XckpbB6pQ7lp8bx8VKc/GHEArqjlqTpa5bUXm4SYUkJiS5/vm9T0zzXsZ1SVhWw2h82BnEGy87gjOG/9TiYDEjK3disBaEvrm9jHsAAJNY9D9jFcyXz1RVS5TjrX4wY0xGG28bsSH2SPQ4BfE37u5q/vQ2DjSkITH7xNDb+BuitF8oQIWDVV2xHo1NwLyJ1LDv31Tj1J+yeuc5PUG5fyr+x284d3v8z4a0lur/BKJA/Oebp4XwIFhsrU35QWRmgNPOv0/wS164Fmf2BGzxr5bWxtVWYftBUykoXKW8G6g+7Mwf9h4NDUgEstvciX0x2isVRSq1ob7zWorcIBGyQpqR8Yo8xQJeThcWVQMOPX31mdrVQIMczrAxAcWXQvqlQqLpG5n18H0bfdKgVkWY1D1fR+aguIJxGBvi+9nH9bn7fK2D2hvCrk5oNJCV+ngS40CYWJRTsnM09XSGKQbsIFXqu1gwCOx8WKm/bTkh3tyE7QHjPkHVUXiNH5KseQqvsNv6hNDBBFekUt5iuCcgcGetgi5UsNHflh5gFXOF6SzGdVMGoyLLjfrsMm4ODSuyrN+/aYou7x1tj8e66ab9NCi/t2fpugzZdX3VKnK47G/K9vyF1WTLn9M+w4s6EioZQYEi0OPbhWVclhWu60qrVl4QBvZ9tPeHGzINcZUP3r29ycKm6mPh8PPGRmAwY9hWiFACJ5eMkQty4axQd/7jLBkMp3BvqeABPJe6Hbc9/FjbCmi/s8BJM0MlGWtyWyJlRB5Ex614SGyx2ENtg== X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(478600001)(40460700003)(54906003)(8676002)(86362001)(8936002)(5660300002)(7636003)(2906002)(36756003)(82310400005)(4326008)(6916009)(70586007)(70206006)(82740400003)(356005)(316002)(40480700001)(41300700001)(36860700001)(47076005)(186003)(6286002)(2616005)(1076003)(26005)(55016003)(83380400001)(336012)(426003)(7696005)(6666004)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 06:38:13.5838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62ea44ed-3348-4ec6-8191-08db55d81fbe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C97E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6859 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add modify field support for GENEVE option fields: - "RTE_FLOW_FIELD_GENEVE_OPT_TYPE" - "RTE_FLOW_FIELD_GENEVE_OPT_CLASS" - "RTE_FLOW_FIELD_GENEVE_OPT_DATA" Each GENEVE TLV option is identified by both its "class" and "type", so 2 new fields were added to "rte_flow_action_modify_data" structure to help specify which option to modify. To get room for those 2 new fields, the "level" field move to use "uint8_t" which is more than enough for encapsulation level. Signed-off-by: Michael Baum --- app/test-pmd/cmdline_flow.c | 48 +++++++++++++++++++++++- doc/guides/prog_guide/rte_flow.rst | 12 ++++++ doc/guides/rel_notes/release_23_07.rst | 3 ++ lib/ethdev/rte_flow.h | 51 +++++++++++++++++++++++++- 4 files changed, 112 insertions(+), 2 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 58939ec321..8c1dea53c0 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -636,11 +636,15 @@ enum index { ACTION_MODIFY_FIELD_DST_TYPE_VALUE, ACTION_MODIFY_FIELD_DST_LEVEL, ACTION_MODIFY_FIELD_DST_LEVEL_VALUE, + ACTION_MODIFY_FIELD_DST_TYPE_ID, + ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, ACTION_MODIFY_FIELD_SRC_TYPE, ACTION_MODIFY_FIELD_SRC_TYPE_VALUE, ACTION_MODIFY_FIELD_SRC_LEVEL, ACTION_MODIFY_FIELD_SRC_LEVEL_VALUE, + ACTION_MODIFY_FIELD_SRC_TYPE_ID, + ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, ACTION_MODIFY_FIELD_SRC_VALUE, ACTION_MODIFY_FIELD_SRC_POINTER, @@ -854,7 +858,9 @@ static const char *const modify_field_ids[] = { "ipv4_ecn", "ipv6_ecn", "gtp_psc_qfi", "meter_color", "ipv6_proto", "flex_item", - "hash_result", NULL + "hash_result", + "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", + NULL }; static const char *const meter_colors[] = { @@ -2295,6 +2301,8 @@ static const enum index next_action_sample[] = { static const enum index action_modify_field_dst[] = { ACTION_MODIFY_FIELD_DST_LEVEL, + ACTION_MODIFY_FIELD_DST_TYPE_ID, + ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, ACTION_MODIFY_FIELD_SRC_TYPE, ZERO, @@ -2302,6 +2310,8 @@ static const enum index action_modify_field_dst[] = { static const enum index action_modify_field_src[] = { ACTION_MODIFY_FIELD_SRC_LEVEL, + ACTION_MODIFY_FIELD_SRC_TYPE_ID, + ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, ACTION_MODIFY_FIELD_SRC_VALUE, ACTION_MODIFY_FIELD_SRC_POINTER, @@ -6388,6 +6398,24 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_DST_TYPE_ID] = { + .name = "dst_type_id", + .help = "destination field type ID", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + dst.type)), + .call = parse_vc_conf, + }, + [ACTION_MODIFY_FIELD_DST_CLASS_ID] = { + .name = "dst_class", + .help = "destination field class ID", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_action_modify_field, + dst.class_id)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_DST_OFFSET] = { .name = "dst_offset", .help = "destination field bit offset", @@ -6423,6 +6451,24 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_SRC_TYPE_ID] = { + .name = "src_type_id", + .help = "source field type ID", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + src.type)), + .call = parse_vc_conf, + }, + [ACTION_MODIFY_FIELD_SRC_CLASS_ID] = { + .name = "src_class", + .help = "source field class ID", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_action_modify_field, + src.class_id)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_SRC_OFFSET] = { .name = "src_offset", .help = "source field bit offset", diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 25b57bf86d..cd38f0de46 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2937,6 +2937,14 @@ as well as any tag element in the tag array: For the tag array (in case of multiple tags are supported and present) ``level`` translates directly into the array index. +``type`` is used to specify (along with ``class_id``) the Geneve option which +is being modified. +This field is relevant only for ``RTE_FLOW_FIELD_GENEVE_OPT_XXXX`` type. + +``class_id`` is used to specify (along with ``type``) the Geneve option which +is being modified. +This field is relevant only for ``RTE_FLOW_FIELD_GENEVE_OPT_XXXX`` type. + ``flex_handle`` is used to specify the flex item pointer which is being modified. ``flex_handle`` and ``level`` are mutually exclusive. @@ -2994,6 +3002,10 @@ value as sequence of bytes {xxx, xxx, 0x85, xxx, xxx, xxx}. +-----------------+----------------------------------------------------------+ | ``level`` | encapsulation level of a packet field or tag array index | +-----------------+----------------------------------------------------------+ + | ``type`` | geneve option type | + +-----------------+----------------------------------------------------------+ + | ``class_id`` | geneve option class ID | + +-----------------+----------------------------------------------------------+ | ``flex_handle`` | flex item handle of a packet field | +-----------------+----------------------------------------------------------+ | ``offset`` | number of bits to skip at the beginning | diff --git a/doc/guides/rel_notes/release_23_07.rst b/doc/guides/rel_notes/release_23_07.rst index a9b1293689..ce1755096f 100644 --- a/doc/guides/rel_notes/release_23_07.rst +++ b/doc/guides/rel_notes/release_23_07.rst @@ -84,6 +84,9 @@ API Changes Also, make sure to start the actual text at the margin. ======================================================= +* The ``level`` field in experimental structure + ``struct rte_flow_action_modify_data`` was reduced to 8 bits. + ABI Changes ----------- diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 713ba8b65c..b82eb0c0a8 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3773,6 +3773,9 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_IPV6_PROTO, /**< IPv6 next header. */ RTE_FLOW_FIELD_FLEX_ITEM, /**< Flex item. */ RTE_FLOW_FIELD_HASH_RESULT, /**< Hash result. */ + RTE_FLOW_FIELD_GENEVE_OPT_TYPE, /**< GENEVE option type */ + RTE_FLOW_FIELD_GENEVE_OPT_CLASS,/**< GENEVE option class */ + RTE_FLOW_FIELD_GENEVE_OPT_DATA /**< GENEVE option data */ }; /** @@ -3788,7 +3791,53 @@ struct rte_flow_action_modify_data { struct { /** Encapsulation level or tag index or flex item handle. */ union { - uint32_t level; + struct { + /** + * Packet encapsulation level containing + * the field modify to. + * + * - @p 0 requests the default behavior. + * Depending on the packet type, it + * can mean outermost, innermost or + * anything in between. + * + * It basically stands for the + * innermost encapsulation level + * modification can be performed on + * according to PMD and device + * capabilities. + * + * - @p 1 requests modification to be + * performed on the outermost packet + * encapsulation level. + * + * - @p 2 and subsequent values request + * modification to be performed on + * the specified inner packet + * encapsulation level, from + * outermost to innermost (lower to + * higher values). + * + * Values other than @p 0 are not + * necessarily supported. + * + * For RTE_FLOW_FIELD_TAG it represents + * the tag element in the tag array. + */ + uint8_t level; + /** + * Geneve option type. relevant only + * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + uint8_t type; + /** + * Geneve option class. relevant only + * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + rte_be16_t class_id; + }; struct rte_flow_item_flex_handle *flex_handle; }; /** Number of bits to skip from a field. */ From patchwork Tue May 16 06:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 126870 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4824342B1F; Tue, 16 May 2023 08:38:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C082142D5F; Tue, 16 May 2023 08:38:15 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2078.outbound.protection.outlook.com [40.107.100.78]) by mails.dpdk.org (Postfix) with ESMTP id EAFD742D5D for ; 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Mon, 15 May 2023 23:38:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 15 May 2023 23:38:07 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Mon, 15 May 2023 23:38:06 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" Subject: [PATCH v1 6/7] ethdev: add MPLS header modification support Date: Tue, 16 May 2023 09:37:46 +0300 Message-ID: <20230516063747.3047758-7-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E645:EE_|DS0PR12MB7582:EE_ X-MS-Office365-Filtering-Correlation-Id: 45913d20-04f3-442a-8b7b-08db55d81f3f X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 06:38:12.7206 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45913d20-04f3-442a-8b7b-08db55d81f3f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E645.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7582 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for MPLS modify header using "RTE_FLOW_FIELD_MPLS" id. Since MPLS heaser might appear more the one time in inner/outer/tunnel, a new field was added to "rte_flow_action_modify_data" structure in addition to "level" field. The "sub_level" field is the index of the header inside encapsulation level. It is used for modify multiple MPLS headers in same encapsulation level. This addition enables to modify multiple VLAN headers too, so the description of "RTE_FLOW_FIELD_VLAN_XXXX" was updated. Signed-off-by: Michael Baum --- app/test-pmd/cmdline_flow.c | 24 ++++++++++++++- doc/guides/prog_guide/rte_flow.rst | 6 ++++ lib/ethdev/rte_flow.h | 47 ++++++++++++++++++++---------- 3 files changed, 61 insertions(+), 16 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 8c1dea53c0..5370be1e3c 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -636,6 +636,7 @@ enum index { ACTION_MODIFY_FIELD_DST_TYPE_VALUE, ACTION_MODIFY_FIELD_DST_LEVEL, ACTION_MODIFY_FIELD_DST_LEVEL_VALUE, + ACTION_MODIFY_FIELD_DST_SUB_LEVEL, ACTION_MODIFY_FIELD_DST_TYPE_ID, ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, @@ -643,6 +644,7 @@ enum index { ACTION_MODIFY_FIELD_SRC_TYPE_VALUE, ACTION_MODIFY_FIELD_SRC_LEVEL, ACTION_MODIFY_FIELD_SRC_LEVEL_VALUE, + ACTION_MODIFY_FIELD_SRC_SUB_LEVEL, ACTION_MODIFY_FIELD_SRC_TYPE_ID, ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, @@ -859,7 +861,7 @@ static const char *const modify_field_ids[] = { "ipv6_proto", "flex_item", "hash_result", - "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", + "geneve_opt_type", "geneve_opt_class", "geneve_opt_data", "mpls", NULL }; @@ -2301,6 +2303,7 @@ static const enum index next_action_sample[] = { static const enum index action_modify_field_dst[] = { ACTION_MODIFY_FIELD_DST_LEVEL, + ACTION_MODIFY_FIELD_DST_SUB_LEVEL, ACTION_MODIFY_FIELD_DST_TYPE_ID, ACTION_MODIFY_FIELD_DST_CLASS_ID, ACTION_MODIFY_FIELD_DST_OFFSET, @@ -2310,6 +2313,7 @@ static const enum index action_modify_field_dst[] = { static const enum index action_modify_field_src[] = { ACTION_MODIFY_FIELD_SRC_LEVEL, + ACTION_MODIFY_FIELD_SRC_SUB_LEVEL, ACTION_MODIFY_FIELD_SRC_TYPE_ID, ACTION_MODIFY_FIELD_SRC_CLASS_ID, ACTION_MODIFY_FIELD_SRC_OFFSET, @@ -6398,6 +6402,15 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_DST_SUB_LEVEL] = { + .name = "dst_sub_level", + .help = "destination field sub level", + .next = NEXT(action_modify_field_dst, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + dst.sub_level)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_DST_TYPE_ID] = { .name = "dst_type_id", .help = "destination field type ID", @@ -6451,6 +6464,15 @@ static const struct token token_list[] = { .call = parse_vc_modify_field_level, .comp = comp_none, }, + [ACTION_MODIFY_FIELD_SRC_SUB_LEVEL] = { + .name = "stc_sub_level", + .help = "source field sub level", + .next = NEXT(action_modify_field_src, + NEXT_ENTRY(COMMON_UNSIGNED)), + .args = ARGS(ARGS_ENTRY(struct rte_flow_action_modify_field, + src.sub_level)), + .call = parse_vc_conf, + }, [ACTION_MODIFY_FIELD_SRC_TYPE_ID] = { .name = "src_type_id", .help = "source field type ID", diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index cd38f0de46..1f681a38e4 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2937,6 +2937,10 @@ as well as any tag element in the tag array: For the tag array (in case of multiple tags are supported and present) ``level`` translates directly into the array index. +- ``sub_level`` is the index of the header inside encapsulation level. + It is used for modify either ``VLAN`` or ``MPLS`` headers which multiple of + them might be supported in same encapsulation level. + ``type`` is used to specify (along with ``class_id``) the Geneve option which is being modified. This field is relevant only for ``RTE_FLOW_FIELD_GENEVE_OPT_XXXX`` type. @@ -3002,6 +3006,8 @@ value as sequence of bytes {xxx, xxx, 0x85, xxx, xxx, xxx}. +-----------------+----------------------------------------------------------+ | ``level`` | encapsulation level of a packet field or tag array index | +-----------------+----------------------------------------------------------+ + | ``sub_level`` | header level inside encapsulation level | + +-----------------+----------------------------------------------------------+ | ``type`` | geneve option type | +-----------------+----------------------------------------------------------+ | ``class_id`` | geneve option class ID | diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index b82eb0c0a8..4b2e17e266 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3740,8 +3740,8 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_START = 0, /**< Start of a packet. */ RTE_FLOW_FIELD_MAC_DST, /**< Destination MAC Address. */ RTE_FLOW_FIELD_MAC_SRC, /**< Source MAC Address. */ - RTE_FLOW_FIELD_VLAN_TYPE, /**< 802.1Q Tag Identifier. */ - RTE_FLOW_FIELD_VLAN_ID, /**< 802.1Q VLAN Identifier. */ + RTE_FLOW_FIELD_VLAN_TYPE, /**< VLAN Tag Identifier. */ + RTE_FLOW_FIELD_VLAN_ID, /**< VLAN Identifier. */ RTE_FLOW_FIELD_MAC_TYPE, /**< EtherType. */ RTE_FLOW_FIELD_IPV4_DSCP, /**< IPv4 DSCP. */ RTE_FLOW_FIELD_IPV4_TTL, /**< IPv4 Time To Live. */ @@ -3775,7 +3775,8 @@ enum rte_flow_field_id { RTE_FLOW_FIELD_HASH_RESULT, /**< Hash result. */ RTE_FLOW_FIELD_GENEVE_OPT_TYPE, /**< GENEVE option type */ RTE_FLOW_FIELD_GENEVE_OPT_CLASS,/**< GENEVE option class */ - RTE_FLOW_FIELD_GENEVE_OPT_DATA /**< GENEVE option data */ + RTE_FLOW_FIELD_GENEVE_OPT_DATA, /**< GENEVE option data */ + RTE_FLOW_FIELD_MPLS /**< MPLS header. */ }; /** @@ -3821,22 +3822,38 @@ struct rte_flow_action_modify_data { * Values other than @p 0 are not * necessarily supported. * + * @note that for MPLS field, + * encapsulation level also include + * tunnel since MPLS may appear in + * outer, inner or tunnel. + * * For RTE_FLOW_FIELD_TAG it represents * the tag element in the tag array. */ uint8_t level; - /** - * Geneve option type. relevant only - * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX - * modification type. - */ - uint8_t type; - /** - * Geneve option class. relevant only - * for RTE_FLOW_FIELD_GENEVE_OPT_XXXX - * modification type. - */ - rte_be16_t class_id; + union { + /** + * Header level inside + * encapsulation level. + */ + uint8_t sub_level; + /** + * Geneve option identifier. + * relevant only for + * RTE_FLOW_FIELD_GENEVE_OPT_XXXX + * modification type. + */ + struct { + /** + * Geneve option type. + */ + uint8_t type; + /** + * Geneve option class. + */ + rte_be16_t class_id; + }; + }; }; struct rte_flow_item_flex_handle *flex_handle; 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Mon, 15 May 2023 23:38:08 -0700 From: Michael Baum To: CC: Ori Kam , Aman Singh , "Yuying Zhang" , Ferruh Yigit , "Thomas Monjalon" Subject: [PATCH v1 7/7] net/mlx5: add MPLS modify field support Date: Tue, 16 May 2023 09:37:47 +0300 Message-ID: <20230516063747.3047758-8-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230516063747.3047758-1-michaelba@nvidia.com> References: <20230516063747.3047758-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT060:EE_|CY8PR12MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: 641f53af-f06b-4ee4-ac85-08db55d821c3 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S8B7OfGc8jQOlQYCzv5pTToeJMPP44OBFqOBuuWoMi5eP3ofKKjfz+phZl+UfNlNDq2xgfvTkNKFDCJwCN9WMC9BcLYgQDvyFMoZullrwutknaFvzDwNvtC9jnvgfqyAoJVhwmQ4h12QFO0q272UO9CFaME98criuSIFigGs3diNV/PeFVcFtTjvvDfb+uiDVn0tg/upeq9qklJA1MwObVcXSIRECJXOdvQDPxn0esufLrFSzdh5g+mA6lat8/S9ppriPXTmhFQoSZrXLJrahRpOvALx1VIQ5GQL1r77g9la/VYVoNsTx17dMSWZQUkxaaCHWpFukFtoSrP+UBJb39O8K6QJE3WXQAIynxe971RVsoYZr7bcmROdXloTCMLzgFc/LLhnuk9c3KhiKNqnml7PUmPttYgga1jiCeInLyfhxdCnpbo28JJ5OZmlpATetwrQ2s0LA62y7eLrV22z7eYWAZ4V63weEY7ae6GrsTxvn4xa8IDsjuISuz/6wkGpwTyQbBzBCVEkR8q8hArrCpnuV5asmuI8ZNL9Fm7vsx+muFFBssn1JYniu1pR1cb7vFxnvVbW+i0mSGlete+zTIX9HC4KzEb4C7VeXwmCtsxEzOJCMoJzduQDMeLiHzH8ZNV8n0r4XNNUcYoEh1dMK/37G8Ant5E6P7I8hsVAFIOcmixa6S5WfoRGI4dVVCpzrbfmucKaGkgKeCBRNBrJQ8WB8iVd0girUZnnBSOECOZxEy7wnKisEJ2abZp81/TJ X-Forefront-Antispam-Report: CIP:216.228.118.233; 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For now it is supported only to copy from. Signed-off-by: Michael Baum --- drivers/common/mlx5/mlx5_prm.h | 5 +++++ drivers/net/mlx5/mlx5_flow_dv.c | 23 +++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 16 +++++++++------- 3 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ed3d5efbb7..04c1400a1e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -787,6 +787,11 @@ enum mlx5_modification_field { MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, MLX5_MODI_HASH_RESULT = 0x81, + MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a, + MLX5_MODI_IN_MPLS_LABEL_1, + MLX5_MODI_IN_MPLS_LABEL_2, + MLX5_MODI_IN_MPLS_LABEL_3, + MLX5_MODI_IN_MPLS_LABEL_4, MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, MLX5_MODI_INVALID = INT_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f136f43b0a..93cce16a1e 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1388,6 +1388,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_GENEVE_VNI: return 24; case RTE_FLOW_FIELD_GTP_TEID: + case RTE_FLOW_FIELD_MPLS: case RTE_FLOW_FIELD_TAG: return 32; case RTE_FLOW_FIELD_MARK: @@ -1435,6 +1436,12 @@ flow_modify_info_mask_32_masked(uint32_t length, uint32_t off, uint32_t post_mas return rte_cpu_to_be_32(mask & post_mask); } +static __rte_always_inline enum mlx5_modification_field +mlx5_mpls_modi_field_get(const struct rte_flow_action_modify_data *data) +{ + return MLX5_MODI_IN_MPLS_LABEL_0 + data->sub_level; +} + static void mlx5_modify_flex_item(const struct rte_eth_dev *dev, const struct mlx5_flex_item *flex, @@ -1893,6 +1900,16 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_MPLS: + MLX5_ASSERT(data->offset + width <= 32); + off_be = 32 - (data->offset + width); + info[idx] = (struct field_modify_info){4, 0, + mlx5_mpls_modi_field_get(data)}; + if (mask) + mask[idx] = flow_modify_info_mask_32(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_TAG: { MLX5_ASSERT(data->offset + width <= 32); @@ -5344,6 +5361,12 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifications of the GENEVE Network" " Identifier is not supported"); + if (action_modify_field->dst.field == RTE_FLOW_FIELD_MPLS || + action_modify_field->src.field == RTE_FLOW_FIELD_MPLS) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifications of the MPLS header " + "is not supported"); if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK || action_modify_field->src.field == RTE_FLOW_FIELD_MARK) if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 1b68a19900..80e6398992 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3546,10 +3546,8 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, const struct rte_flow_action *mask, struct rte_flow_error *error) { - const struct rte_flow_action_modify_field *action_conf = - action->conf; - const struct rte_flow_action_modify_field *mask_conf = - mask->conf; + const struct rte_flow_action_modify_field *action_conf = action->conf; + const struct rte_flow_action_modify_field *mask_conf = mask->conf; if (action_conf->operation != mask_conf->operation) return rte_flow_error_set(error, EINVAL, @@ -3604,6 +3602,11 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifying Geneve VNI is not supported"); + /* Due to HW bug, tunnel MPLS header is read only. */ + if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "MPLS cannot be used as destination"); return 0; } @@ -4134,9 +4137,8 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, action_flags |= MLX5_FLOW_ACTION_METER; break; case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: - ret = flow_hw_validate_action_modify_field(action, - mask, - error); + ret = flow_hw_validate_action_modify_field(action, mask, + error); if (ret < 0) return ret; action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;