From patchwork Wed Apr 26 19:04:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126551 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 579E942A0A; Wed, 26 Apr 2023 21:30:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB9F842D40; Wed, 26 Apr 2023 21:30:06 +0200 (CEST) Received: from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id 2ECFC410FA for ; Wed, 26 Apr 2023 21:04:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=ibRFzpID1kbihtBn46C9aQlCih5pB+x19DqYGgCn5aA=; b=s2fKHUHE48N5IbVKT0m1lqV4RJdEnr7cXSOBdtxiQgNmyOuoT2a+ZNQPcM6vwb UX4IUVH591Ll99WzexWFX7U/MuZxtwkSuHc76MYTPtn76yXEi5QV3jm6dM9L0/ ObKcAjJA2W2TT395ywFWIIcf/v967TJ3ZKiXYoE/4zNZdv4= Received: from sc9-mailhost1.vmware.com (10.113.161.71) by EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:29 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost1.vmware.com (Postfix) with ESMTP id C684B20160; Wed, 26 Apr 2023 12:04:31 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id BF4ACA83B6; Wed, 26 Apr 2023 12:04:31 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 1/7] net/vmxnet3: prepare for version 7 changes Date: Wed, 26 Apr 2023 12:04:08 -0700 Message-ID: <20230426190415.28239-2-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org vmxnet3 is currently at version 6 and this patch initiates the preparation to accommodate changes for up to version 7. Introduced utility macros for vmxnet3 version 7 comparison. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/vmxnet3_ethdev.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h index 5a303717b1..fc976707fd 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.h +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h @@ -124,6 +124,7 @@ struct vmxnet3_hw { UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES]; }; +#define VMXNET3_REV_7 6 /* Vmxnet3 Rev. 7 */ #define VMXNET3_REV_6 5 /* Vmxnet3 Rev. 6 */ #define VMXNET3_REV_5 4 /* Vmxnet3 Rev. 5 */ #define VMXNET3_REV_4 3 /* Vmxnet3 Rev. 4 */ @@ -131,6 +132,7 @@ struct vmxnet3_hw { #define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */ #define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */ +#define VMXNET3_VERSION_GE_7(hw) ((hw)->version >= VMXNET3_REV_7 + 1) #define VMXNET3_VERSION_GE_6(hw) ((hw)->version >= VMXNET3_REV_6 + 1) #define VMXNET3_VERSION_GE_5(hw) ((hw)->version >= VMXNET3_REV_5 + 1) #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1) From patchwork Wed Apr 26 19:04:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126552 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A56BD42A0A; Wed, 26 Apr 2023 21:30:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC3EE42D47; Wed, 26 Apr 2023 21:30:07 +0200 (CEST) Received: from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id 878FF4068E for ; Wed, 26 Apr 2023 21:04:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=CvRxe9Z97Y9/30fFNADzZnTY/K7BJpytFA7iYHNcTtg=; b=aJX/ZyrHbzB9lYQFeUNRuCV+/A0wtUWEUrTS7Qn5dSOSWVp065YIZjwwH2nIWE PKlJmixWLIiwuXyDZBPxjyctQGNx9ONGehA6E1iQF+ARntlAA83J2GaGLcuYU8 DyxZN0kHcsCs3NVOIjaJX5UJ89HGipWTp5KtrQ4rVlOC6XY= Received: from sc9-mailhost3.vmware.com (10.113.161.73) by EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:31 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost3.vmware.com (Postfix) with ESMTP id B689D201BC; Wed, 26 Apr 2023 12:04:33 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id ABE50A83B6; Wed, 26 Apr 2023 12:04:33 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 2/7] net/vmxnet3: add support for capability registers Date: Wed, 26 Apr 2023 12:04:09 -0700 Message-ID: <20230426190415.28239-3-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch enhances vmxnet3 to support capability registers which allows it to enable features selectively. The DCR register tracks the capabilities vmxnet3 device supports. The PTCR register states the capabilities that the passthrough device supports. With the help of these registers, vmxnet3 can enable only those features which the passthrough device supports. This allows smooth transition to Uniform-Passthrough (UPT) mode if the virtual NIC requests it. If PTCR register returns nothing or error it means UPT is not being requested and vnic will continue in emulation mode. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/base/vmxnet3_defs.h | 44 +++++++++++++++++++++--- drivers/net/vmxnet3/vmxnet3_ethdev.c | 60 +++++++++++++++++++++++++++++++++ drivers/net/vmxnet3/vmxnet3_ethdev.h | 11 ++++++ 3 files changed, 110 insertions(+), 5 deletions(-) diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h index bd6695e69d..759fdb6e4a 100644 --- a/drivers/net/vmxnet3/base/vmxnet3_defs.h +++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h @@ -26,6 +26,12 @@ #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ +#define VMXNET3_REG_DCR 0x48 /* Device capability register, + * from 0x48 to 0x80 + */ +#define VMXNET3_REG_PTCR 0x88 /* Passthru capbility register + * from 0x88 to 0xb0 + */ #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ @@ -103,11 +109,13 @@ typedef enum { VMXNET3_CMD_GET_CONF_INTR, VMXNET3_CMD_GET_ADAPTIVE_RING_INFO, VMXNET3_CMD_GET_TXDATA_DESC_SIZE, - VMXNET3_CMD_RESERVED5, - VMXNET3_CMD_RESERVED6, - VMXNET3_CMD_RESERVED7, - VMXNET3_CMD_RESERVED8, - VMXNET3_CMD_GET_MAX_QUEUES_CONF, + VMXNET3_CMD_RESERVED5, + VMXNET3_CMD_RESERVED6, + VMXNET3_CMD_RESERVED7, + VMXNET3_CMD_RESERVED8, + VMXNET3_CMD_GET_MAX_QUEUES_CONF, + VMXNET3_CMD_GET_MAX_CAPABILITIES, + VMXNET3_CMD_GET_DCR0_REG, } Vmxnet3_Cmd; /* Adaptive Ring Info Flags */ @@ -877,4 +885,30 @@ do {\ #define VMXNET3_DID_PASSTHRU 0xFFFF +#define VMXNET3_DCR_ERROR 31 /* error when bit 31 of DCR is set */ +#define VMXNET3_CAP_UDP_RSS 0 /* bit 0 of DCR 0 */ +#define VMXNET3_CAP_ESP_RSS_IPV4 1 /* bit 1 of DCR 0 */ +#define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD 2 /* bit 2 of DCR 0 */ +#define VMXNET3_CAP_GENEVE_TSO 3 /* bit 3 of DCR 0 */ +#define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD 4 /* bit 4 of DCR 0 */ +#define VMXNET3_CAP_VXLAN_TSO 5 /* bit 5 of DCR 0 */ +#define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD 6 /* bit 6 of DCR 0 */ +#define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD 7 /* bit 7 of DCR 0 */ +#define VMXNET3_CAP_PKT_STEERING_IPV4 8 /* bit 8 of DCR 0 */ +#define VMXNET3_CAP_VERSION_4_MAX VMXNET3_CAP_PKT_STEERING_IPV4 +#define VMXNET3_CAP_ESP_RSS_IPV6 9 /* bit 9 of DCR 0 */ +#define VMXNET3_CAP_VERSION_5_MAX VMXNET3_CAP_ESP_RSS_IPV6 +#define VMXNET3_CAP_ESP_OVER_UDP_RSS 10 /* bit 10 of DCR 0 */ +#define VMXNET3_CAP_INNER_RSS 11 /* bit 11 of DCR 0 */ +#define VMXNET3_CAP_INNER_ESP_RSS 12 /* bit 12 of DCR 0 */ +#define VMXNET3_CAP_CRC32_HASH_FUNC 13 /* bit 13 of DCR 0 */ +#define VMXNET3_CAP_VERSION_6_MAX VMXNET3_CAP_CRC32_HASH_FUNC +#define VMXNET3_CAP_OAM_FILTER 14 /* bit 14 of DCR 0 */ +#define VMXNET3_CAP_ESP_QS 15 /* bit 15 of DCR 0 */ +#define VMXNET3_CAP_LARGE_BAR 16 /* bit 16 of DCR 0 */ +#define VMXNET3_CAP_OOORX_COMP 17 /* bit 17 of DCR 0 */ +#define VMXNET3_CAP_VERSION_7_MAX 18 +/* when new capability is introduced, update VMXNET3_CAP_MAX */ +#define VMXNET3_CAP_MAX VMXNET3_CAP_VERSION_7_MAX + #endif /* _VMXNET3_DEFS_H_ */ diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c index fd946dec5c..05b6d54cb9 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.c +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c @@ -299,6 +299,61 @@ eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw) sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size; } +static int +eth_vmxnet3_setup_capabilities(struct vmxnet3_hw *hw, + struct rte_eth_dev *eth_dev) +{ + uint32_t dcr, ptcr, value; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, + VMXNET3_CMD_GET_MAX_CAPABILITIES); + value = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); + hw->max_capabilities[0] = value; + dcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_DCR); + hw->DCR_capabilities[0] = dcr; + hw->used_DCR_capabilities[0] = 0; + ptcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_PTCR); + hw->PTCR_capabilities[0] = ptcr; + hw->used_PTCR_capabilities[0] = 0; + + if (hw->uptv2_enabled && !(ptcr & (1 << VMXNET3_DCR_ERROR))) { + PMD_DRV_LOG(NOTICE, "UPTv2 enabled"); + hw->used_PTCR_capabilities[0] = ptcr; + } else { + /* Use all DCR capabilities, but disable large bar */ + hw->used_DCR_capabilities[0] = dcr & + (~(1UL << VMXNET3_CAP_LARGE_BAR)); + PMD_DRV_LOG(NOTICE, "UPTv2 disabled"); + } + if (hw->DCR_capabilities[0] & (1UL << VMXNET3_CAP_OOORX_COMP) && + hw->PTCR_capabilities[0] & (1UL << VMXNET3_CAP_OOORX_COMP)) { + if (hw->uptv2_enabled) { + hw->used_PTCR_capabilities[0] |= + (1UL << VMXNET3_CAP_OOORX_COMP); + } + } + if (hw->used_PTCR_capabilities[0]) { + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DCR, + hw->used_PTCR_capabilities[0]); + } else if (hw->used_DCR_capabilities[0]) { + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DCR, + hw->used_DCR_capabilities[0]); + } + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG); + dcr = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD); + hw->used_DCR_capabilities[0] = dcr; + PMD_DRV_LOG(DEBUG, "Dev " PCI_PRI_FMT ", vmxnet3 v%d, UPT enabled: %s, " + "DCR0=0x%08x, used DCR=0x%08x, " + "PTCR=0x%08x, used PTCR=0x%08x", + pci_dev->addr.domain, pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function, hw->version, + hw->uptv2_enabled ? "true" : "false", + hw->DCR_capabilities[0], hw->used_DCR_capabilities[0], + hw->PTCR_capabilities[0], hw->used_PTCR_capabilities[0]); + return 0; +} + /* * It returns 0 on success. */ @@ -396,6 +451,11 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) return -EIO; } + if (VMXNET3_VERSION_GE_7(hw)) { + /* start with UPTv2 enabled to avoid ESXi issues */ + hw->uptv2_enabled = TRUE; + eth_vmxnet3_setup_capabilities(hw, eth_dev); + } /* Getting MAC Address */ mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h index fc976707fd..1bbf2b4465 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.h +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h @@ -122,6 +122,17 @@ struct vmxnet3_hw { UPT1_RxStats saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES]; UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES]; UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES]; + /* device capability bit map */ + uint32_t DCR_capabilities[8]; + /* pass-through capability bit map */ + uint32_t PTCR_capabilities[8]; + /* max number of capabilities */ + uint32_t max_capabilities[8]; + /* used device capability bit map */ + uint32_t used_DCR_capabilities[8]; + /* used pass-through capability bit map */ + uint32_t used_PTCR_capabilities[8]; + bool uptv2_enabled; }; #define VMXNET3_REV_7 6 /* Vmxnet3 Rev. 7 */ From patchwork Wed Apr 26 19:04:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126553 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 924D642A0A; Wed, 26 Apr 2023 21:30:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6A3F42D4D; Wed, 26 Apr 2023 21:30:08 +0200 (CEST) Received: from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id E0D34410FA for ; Wed, 26 Apr 2023 21:04:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=vVJlv6iyzPMACZLN4o5vnYkEXm6O4IkqMiNt3DRvQXo=; b=mEVpj/rQX+LNV7lOghFWyPjlVprd4MrTDilx2JaFY6rIPLSZF5GC5+ZUzDIyLU U1vNYGfRyda0AXUnb3BPayLYIJCPOsx+lCKpqZxMrJzaIQF//bwhTjUCbQ9byt DEQ/KrJjjAo7zf7fXMu/0zC1ropvg6xtj/vo69TcEeo7QJI= Received: from sc9-mailhost3.vmware.com (10.113.161.73) by EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:31 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost3.vmware.com (Postfix) with ESMTP id D81B9201BC; Wed, 26 Apr 2023 12:04:33 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id D0563A83B6; Wed, 26 Apr 2023 12:04:33 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 3/7] net/vmxnet3: add support for large passthrough BAR register Date: Wed, 26 Apr 2023 12:04:10 -0700 Message-ID: <20230426190415.28239-4-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For vmxnet3 to work in UPT mode, the BAR sizes have been increased. The PT page has been extended to 2 pages and also includes OOB pages as a part of PT BAR. This patch enhances vmxnet3 to use appropriate BAR offsets based on the capability registered. To use new offsets, VMXNET3_CAP_LARGE_BAR needs to be set by the device. If it is not set then the device will use legacy PT page layout. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/base/vmxnet3_defs.h | 13 +++++++++++-- drivers/net/vmxnet3/vmxnet3_ethdev.c | 11 +++++++++++ drivers/net/vmxnet3/vmxnet3_ethdev.h | 2 ++ drivers/net/vmxnet3/vmxnet3_rxtx.c | 13 +++++++------ 4 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h index 759fdb6e4a..27f35a0062 100644 --- a/drivers/net/vmxnet3/base/vmxnet3_defs.h +++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h @@ -43,8 +43,16 @@ #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ -#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ -#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ +/* For Large PT BAR, the following offset to DB register */ +#define VMXNET3_REG_LB_TXPROD 0x1000 /* Tx Producer Index */ +#define VMXNET3_REG_LB_RXPROD 0x1400 /* Rx Producer Index for ring 1 */ +#define VMXNET3_REG_LB_RXPROD2 0x1800 /* Rx Producer Index for ring 2 */ + +#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ +#define VMXNET3_LARGE_PT_REG_SIZE 8192 /* large PT pages */ +#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ +#define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096) /* LARGE BAR 0 */ +#define VMXNET3_OOB_REG_SIZE (4094 * 4096) /* OOB pages */ /* * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at @@ -56,6 +64,7 @@ * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" */ #define VMXNET3_PHYSMEM_PAGES 4 +#define VMXNET3_PHYSMEM_LB_PAGES 4099 /* 4096 + 1 + 2 */ #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ #define VMXNET3_REG_ALIGN_MASK 0x7 diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c index 05b6d54cb9..62c7e048f5 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.c +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c @@ -456,6 +456,17 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) hw->uptv2_enabled = TRUE; eth_vmxnet3_setup_capabilities(hw, eth_dev); } + + if (hw->used_DCR_capabilities[0] & (1 << VMXNET3_CAP_LARGE_BAR)) { + hw->tx_prod_offset = VMXNET3_REG_LB_TXPROD; + hw->rx_prod_offset[0] = VMXNET3_REG_LB_RXPROD; + hw->rx_prod_offset[1] = VMXNET3_REG_LB_RXPROD2; + } else { + hw->tx_prod_offset = VMXNET3_REG_TXPROD; + hw->rx_prod_offset[0] = VMXNET3_REG_RXPROD; + hw->rx_prod_offset[1] = VMXNET3_REG_RXPROD2; + } + /* Getting MAC Address */ mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL); mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH); diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h index 1bbf2b4465..cabd83e7e1 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.h +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h @@ -122,6 +122,8 @@ struct vmxnet3_hw { UPT1_RxStats saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES]; UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES]; UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES]; + uint16_t tx_prod_offset; + uint16_t rx_prod_offset[2]; /* device capability bit map */ uint32_t DCR_capabilities[8]; /* pass-through capability bit map */ diff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c index a875ffec07..83daac02c4 100644 --- a/drivers/net/vmxnet3/vmxnet3_rxtx.c +++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c @@ -57,8 +57,6 @@ #define VMXNET3_TX_OFFLOAD_NOTSUP_MASK \ (RTE_MBUF_F_TX_OFFLOAD_MASK ^ VMXNET3_TX_OFFLOAD_MASK) -static const uint32_t rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2}; - static int vmxnet3_post_rx_bufs(vmxnet3_rx_queue_t*, uint8_t); static void vmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *); #ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED @@ -577,7 +575,7 @@ vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, if (deferred >= rte_le_to_cpu_32(txq_ctrl->txThreshold)) { txq_ctrl->txNumDeferred = 0; /* Notify vSwitch that packets are available. */ - VMXNET3_WRITE_BAR0_REG(hw, (VMXNET3_REG_TXPROD + txq->queue_id * VMXNET3_REG_ALIGN), + VMXNET3_WRITE_BAR0_REG(hw, (hw->tx_prod_offset + txq->queue_id * VMXNET3_REG_ALIGN), txq->cmd_ring.next2fill); } @@ -1000,7 +998,8 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) /* It's time to renew descriptors */ vmxnet3_renew_desc(rxq, ring_idx, newm); if (unlikely(rxq->shared->ctrl.updateRxProd)) { - VMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN), + VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] + + (rxq->queue_id * VMXNET3_REG_ALIGN), rxq->cmd_ring[ring_idx].next2fill); } @@ -1027,7 +1026,8 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) } if (unlikely(rxq->shared->ctrl.updateRxProd)) { for (ring_idx = 0; ring_idx < VMXNET3_RX_CMDRING_SIZE; ring_idx++) { - VMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN), + VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] + + (rxq->queue_id * VMXNET3_REG_ALIGN), rxq->cmd_ring[ring_idx].next2fill); } } @@ -1322,7 +1322,8 @@ vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev) * mbufs for coming packets. */ if (unlikely(rxq->shared->ctrl.updateRxProd)) { - VMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[j] + (rxq->queue_id * VMXNET3_REG_ALIGN), + VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[j] + + (rxq->queue_id * VMXNET3_REG_ALIGN), rxq->cmd_ring[j].next2fill); } } From patchwork Wed Apr 26 19:04:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126556 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCAB042A0A; Wed, 26 Apr 2023 21:30:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC00E42D5D; Wed, 26 Apr 2023 21:30:11 +0200 (CEST) Received: from EX-PRD-EDGE02.vmware.com (ex-prd-edge02.vmware.com [208.91.3.34]) by mails.dpdk.org (Postfix) with ESMTP id C013C42D37 for ; Wed, 26 Apr 2023 21:04:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=Y+SEs8Qr/AcI2mLvFCCNM3gRxzfrWaPuZQY6XwiRALM=; b=POuHP8fr8XaSnXO6v2eftFBOw9Zvj/r6nPH9TnhrhlV6DZuWsbzl9z3sa0Lk58 Ogj29p0lLF2/f9FDeZhW78x26GimN/hAAPsCddFKdN5kb9O+PR8onCNU9ru7Bo OrunnVmBkuj2HbOmGJ5iStth71qtHt5RFgnqoAGuvNKNd0g= Received: from sc9-mailhost1.vmware.com (10.113.161.71) by EX-PRD-EDGE02.vmware.com (10.188.245.7) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:32 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost1.vmware.com (Postfix) with ESMTP id 041C220160; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id EE149A83B6; Wed, 26 Apr 2023 12:04:33 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 4/7] net/vmxnet3: add command to set ring buffer sizes Date: Wed, 26 Apr 2023 12:04:11 -0700 Message-ID: <20230426190415.28239-5-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE02.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a new command to set ring buffer sizes. This is required to pass the buffer size information to passthrough devices. Also, ring sizes are round down to power of 2. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/base/vmxnet3_defs.h | 15 +++++++++++++++ drivers/net/vmxnet3/vmxnet3_ethdev.c | 18 ++++++++++++++++++ drivers/net/vmxnet3/vmxnet3_ethdev.h | 1 + drivers/net/vmxnet3/vmxnet3_rxtx.c | 7 +++++++ 4 files changed, 41 insertions(+) diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h index 27f35a0062..d8cc295b08 100644 --- a/drivers/net/vmxnet3/base/vmxnet3_defs.h +++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h @@ -105,6 +105,9 @@ typedef enum { VMXNET3_CMD_RESERVED4, VMXNET3_CMD_REGISTER_MEMREGS, VMXNET3_CMD_SET_RSS_FIELDS, + VMXNET3_CMD_RESERVED9, + VMXNET3_CMD_RESERVED10, + VMXNET3_CMD_SET_RING_BUFFER_SIZE, VMXNET3_CMD_FIRST_GET = 0xF00D0000, VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, @@ -822,6 +825,17 @@ typedef enum Vmxnet3_RSSField { VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020, } Vmxnet3_RSSField; +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_RingBufferSize { + __le16 ring1BufSizeType0; + __le16 ring1BufSizeType1; + __le16 ring2BufSizeType1; + __le16 pad; +} +#include "vmware_pack_end.h" +Vmxnet3_RingBufferSize; + /* * If the command data <= 16 bytes, use the shared memory direcly. * Otherwise, use the variable length configuration descriptor. @@ -832,6 +846,7 @@ union Vmxnet3_CmdInfo { Vmxnet3_VariableLenConfDesc varConf; Vmxnet3_SetPolling setPolling; Vmxnet3_RSSField setRSSFields; + Vmxnet3_RingBufferSize ringBufSize; __le16 reserved[2]; __le64 data[2]; } diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c index 62c7e048f5..b9cf007429 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.c +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c @@ -1018,6 +1018,22 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) return VMXNET3_SUCCESS; } +static void +vmxnet3_init_bufsize(struct vmxnet3_hw *hw) +{ + struct Vmxnet3_DriverShared *shared = hw->shared; + union Vmxnet3_CmdInfo *cmd_info = &shared->cu.cmdInfo; + + if (!VMXNET3_VERSION_GE_7(hw)) + return; + + cmd_info->ringBufSize.ring1BufSizeType0 = hw->rxdata_buf_size; + cmd_info->ringBufSize.ring1BufSizeType1 = 0; + cmd_info->ringBufSize.ring2BufSizeType1 = hw->rxdata_buf_size; + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, + VMXNET3_CMD_SET_RING_BUFFER_SIZE); +} + /* * Configure device link speed and setup link. * Must be called after eth_vmxnet3_dev_init. Other wise it might fail @@ -1101,6 +1117,8 @@ vmxnet3_dev_start(struct rte_eth_dev *dev) return ret; } + vmxnet3_init_bufsize(hw); + hw->adapter_stopped = FALSE; /* Setting proper Rx Mode and issue Rx Mode Update command */ diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h index cabd83e7e1..2b3e2c4caa 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.h +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h @@ -96,6 +96,7 @@ struct vmxnet3_hw { uint16_t txdata_desc_size; /* tx data ring buffer size */ uint16_t rxdata_desc_size; /* rx data ring buffer size */ + uint16_t rxdata_buf_size; /* rx data buffer size */ uint8_t num_intrs; diff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c index 83daac02c4..e31878ecab 100644 --- a/drivers/net/vmxnet3/vmxnet3_rxtx.c +++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c @@ -1113,6 +1113,8 @@ vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } else { ring->size = nb_desc; + if (VMXNET3_VERSION_GE_7(hw)) + ring->size = rte_align32prevpow2(nb_desc); ring->size &= ~VMXNET3_RING_SIZE_MASK; } comp_ring->size = data_ring->size = ring->size; @@ -1193,6 +1195,9 @@ vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, } rxq->mp = mp; + /* Remember buffer size for initialization in dev start. */ + hw->rxdata_buf_size = + rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; rxq->queue_id = queue_idx; rxq->port_id = dev->data->port_id; rxq->shared = NULL; /* set in vmxnet3_setup_driver_shared() */ @@ -1217,6 +1222,8 @@ vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } else { ring0->size = nb_desc; + if (VMXNET3_VERSION_GE_7(hw)) + ring0->size = rte_align32prevpow2(nb_desc); ring0->size &= ~VMXNET3_RING_SIZE_MASK; ring1->size = ring0->size; } From patchwork Wed Apr 26 19:04:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126554 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50C1742A0A; Wed, 26 Apr 2023 21:30:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D5B6342D52; Wed, 26 Apr 2023 21:30:09 +0200 (CEST) Received: from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id 45D284068E for ; Wed, 26 Apr 2023 21:04:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=am+89PS/HJGdtII8YmqMh6hZAID3jtRz4wlveSWbYJU=; b=NKr3Apvkot/vQN18BgwZylVvIMwmvcAE3cm6w4Br/PL2iVRGMPrMwVxwJbBEsH x8EULjK5MW47RQ1LOhyCeKF7sn5Dxujn9KCvQLmHLZFVdSE7loAGczMzv+VMon OMAlYixp20cHtnxa+7wvpDgbE6b7fAKa6X/mwV8jO6GMhzk= Received: from sc9-mailhost1.vmware.com (10.113.161.71) by EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:31 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost1.vmware.com (Postfix) with ESMTP id 3139320160; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id 14647A83B8; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 5/7] net/vmxnet3: limit number of TXDs used for TSO packet Date: Wed, 26 Apr 2023 12:04:12 -0700 Message-ID: <20230426190415.28239-6-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, vmxnet3 does not have a limit on number of descriptors used for a TSO packet. However, with UPT, for hardware performance reasons, this patch limits the number of transmit descriptors to 24 for a TSO packet. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/base/vmxnet3_defs.h | 2 ++ drivers/net/vmxnet3/vmxnet3_rxtx.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h index d8cc295b08..24c235876e 100644 --- a/drivers/net/vmxnet3/base/vmxnet3_defs.h +++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h @@ -419,6 +419,8 @@ typedef union Vmxnet3_GenericDesc { /* max # of tx descs for a non-tso pkt */ #define VMXNET3_MAX_TXD_PER_PKT 16 +/* max # of tx descs for a tso pkt */ +#define VMXNET3_MAX_TSO_TXD_PER_PKT 24 /* Max size of a single rx buffer */ #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) diff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c index e31878ecab..7bbae4177e 100644 --- a/drivers/net/vmxnet3/vmxnet3_rxtx.c +++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c @@ -364,6 +364,14 @@ vmxnet3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, rte_errno = EINVAL; return i; } + /* TSO packet cannot occupy more than + * VMXNET3_MAX_TSO_TXD_PER_PKT TX descriptors. + */ + if ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) != 0 && + m->nb_segs > VMXNET3_MAX_TSO_TXD_PER_PKT) { + rte_errno = EINVAL; + return i; + } /* check that only supported TX offloads are requested. */ if ((ol_flags & VMXNET3_TX_OFFLOAD_NOTSUP_MASK) != 0 || @@ -444,10 +452,12 @@ vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, continue; } - /* Drop non-TSO packet that is excessively fragmented */ - if (unlikely(!tso && count > VMXNET3_MAX_TXD_PER_PKT)) { - PMD_TX_LOG(ERR, "Non-TSO packet cannot occupy more than %d tx " - "descriptors. Packet dropped.", VMXNET3_MAX_TXD_PER_PKT); + /* Drop non-TSO or TSO packet that is excessively fragmented */ + if (unlikely((!tso && count > VMXNET3_MAX_TXD_PER_PKT) || + (tso && count > VMXNET3_MAX_TSO_TXD_PER_PKT))) { + PMD_TX_LOG(ERR, "Non-TSO or TSO packet cannot occupy more than " + "%d or %d tx descriptors respectively. Packet dropped.", + VMXNET3_MAX_TXD_PER_PKT, VMXNET3_MAX_TSO_TXD_PER_PKT); txq->stats.drop_too_many_segs++; txq->stats.drop_total++; rte_pktmbuf_free(txm); From patchwork Wed Apr 26 19:04:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126555 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4853E42A0A; Wed, 26 Apr 2023 21:30:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D47A142D33; Wed, 26 Apr 2023 21:30:10 +0200 (CEST) Received: from EX-PRD-EDGE01.vmware.com (EX-PRD-EDGE01.vmware.com [208.91.3.33]) by mails.dpdk.org (Postfix) with ESMTP id 9E8FA42D17 for ; Wed, 26 Apr 2023 21:04:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=7Qp9gpCa7+IRbcrytySuRMSJQVWMKDOipHc3Nx3mocs=; b=wWAegXcm5dwSbqFAoH2XHbhmv139tL3D6gGeEqJfs2veOSG5emj4HHjAgtZC3L w0h1p9lNPhrq0H0uVjLr44XNGiCES0+0ot/q7xAv3uVOKH8HsgnMER8yhfQDKh M9M6a4Q1NfrodbmnYQyj2uwAZJ2BMn52iwTwed0jM7ifk/Y= Received: from sc9-mailhost2.vmware.com (10.113.161.72) by EX-PRD-EDGE01.vmware.com (10.188.245.6) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:31 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost2.vmware.com (Postfix) with ESMTP id 446CF201EF; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id 31CE8A83B6; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 6/7] net/vmxnet3: avoid updating rxprod register frequently Date: Wed, 26 Apr 2023 12:04:13 -0700 Message-ID: <20230426190415.28239-7-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE01.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When UPT is enabled, the driver updates rxprod register to let the device know that it has processed the received packets and new buffers are available. However, updating it too frequently can lead to reduced performance. This patch adds code to avoid updating the register frequently. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- drivers/net/vmxnet3/vmxnet3_rxtx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c index 7bbae4177e..39ad0726cb 100644 --- a/drivers/net/vmxnet3/vmxnet3_rxtx.c +++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c @@ -1007,7 +1007,8 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) /* It's time to renew descriptors */ vmxnet3_renew_desc(rxq, ring_idx, newm); - if (unlikely(rxq->shared->ctrl.updateRxProd)) { + if (unlikely(rxq->shared->ctrl.updateRxProd && + (rxq->cmd_ring[ring_idx].next2fill & 0xf) == 0)) { VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN), rxq->cmd_ring[ring_idx].next2fill); @@ -1027,18 +1028,21 @@ vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) if (unlikely(nb_rxd == 0)) { uint32_t avail; + uint32_t posted = 0; for (ring_idx = 0; ring_idx < VMXNET3_RX_CMDRING_SIZE; ring_idx++) { avail = vmxnet3_cmd_ring_desc_avail(&rxq->cmd_ring[ring_idx]); if (unlikely(avail > 0)) { /* try to alloc new buf and renew descriptors */ - vmxnet3_post_rx_bufs(rxq, ring_idx); + if (vmxnet3_post_rx_bufs(rxq, ring_idx) > 0) + posted |= (1 << ring_idx); } } if (unlikely(rxq->shared->ctrl.updateRxProd)) { for (ring_idx = 0; ring_idx < VMXNET3_RX_CMDRING_SIZE; ring_idx++) { - VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] + - (rxq->queue_id * VMXNET3_REG_ALIGN), - rxq->cmd_ring[ring_idx].next2fill); + if (posted & (1 << ring_idx)) + VMXNET3_WRITE_BAR0_REG(hw, hw->rx_prod_offset[ring_idx] + + (rxq->queue_id * VMXNET3_REG_ALIGN), + rxq->cmd_ring[ring_idx].next2fill); } } } From patchwork Wed Apr 26 19:04:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronak Doshi X-Patchwork-Id: 126557 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3F5B42A0A; Wed, 26 Apr 2023 21:31:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF64242D61; Wed, 26 Apr 2023 21:30:12 +0200 (CEST) Received: from EX-PRD-EDGE02.vmware.com (ex-prd-edge02.vmware.com [208.91.3.34]) by mails.dpdk.org (Postfix) with ESMTP id 256E442D39 for ; Wed, 26 Apr 2023 21:04:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; s=s1024; d=vmware.com; h=from:to:cc:subject:date:message-id:in-reply-to:mime-version: content-type; bh=DJ0feCiE+01MRRgeJhRQJEMgoG2diKpwlzkf8yrSCIQ=; b=H7WIy5Zwen1EVFmc/lm5lfsy784EzJ3RYSK9srzyHVEVZl1BdmFtVwWIGJhD0J MqXI7z9VTr1igzDcHkKRd2FqPsV2E6LL5+PSMD9saTp6pB8D0y/3CN/j6QPKrF XjYrdRNEj40oey6zq4slFuJyNgzKUrCu+71OIuOo6iQUmmg= Received: from sc9-mailhost2.vmware.com (10.113.161.72) by EX-PRD-EDGE02.vmware.com (10.188.245.7) with Microsoft SMTP Server id 15.1.2375.34; Wed, 26 Apr 2023 12:04:32 -0700 Received: from htb-1n-eng-dhcp122.eng.vmware.com (unknown [10.20.114.216]) by sc9-mailhost2.vmware.com (Postfix) with ESMTP id 5F0C5202A6; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) Received: by htb-1n-eng-dhcp122.eng.vmware.com (Postfix, from userid 0) id 5A1BBA83B6; Wed, 26 Apr 2023 12:04:34 -0700 (PDT) From: Ronak Doshi To: Jochen Behrens CC: , Ronak Doshi Subject: [PATCH v2 next 7/7] net/vmxnet3: update to version 7 Date: Wed, 26 Apr 2023 12:04:14 -0700 Message-ID: <20230426190415.28239-8-doshir@vmware.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20230426190415.28239-1-doshir@vmware.com> References: <20230426190415.28239-1-doshir@vmware.com> MIME-Version: 1.0 Received-SPF: None (EX-PRD-EDGE02.vmware.com: doshir@vmware.com does not designate permitted sender hosts) X-Mailman-Approved-At: Wed, 26 Apr 2023 21:30:01 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org With all vmxnet3 version 7 changes incorporated in the vmxnet3 driver, the driver can configure emulation to run at vmxnet3 version 7, provided the emulation advertises support for version 7. Signed-off-by: Ronak Doshi Acked-by: Jochen Behrens --- doc/guides/nics/vmxnet3.rst | 26 ++++++++++++++++++++++++++ doc/guides/rel_notes/release_23_07.rst | 6 ++++++ drivers/net/vmxnet3/vmxnet3_ethdev.c | 6 +++++- drivers/net/vmxnet3/vmxnet3_ring.h | 2 +- 4 files changed, 38 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/vmxnet3.rst b/doc/guides/nics/vmxnet3.rst index 190cf91a47..d96e296530 100644 --- a/doc/guides/nics/vmxnet3.rst +++ b/doc/guides/nics/vmxnet3.rst @@ -67,6 +67,32 @@ There are several options available for filtering packets at VMXNET3 device leve * VLAN tag based filtering without load balancing - SUPPORTED +#. Vmxnet3 versions and associated features. + + Vmxnet3 version is tied to corresponding ESXi hardware version and each + version defines a set of compatible features. + + * Vmxnet3 version 7, hw ver 19 + This version adds support for Uniform Passthrough(UPT). + + * Vmxnet3 version 6, hw ver 17 + This version enhanced vmxnet3 to support queues up to 32 and also + removed power-of-two limitations on the queues. + + * Vmxnet3 version 5, hw ver 15 + Features not related to dpdk vmxnet3 PMD. + + * Vmxnet3 version 4, hw ver 14 + This version adds supoprt for UDP and ESP RSS + + * Vmxnet3 version 3, hw ver 13 + This version added performance enhancement features such as + configurable Tx data ring, Receive Data Ring, and the ability + to register memory regions. + + * Vmxnet3 version 2, hw ver 11 + This version adds support for Large Receive offload (LRO). + .. note:: diff --git a/doc/guides/rel_notes/release_23_07.rst b/doc/guides/rel_notes/release_23_07.rst index a9b1293689..907a06cd62 100644 --- a/doc/guides/rel_notes/release_23_07.rst +++ b/doc/guides/rel_notes/release_23_07.rst @@ -55,6 +55,12 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= + * **Added vmxnet3 version 7 support.** + + Added support for vmxnet3 version 7 which includes support + for uniform passthrough(UPT). The patches also add support + for new capability registers, large passthru BAR and some + performance enhancements for UPT. Removed Items ------------- diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c index b9cf007429..41073e9798 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.c +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c @@ -410,7 +410,11 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) /* Check h/w version compatibility with driver. */ ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS); - if (ver & (1 << VMXNET3_REV_6)) { + if (ver & (1 << VMXNET3_REV_7)) { + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, + 1 << VMXNET3_REV_7); + hw->version = VMXNET3_REV_7 + 1; + } else if (ver & (1 << VMXNET3_REV_6)) { VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1 << VMXNET3_REV_6); hw->version = VMXNET3_REV_6 + 1; diff --git a/drivers/net/vmxnet3/vmxnet3_ring.h b/drivers/net/vmxnet3/vmxnet3_ring.h index 50992349d8..948762db90 100644 --- a/drivers/net/vmxnet3/vmxnet3_ring.h +++ b/drivers/net/vmxnet3/vmxnet3_ring.h @@ -7,7 +7,7 @@ #define VMXNET3_RX_CMDRING_SIZE 2 -#define VMXNET3_DRIVER_VERSION_NUM 0x01012000 +#define VMXNET3_DRIVER_VERSION_NUM 0x01013000 /* Default ring size */ #define VMXNET3_DEF_TX_RING_SIZE 512