From patchwork Mon Apr 24 09:17:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126449 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6771429D9; Mon, 24 Apr 2023 11:22:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B39E942D0B; Mon, 24 Apr 2023 11:22:54 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id DB3A6427EE; Mon, 24 Apr 2023 11:22:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328173; x=1713864173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Uif3yWVIQgIh0D3fKJZLNA/CaIcwxrfGucqrP3RvUEg=; b=L+AM1zIgDwiO6wwMtTcIbWJyGPfuh/DWtSKGN5M0V+NbESdOwpZdgAEe 8osTWHmK/KD8ZFaG0aJHtWJQQejMFXRWerAnJPRAkJ2kpBSgeplJqVaoU CkREDhBvGg4HCTv90dw893PUox6kXHL14q/HVgV1crXauT0qoTLnB01Yk Niiv29F0U1Eod3NoTULugFqbrQLkYSj6kXpzZ05Cd6iUe+jcpCKLNWNk7 v3mpAb3OsVlLlNShBAuu8DQgEh9u7W7tX526v1Xyb0CYd+Wzthnk7UWOe pxN+foubO70+bIqrcI0CpcxUpigCeP/d9BktvojzqB1uY7ACINDVWX3w8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680016" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680016" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:22:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836894973" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836894973" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:50 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 1/7] common/idpf: fix 64b timestamp roll over issue Date: Mon, 24 Apr 2023 05:17:01 -0400 Message-Id: <20230424091707.488045-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reading MTS register at first packet will cause timestamp roll over issue. To support calculating 64b timestamp, need an alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/common/idpf/idpf_common_rxtx.c | 108 ++++++++++++------------- drivers/common/idpf/idpf_common_rxtx.h | 3 +- drivers/common/idpf/version.map | 1 + 3 files changed, 55 insertions(+), 57 deletions(-) diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index fc87e3e243..19bcb94077 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -4,6 +4,7 @@ #include #include +#include #include "idpf_common_rxtx.h" @@ -442,56 +443,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq) return 0; } -#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000 /* Helper function to convert a 32b nanoseconds timestamp to 64b. */ static inline uint64_t -idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag, - uint32_t in_timestamp) +idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp) { -#ifdef RTE_ARCH_X86_64 - struct idpf_hw *hw = &ad->hw; const uint64_t mask = 0xFFFFFFFF; - uint32_t hi, lo, lo2, delta; + const uint32_t half_overflow_duration = 0x1 << 31; + uint32_t delta; uint64_t ns; - if (flag != 0) { - IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); - IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | - PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); - lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); - /* - * On typical system, the delta between lo and lo2 is ~1000ns, - * so 10000 seems a large-enough but not overly-big guard band. - */ - if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) - lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - else - lo2 = lo; - - if (lo2 < lo) { - lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); - hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); - } - - ad->time_hw = ((uint64_t)hi << 32) | lo; - } - - delta = (in_timestamp - (uint32_t)(ad->time_hw & mask)); - if (delta > (mask / 2)) { - delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp); - ns = ad->time_hw - delta; + delta = (in_timestamp - (uint32_t)(time_hw & mask)); + if (delta > half_overflow_duration) { + delta = ((uint32_t)(time_hw & mask) - in_timestamp); + ns = time_hw - delta; } else { - ns = ad->time_hw + delta; + ns = time_hw + delta; } - return ns; -#else /* !RTE_ARCH_X86_64 */ - RTE_SET_USED(ad); - RTE_SET_USED(flag); - RTE_SET_USED(in_timestamp); - return 0; -#endif /* RTE_ARCH_X86_64 */ } #define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \ @@ -659,9 +627,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_desc_ring = rxq->rx_ring; ptype_tbl = rxq->adapter->ptype_tbl; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) - rxq->hw_register_set = 1; - while (nb_rx < nb_pkts) { rx_desc = &rx_desc_ring[rx_id]; @@ -720,10 +685,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rx_desc->ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; @@ -1077,9 +1040,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, rx_ring = rxq->rx_ring; ptype_tbl = rxq->adapter->ptype_tbl; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) - rxq->hw_register_set = 1; - while (nb_rx < nb_pkts) { rxdp = &rx_ring[rx_id]; rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0); @@ -1142,10 +1102,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; @@ -1272,10 +1230,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, if (idpf_timestamp_dynflag > 0 && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { /* timestamp */ - ts_ns = idpf_tstamp_convert_32b_64b(ad, - rxq->hw_register_set, + ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw, rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high)); - rxq->hw_register_set = 0; *RTE_MBUF_DYNFIELD(rxm, idpf_timestamp_dynfield_offset, rte_mbuf_timestamp_t *) = ts_ns; @@ -1621,3 +1577,43 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq) rxq->bufq2->ops = &def_rx_ops_vec; return idpf_rxq_vec_setup_default(rxq->bufq2); } + +#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000 +void +idpf_dev_read_time_hw(void *cb_arg) +{ +#ifdef RTE_ARCH_X86_64 + struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg; + uint32_t hi, lo, lo2; + int rc = 0; + struct idpf_hw *hw = &ad->hw; + + IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); + IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, + PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); + lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); + /* + * On typical system, the delta between lo and lo2 is ~1000ns, + * so 10000 seems a large-enough but not overly-big guard band. + */ + if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) + lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + else + lo2 = lo; + + if (lo2 < lo) { + lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0); + hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0); + } + + ad->time_hw = ((uint64_t)hi << 32) | lo; +#else /* !RTE_ARCH_X86_64 */ + ad->time_hw = 0; +#endif /* RTE_ARCH_X86_64 */ + + /* re-alarm watchdog */ + rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg); + if (rc) + DRV_LOG(ERR, "Failed to reset device watchdog alarm"); +} diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h index 11260d07f9..af1425eb3f 100644 --- a/drivers/common/idpf/idpf_common_rxtx.h +++ b/drivers/common/idpf/idpf_common_rxtx.h @@ -142,7 +142,6 @@ struct idpf_rx_queue { struct idpf_rx_queue *bufq2; uint64_t offloads; - uint32_t hw_register_set; }; struct idpf_tx_entry { @@ -300,4 +299,6 @@ __rte_internal uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); +__rte_internal +void idpf_dev_read_time_hw(void *cb_arg); #endif /* _IDPF_COMMON_RXTX_H_ */ diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map index 70334a1b03..c67c554911 100644 --- a/drivers/common/idpf/version.map +++ b/drivers/common/idpf/version.map @@ -14,6 +14,7 @@ INTERNAL { idpf_dp_splitq_recv_pkts_avx512; idpf_dp_splitq_xmit_pkts; idpf_dp_splitq_xmit_pkts_avx512; + idpf_dev_read_time_hw; idpf_qc_rx_thresh_check; idpf_qc_rx_queue_release; From patchwork Mon Apr 24 09:17:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126450 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25EA9429D9; Mon, 24 Apr 2023 11:23:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE01542D17; Mon, 24 Apr 2023 11:22:56 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id D789142D0E; Mon, 24 Apr 2023 11:22:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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24 Apr 2023 02:22:52 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 2/7] net/idpf: save main time by alarm Date: Mon, 24 Apr 2023 05:17:02 -0400 Message-Id: <20230424091707.488045-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/net/idpf/idpf_ethdev.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c index e02ec2ec5a..3f33ffbc78 100644 --- a/drivers/net/idpf/idpf_ethdev.c +++ b/drivers/net/idpf/idpf_ethdev.c @@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev) goto err_vec; } + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + rte_eal_alarm_set(1000 * 1000, + &idpf_dev_read_time_hw, + (void *)base); + } + ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); @@ -810,6 +816,7 @@ static int idpf_dev_stop(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *base = vport->adapter; if (vport->stopped == 1) return 0; @@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev) idpf_vc_vectors_dealloc(vport); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + rte_eal_alarm_cancel(idpf_dev_read_time_hw, + base); + } + vport->stopped = 1; return 0; From patchwork Mon Apr 24 09:17:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126451 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52A54429D9; Mon, 24 Apr 2023 11:23:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3FE8842D2F; Mon, 24 Apr 2023 11:22:59 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C497C42BC9; Mon, 24 Apr 2023 11:22:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328178; x=1713864178; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rBoMztJv/D4KvLyyT7WKZiNEYfaBJ6rb4N+pYsGSiSE=; b=H144kqTqFV3YwO/CEUGBAtsH7qf34E5uqbGXPfqSHA614Z8U0K+0LvkR cTI8uJxfzzgdESEt552PHEEncxDjsRiwfjSqtMWzaOZ9jqoMQftPer8+h TbtqYFdh93CDWMio/dMNvWvj+QpMkCMUJW1xnm9KwleDx0aVrOgPUgReC pDLsN8Su5Ge9wWkjpwl01asIVWp3J+94Y6lQmQPDjaYf6rn23hr53ETMn zc63/CCrfNLtmIBmdw/Q/Ja7g43cBFfUO/JP0RHbgBdRAxOmN4A0RwewE ZIgJIePEfQzKmbQbUN/+GGjGU/70rZUKMvrR93lmCELM8gBtYO98lJLH8 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680061" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680061" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:22:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895063" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895063" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:54 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 3/7] net/cpfl: save main time by alarm Date: Mon, 24 Apr 2023 05:17:03 -0400 Message-Id: <20230424091707.488045-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using alarm to save main time from registers every 1 second. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- drivers/net/cpfl/cpfl_ethdev.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index ede730fd50..82d8147494 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -767,6 +767,12 @@ cpfl_dev_start(struct rte_eth_dev *dev) goto err_vec; } + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + rte_eal_alarm_set(1000 * 1000, + &idpf_dev_read_time_hw, + (void *)base); + } + ret = idpf_vc_vectors_alloc(vport, req_vecs_num); if (ret != 0) { PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors"); @@ -816,6 +822,7 @@ static int cpfl_dev_stop(struct rte_eth_dev *dev) { struct idpf_vport *vport = dev->data->dev_private; + struct idpf_adapter *base = vport->adapter; if (vport->stopped == 1) return 0; @@ -828,6 +835,11 @@ cpfl_dev_stop(struct rte_eth_dev *dev) idpf_vc_vectors_dealloc(vport); + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + rte_eal_alarm_cancel(idpf_dev_read_time_hw, + base); + } + vport->stopped = 1; return 0; From patchwork Mon Apr 24 09:17:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126452 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB500429D9; Mon, 24 Apr 2023 11:23:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4448742C76; Mon, 24 Apr 2023 11:23:01 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C89CC42D31; Mon, 24 Apr 2023 11:22:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328180; x=1713864180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D1xeMQBK3/UBoW/17IB/HQbbUD/ywjtGem9EljSzqaU=; b=E86t9ueB+4fMuN/nAl+ThlhqZXO/e87vicUx9C2O7i7U4HcnCHFAWzwh MOVYRXAg+zFJhL+B2dkbWrBZk6jmDLCvYX01xZKfzbzTgx2/qqD6cl2sI cNGF024fdGdHXHO+h48rHl2gOFboUCJoDThl0LZmQRKILnxqWcMVdiB7d Eaa0GSaP2icIPuSk9hk8e8U7ciGeZHfj/n4zjxBNFiDGEAjoxG2VAbNJB C465BPZy7m3sWCepqJ6mWFdoJ8vYfS4DgCeFbsJjBdKYqL/GUiRU/XZ7b dwPfsIuw6hD1v0a8CpFr+nmXBHdMVz6mfebunwOF019Ghog2K6+8DTwL5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680065" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680065" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:22:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895091" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895091" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:57 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC Date: Mon, 24 Apr 2023 05:17:04 -0400 Message-Id: <20230424091707.488045-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For ACC, getting main time from MTS registers by shared memory. Notice: it is a workaround, and it will be removed after generic solution are provided. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- config/meson.build | 3 ++ drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++ drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++--- meson_options.txt | 2 ++ 4 files changed, 79 insertions(+), 4 deletions(-) diff --git a/config/meson.build b/config/meson.build index fa730a1b14..8d74f301b4 100644 --- a/config/meson.build +++ b/config/meson.build @@ -316,6 +316,9 @@ endif if get_option('mbuf_refcnt_atomic') dpdk_conf.set('RTE_MBUF_REFCNT_ATOMIC', true) endif +if get_option('enable_acc_timestamp') + dpdk_conf.set('IDPF_ACC_TIMESTAMP', true) +endif dpdk_conf.set10('RTE_IOVA_IN_MBUF', get_option('enable_iova_as_pa')) compile_time_cpuflags = [] diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 99ae9cf60a..e634939a51 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -24,6 +24,13 @@ #include #include +#ifdef IDPF_ACC_TIMESTAMP +#include +#include +#include +#include +#endif /* IDPF_ACC_TIMESTAMP */ + #define INLINE inline #define STATIC static @@ -361,4 +368,45 @@ idpf_hweight32(u32 num) #endif +#ifdef IDPF_ACC_TIMESTAMP +#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000 +#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C) +#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10) + +inline uint32_t +idpf_mmap_r32(uint64_t pa) +{ + int fd; + void *bp, *vp; + uint32_t rval = 0xdeadbeef; + uint32_t ps, ml, of; + + fd = open("/dev/mem", (O_RDWR | O_SYNC)); + if (fd == -1) { + perror("/dev/mem"); + return -1; + } + ml = ps = getpagesize(); + of = (uint32_t)pa & (ps - 1); + if (of + (sizeof(uint32_t) * 4) > ps) + ml *= 2; + bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1)); + if (bp == MAP_FAILED) { + perror("mmap"); + goto done; + } + + vp = (char *)bp + of; + + rval = *(volatile uint32_t *)vp; + if (munmap(bp, ml) == -1) + perror("munmap"); +done: + close(fd); + + return rval; +} + +#endif /* IDPF_ACC_TIMESTAMP */ + #endif /* _IDPF_OSDEP_H_ */ diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index 19bcb94077..9c58f3fb11 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -1582,12 +1582,36 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq) void idpf_dev_read_time_hw(void *cb_arg) { -#ifdef RTE_ARCH_X86_64 struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg; uint32_t hi, lo, lo2; int rc = 0; +#ifndef IDPF_ACC_TIMESTAMP struct idpf_hw *hw = &ad->hw; +#endif /* !IDPF_ACC_TIMESTAMP */ +#ifdef IDPF_ACC_TIMESTAMP + + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + DRV_LOG(DEBUG, "lo : %X,", lo); + DRV_LOG(DEBUG, "hi : %X,", hi); + /* + * On typical system, the delta between lo and lo2 is ~1000ns, + * so 10000 seems a large-enough but not overly-big guard band. + */ + if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) + lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + else + lo2 = lo; + + if (lo2 < lo) { + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + } + + ad->time_hw = ((uint64_t)hi << 32) | lo; + +#else /* !IDPF_ACC_TIMESTAMP */ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); @@ -1608,9 +1632,7 @@ idpf_dev_read_time_hw(void *cb_arg) } ad->time_hw = ((uint64_t)hi << 32) | lo; -#else /* !RTE_ARCH_X86_64 */ - ad->time_hw = 0; -#endif /* RTE_ARCH_X86_64 */ +#endif /* IDPF_ACC_TIMESTAMP */ /* re-alarm watchdog */ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg); diff --git a/meson_options.txt b/meson_options.txt index 82c8297065..31fc634aa0 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -52,3 +52,5 @@ option('tests', type: 'boolean', value: true, description: 'build unit tests') option('use_hpet', type: 'boolean', value: false, description: 'use HPET timer in EAL') +option('enable_acc_timestamp', type: 'boolean', value: false, description: + 'enable timestamp on ACC.') From patchwork Mon Apr 24 09:17:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126453 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 507E1429D9; Mon, 24 Apr 2023 11:23:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C5FE410ED; Mon, 24 Apr 2023 11:23:04 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id EA6DA42D37; Mon, 24 Apr 2023 11:23:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328182; x=1713864182; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ES0onw81aNtcOt+1/4Kxi0Yxqsjm6OTvjbbjtk8jxI8=; b=A+an9T3c0YmaU+bAz+lZs1n2kdhNUsKtigAl0MmTiZwkmSFwCraZHMSL T5OHcbdiQG4ub3r4l4Mutxk4HwU+0lIbyt+tBS4RcIDh1GFvWd/Auh1b/ kQI23LFux9AsiaVYrgQzGAbj0lMCY0HGdR1YojPx1Ye5HFTbIAjMM73EA N4gO2O/5OCR8b51ukqSJLw3MrGcVBh/+hbuScK7tU57cXXm96MSQ/RFfg W0HVpS12iYvq0Sh2ifY1ZwCMGJ1/VHWAnDayOZpcjrq77Vpe76/TA8Npf iJy8LJdodc71mlMq4G1hAB9vZXcLpl3CE5UCrDG6XfFCyfdP/megLg1PS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680068" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680068" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:23:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895134" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895134" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:59 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 5/7] common/idpf: add timestamp enable flag for rxq Date: Mon, 24 Apr 2023 05:17:05 -0400 Message-Id: <20230424091707.488045-6-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A rxq can be configured with timestamp offload. So, add timestamp enable flag for rxq. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/common/idpf/idpf_common_rxtx.c | 3 ++- drivers/common/idpf/idpf_common_rxtx.h | 2 ++ drivers/common/idpf/version.map | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index 9c58f3fb11..7afe7afe3f 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -354,7 +354,7 @@ int idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) { int err; - if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) { + if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) { /* Register mbuf field and flag for Rx timestamp */ err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset, &idpf_timestamp_dynflag); @@ -363,6 +363,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq) "Cannot register mbuf field/flag for timestamp"); return -EINVAL; } + rxq->ts_enable = TRUE; } return 0; } diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h index af1425eb3f..cb7f5a3ba8 100644 --- a/drivers/common/idpf/idpf_common_rxtx.h +++ b/drivers/common/idpf/idpf_common_rxtx.h @@ -142,6 +142,8 @@ struct idpf_rx_queue { struct idpf_rx_queue *bufq2; uint64_t offloads; + + bool ts_enable; /* if timestamp is enabled */ }; struct idpf_tx_entry { diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map index c67c554911..15b42b4d2e 100644 --- a/drivers/common/idpf/version.map +++ b/drivers/common/idpf/version.map @@ -69,5 +69,8 @@ INTERNAL { idpf_vport_rss_config; idpf_vport_stats_update; + idpf_timestamp_dynfield_offset; + idpf_timestamp_dynflag; + local: *; }; From patchwork Mon Apr 24 09:17:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126454 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1694F429D9; Mon, 24 Apr 2023 11:23:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83B0142D40; Mon, 24 Apr 2023 11:23:05 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C44BB42D39; Mon, 24 Apr 2023 11:23:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328184; x=1713864184; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DqLh3zCghXJ233/kCLsHuOoFvu82TZga0cJMqn91/Xo=; b=C2zxrnDOVZak0kcS8wRZGU2iJZlGrGMwqeWyEXbX4crstqyuZVH7Efny BNtjysHkRXRsSjRAxYpbRoBco/GiqHfRiEz2P3Be8LrMM+IPLk2Dra8xm oxsNNUWBCUOkI3JApADRcZgny9xAJnOfd145lI2EWx5LqoWT6WiYP7YoF jEo7nIgJ+ETcLo3jQX+DrB7/+MpWH8AgvK+BZayXPQJGIHJa2SPU+Wdef iZICkf3W6yIg8446v9hl0UjK/UKoSEgGcNM7jfWbb0IRsKfgut3zZl+ck PkWhe/UHK+nPp8Wes19129o7/f5gLcrkouNePUl6sOw/pbl+cBQoAogBa Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680078" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680078" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:23:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895189" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895189" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:23:01 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev Date: Mon, 24 Apr 2023 05:17:06 -0400 Message-Id: <20230424091707.488045-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to only support timestamp at port level, registering timestamp mbuf should be at dev start stage. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++ drivers/net/cpfl/cpfl_ethdev.h | 3 +++ drivers/net/cpfl/cpfl_rxtx.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 82d8147494..416273f567 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev) rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, (void *)base); + /* Register mbuf field and flag for Rx timestamp */ + ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset, + &idpf_timestamp_dynflag); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp"); + return -EINVAL; + } } ret = idpf_vc_vectors_alloc(vport, req_vecs_num); diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index 200dfcac02..eec253bc77 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -57,6 +57,9 @@ /* Device IDs */ #define IDPF_DEV_ID_CPF 0x1453 +extern int idpf_timestamp_dynfield_offset; +extern uint64_t idpf_timestamp_dynflag; + struct cpfl_vport_param { struct cpfl_adapter_ext *adapter; uint16_t devarg_id; /* arg id from user */ diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index de59b31b3d..cdb5b37da0 100644 --- a/drivers/net/cpfl/cpfl_rxtx.c +++ b/drivers/net/cpfl/cpfl_rxtx.c @@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) frame_size > rxq->rx_buf_len) dev->data->scattered_rx = 1; + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + rxq->ts_enable = TRUE; err = idpf_qc_ts_mbuf_register(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u", From patchwork Mon Apr 24 09:17:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126455 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83345429D9; Mon, 24 Apr 2023 11:23:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DEE4742D3F; Mon, 24 Apr 2023 11:23:07 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id B9DC842D4D; Mon, 24 Apr 2023 11:23:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328186; x=1713864186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DLebQUkHpK4cO26Q3/63+/WSbu7fIKWWQZSDJZpc8MU=; b=Wuesw2RHMrK75ByHvBtlSZLPU53M0q8SDby7/OE4T/GGsQ6qk5kd46Xf VAfFW6ik2chzhDFpUGKCC3oboro60XehAHGlv3oMAw29H0Wr18rcE5w1Q tKYsYpL8c82/33kS27u9Kco2kH82/LeQ31PWIVUdwdzhxYX8JeRztnbGj BXqIECTZ+aWO19Y3EsM+zVS0CmpxWr43PN+ppF4jCv+mMDIedxFTyxUA4 7zlrX+ffwLDOnv2xRfmHw8KaA6c8ZUefPh243Sawez2+Is7ofpKCllc3F h/i/EDTxEHmPfAYF9huyBkrFsX4KppO5ojORcYcXdOL5JodITZLxR7B2+ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680103" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680103" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:23:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895210" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895210" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:23:03 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 7/7] net/idpf: register timestamp mbuf when starting dev Date: Mon, 24 Apr 2023 05:17:07 -0400 Message-Id: <20230424091707.488045-8-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Due to only support timestamp at port level, registering timestamp mbuf should be at dev start stage. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao Suggested-by: Jingjing Wu --- drivers/net/idpf/idpf_ethdev.c | 7 +++++++ drivers/net/idpf/idpf_ethdev.h | 3 +++ drivers/net/idpf/idpf_rxtx.c | 3 +++ 3 files changed, 13 insertions(+) diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c index 3f33ffbc78..7c43f51c25 100644 --- a/drivers/net/idpf/idpf_ethdev.c +++ b/drivers/net/idpf/idpf_ethdev.c @@ -765,6 +765,13 @@ idpf_dev_start(struct rte_eth_dev *dev) rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, (void *)base); + /* Register mbuf field and flag for Rx timestamp */ + ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset, + &idpf_timestamp_dynflag); + if (ret != 0) { + PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp"); + return -EINVAL; + } } ret = idpf_vc_vectors_alloc(vport, req_vecs_num); diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h index 3c2c932438..256e348710 100644 --- a/drivers/net/idpf/idpf_ethdev.h +++ b/drivers/net/idpf/idpf_ethdev.h @@ -55,6 +55,9 @@ #define IDPF_ALARM_INTERVAL 50000 /* us */ +extern int idpf_timestamp_dynfield_offset; +extern uint64_t idpf_timestamp_dynflag; + struct idpf_vport_param { struct idpf_adapter_ext *adapter; uint16_t devarg_id; /* arg id from user */ diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c index 414f9a37f6..1aaf0142d2 100644 --- a/drivers/net/idpf/idpf_rxtx.c +++ b/drivers/net/idpf/idpf_rxtx.c @@ -529,6 +529,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) frame_size > rxq->rx_buf_len) dev->data->scattered_rx = 1; + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + rxq->ts_enable = TRUE; + err = idpf_qc_ts_mbuf_register(rxq); if (err != 0) { PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",