From patchwork Tue Apr 11 04:59:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rushil Gupta X-Patchwork-Id: 125892 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BEC5542917; Tue, 11 Apr 2023 06:59:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A9B4341143; Tue, 11 Apr 2023 06:59:35 +0200 (CEST) Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) by mails.dpdk.org (Postfix) with ESMTP id 4797F40A8B for ; Tue, 11 Apr 2023 06:59:34 +0200 (CEST) Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-54f1ffb8ccfso45494557b3.9 for ; Mon, 10 Apr 2023 21:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1681189173; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cL1hdW+fdzdMMEjvWQbtAqaZ3ShM5h9I7p+kb1FIttc=; b=IwuAknhk3ILzCBFzNJlMfsWaHCBn7itMEtKowJJEOaLK2+Zk5axywW+go7YZFHfley Q0uyHHSkkWp+8gsbZBwddBDnzdbyStjHOt6QZdmo+VsOq8lLymU49oPoLM12g1FPw9MY RJ9Q2I8Vn9uDWbxF+mJHm15QystRBqeumDkKFEODDHhizCUin11nJFwRD+PAHFVhQuih VDAHGrHbysfbMKwFCgzqvpfHTcNwMPGduA8IYlVVOWs0cQiRE8buCrzEo/G0B8v04OPJ FiLCt+Yog5SpgJP9PuG4GKJQPevs4zy2VIeNXu9KSvcZkYxfdTz36U+MMhBkGBhyCU/7 FWJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681189173; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cL1hdW+fdzdMMEjvWQbtAqaZ3ShM5h9I7p+kb1FIttc=; b=6wAFKSvlYbKDOcaQv2gXPcVXQstlv6V0pLn+Sso9Ggkn4USlkLJwCM4PwAx8d5BwzH 7k5NISy4mL7n5d0M3V9ioVSbxEuOYK+InQmaf1xPpoG0fR/f3uUagItwZBh9ugK1ArOm tLBkKEOzzgx1/58s3VpFx8TP6Y20BjeXBJxOwHjE+LT41u8OGm0rzp2FuvCeLaTZlgKJ Q4clE8ox5Qs9aqvTvoscTvbKE817PktWT0NYcxqTpsNw2qPdnifAeSPrP4Cm+VKJFx5k 9rIP/05lbr7cNcUDuHzcj3qZPtzvqfn3dwUSFdfk2HfpmcNozGzzE+hLlfn5QGE2Oob7 Ol4g== X-Gm-Message-State: AAQBX9f0+EjcXZpVshdGlTJ1mlRmwVTjDCpuuqTDntl95o8GOcbZCxCg 0YfkTaSfk82ZnGYs/zjIVVjCnMXSAblz X-Google-Smtp-Source: AKy350YaJJOGl3P54whl2wrH3MQROr41oWTsdV0vwCGEjTfhFrI9+G/xKQg3vJS8CKhUtjmTJhvNbZ/OKbTX X-Received: from rushilg.sea.corp.google.com ([2620:15c:100:202:a817:a4e4:c2c5:a320]) (user=rushilg job=sendgmr) by 2002:a25:c483:0:b0:b4c:9333:2a1 with SMTP id u125-20020a25c483000000b00b4c933302a1mr8059099ybf.10.1681189173623; Mon, 10 Apr 2023 21:59:33 -0700 (PDT) Date: Mon, 10 Apr 2023 21:59:08 -0700 In-Reply-To: <20230411045908.844901-1-rushilg@google.com> Mime-Version: 1.0 References: <20230411045908.844901-1-rushilg@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Message-ID: <20230411045908.844901-2-rushilg@google.com> Subject: [PATCH 1/1] net/gve: update base code for DQO From: Rushil Gupta To: qi.z.zhang@intel.com, ferruh.yigit@amd.com Cc: bruce.richardson@intel.com, dev@dpdk.org, Rushil Gupta , Junfeng Guo X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update gve base code to support DQO. This patch is based on this: https://patchwork.dpdk.org/project/dpdk/list/?series=27647&state=* Signed-off-by: Rushil Gupta Signed-off-by: Junfeng Guo --- drivers/net/gve/base/gve.h | 1 + drivers/net/gve/base/gve_adminq.c | 10 +++++----- drivers/net/gve/base/gve_desc_dqo.h | 4 ---- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/gve/base/gve.h b/drivers/net/gve/base/gve.h index 2dc4507acb..2b7cf7d99b 100644 --- a/drivers/net/gve/base/gve.h +++ b/drivers/net/gve/base/gve.h @@ -7,6 +7,7 @@ #define _GVE_H_ #include "gve_desc.h" +#include "gve_desc_dqo.h" #define GVE_VERSION "1.3.0" #define GVE_VERSION_PREFIX "GVE-" diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c index e745b709b2..e963f910a0 100644 --- a/drivers/net/gve/base/gve_adminq.c +++ b/drivers/net/gve/base/gve_adminq.c @@ -497,11 +497,11 @@ static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index) cmd.create_tx_queue.queue_page_list_id = cpu_to_be32(qpl_id); } else { cmd.create_tx_queue.tx_ring_size = - cpu_to_be16(txq->nb_tx_desc); + cpu_to_be16(priv->tx_desc_cnt); cmd.create_tx_queue.tx_comp_ring_addr = - cpu_to_be64(txq->complq->tx_ring_phys_addr); + cpu_to_be64(txq->compl_ring_phys_addr); cmd.create_tx_queue.tx_comp_ring_size = - cpu_to_be16(priv->tx_compq_size); + cpu_to_be16(priv->tx_compq_size * DQO_TX_MULTIPLIER); } return gve_adminq_issue_cmd(priv, &cmd); @@ -549,9 +549,9 @@ static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index) cmd.create_rx_queue.rx_ring_size = cpu_to_be16(priv->rx_desc_cnt); cmd.create_rx_queue.rx_desc_ring_addr = - cpu_to_be64(rxq->rx_ring_phys_addr); + cpu_to_be64(rxq->compl_ring_phys_addr); cmd.create_rx_queue.rx_data_ring_addr = - cpu_to_be64(rxq->bufq->rx_ring_phys_addr); + cpu_to_be64(rxq->rx_ring_phys_addr); cmd.create_rx_queue.packet_buffer_size = cpu_to_be16(rxq->rx_buf_len); cmd.create_rx_queue.rx_buff_ring_size = diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h index ee1afdecb8..bb4a18d4d1 100644 --- a/drivers/net/gve/base/gve_desc_dqo.h +++ b/drivers/net/gve/base/gve_desc_dqo.h @@ -13,10 +13,6 @@ #define GVE_TX_MAX_HDR_SIZE_DQO 255 #define GVE_TX_MIN_TSO_MSS_DQO 88 -#ifndef __LITTLE_ENDIAN_BITFIELD -#error "Only little endian supported" -#endif - /* Basic TX descriptor (DTYPE 0x0C) */ struct gve_tx_pkt_desc_dqo { __le64 buf_addr;