From patchwork Mon Nov 28 04:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kiran Kumar Kokkilagadda X-Patchwork-Id: 120180 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5473A0093; Mon, 28 Nov 2022 05:33:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B8E84067C; Mon, 28 Nov 2022 05:33:39 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E2B4340156 for ; Mon, 28 Nov 2022 05:33:37 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2ARMdYGo015399 for ; Sun, 27 Nov 2022 20:33:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=opLsPmlrV7Ak9IAqfmWXxSr16KW6zD2Xv4+6pNNAHWs=; b=jz3/jnEL8vuLyWw34AuE3B7IiZBSPPh3tR6AubI/v+dXxk4E6QMzA+X2cUkrJG4/P0fF 5ePLrYGdOtK0AO0SDsOWlb9DsRznqGLmEok5YZOCF5XPQDYfruMEfqe2RRcd3aSOdokX 2VXoLyFQxTDR56ND/Y7MW/6cPetaFV4GHyLUTy47dXG293CjivvYu6Zqk2dJ6El3yJyR li2qvG60W0KoHS5vpctmWLaOA1aNZ4IxWn+8AfoIs1pr7yTjxUO6Oue6ZcPxxA+PEu9D 4IvX8PQXxmX5KXsCl2rs6nwf6s4YTuJeOLSEEqbeBmuLW4dPYe/Qk4d31egAHXzvZsLb 2g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3m3k6w4321-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 27 Nov 2022 20:33:37 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 27 Nov 2022 20:33:34 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 27 Nov 2022 20:33:34 -0800 Received: from cavium-kiran.. (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 055A63F70A1; Sun, 27 Nov 2022 20:33:32 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Subject: [dpdk-dev][PATCH] net/cnxk: add support for L2 ether ptype for cnxk Date: Mon, 28 Nov 2022 10:03:27 +0530 Message-ID: <20221128043327.1472374-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Proofpoint-GUID: 3BcW8WpuE3ig-HaB-XH0fu389BSBGk8e X-Proofpoint-ORIG-GUID: 3BcW8WpuE3ig-HaB-XH0fu389BSBGk8e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-28_04,2022-11-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kiran Kumar K Adding lookup support for RTE_PTYPE_L2_ETHER in cnxk driver. Signed-off-by: Kiran Kumar K --- drivers/net/cnxk/cnxk_lookup.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c index f36fb8f27a..5acf73fe17 100644 --- a/drivers/net/cnxk/cnxk_lookup.c +++ b/drivers/net/cnxk/cnxk_lookup.c @@ -15,6 +15,7 @@ cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev) RTE_SET_USED(eth_dev); static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, /* LA */ RTE_PTYPE_L2_ETHER_QINQ, /* LB */ RTE_PTYPE_L2_ETHER_VLAN, /* LB */ RTE_PTYPE_L2_ETHER_TIMESYNC, /* LB */ @@ -88,19 +89,25 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype) case NPC_LT_LB_CTAG: val |= RTE_PTYPE_L2_ETHER_VLAN; break; + default: + val |= RTE_PTYPE_L2_ETHER; } switch (lc) { case NPC_LT_LC_ARP: + val = (val & ~RTE_PTYPE_L2_MASK); val |= RTE_PTYPE_L2_ETHER_ARP; break; case NPC_LT_LC_NSH: + val = (val & ~RTE_PTYPE_L2_MASK); val |= RTE_PTYPE_L2_ETHER_NSH; break; case NPC_LT_LC_FCOE: + val = (val & ~RTE_PTYPE_L2_MASK); val |= RTE_PTYPE_L2_ETHER_FCOE; break; case NPC_LT_LC_MPLS: + val = (val & ~RTE_PTYPE_L2_MASK); val |= RTE_PTYPE_L2_ETHER_MPLS; break; case NPC_LT_LC_IP: @@ -116,6 +123,7 @@ nix_create_non_tunnel_ptype_array(uint16_t *ptype) val |= RTE_PTYPE_L3_IPV6_EXT; break; case NPC_LT_LC_PTP: + val = (val & ~RTE_PTYPE_L2_MASK); val |= RTE_PTYPE_L2_ETHER_TIMESYNC; break; }