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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0000C406.mail.protection.outlook.com (10.167.241.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Thu, 17 Nov 2022 14:42:43 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 17 Nov 2022 06:42:23 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 17 Nov 2022 06:42:21 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko , Suanming Mou CC: , Raslan Darawsheh Subject: [PATCH] net/mlx5: fix modify field operation validation Date: Thu, 17 Nov 2022 14:41:44 +0000 Message-ID: <20221117144144.1665722-1-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000C406:EE_|BL3PR12MB6642:EE_ X-MS-Office365-Filtering-Correlation-Id: 38d42811-f32f-494d-f769-08dac8a9fc59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2022 14:42:43.2941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38d42811-f32f-494d-f769-08dac8a9fc59 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000C406.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6642 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch removes the following checks from validation of modify field action: - rejection of ADD operation, - offsets should be aligned to 4 bytes. These limitations were removed in commit 0f4aa72b99da ("net/mlx5: support flow modify field with HWS"), but non-HWS validation was not updated. Notes about these limitations are removed from mlx5 PMD docs. On top of that, the current offsetting behavior in modify field action is clarified in the mlx5 docs. Fixes: 0f4aa72b99da ("net/mlx5: support flow modify field with HWS") Cc: suanmingm@nvidia.com Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 21 ++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 4f0db21dde..203bbd9d27 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -447,17 +447,23 @@ Limitations - Modify Field flow: - - Supports the 'set' operation only for ``RTE_FLOW_ACTION_TYPE_MODIFY_FIELD`` action. + - Supports the 'set' and 'add' operations for ``RTE_FLOW_ACTION_TYPE_MODIFY_FIELD`` action. - Modification of an arbitrary place in a packet via the special ``RTE_FLOW_FIELD_START`` Field ID is not supported. - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported. - Encapsulation levels are not supported, can modify outermost header fields only. - - Offsets must be 32-bits aligned, cannot skip past the boundary of a field. + - Offsets cannot skip past the boundary of a field. - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE`` and packet contains one or more VLAN headers, the meaningful type field following the last VLAN header is used as modify field operation argument. The modify field action is not intended to modify VLAN headers type field, dedicated VLAN push and pop actions should be used instead. + - For packet fields (e.g. MAC addresses, IPv4 addresses or L4 ports) + offset specifies the number of bits to skip from field's start, + starting from MSB in the first byte, in the network order. + - For flow metadata fields (e.g. META or TAG) + offset specifies the number of bits to skip from field's start, + starting from LSB in the least significant byte, in the host order. - Age action: diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index bc9a75f225..f1a3868e48 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5035,13 +5035,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, " the width of a field"); if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE && action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) { - if ((action_modify_field->dst.offset + - action_modify_field->width > dst_width) || - (action_modify_field->dst.offset % 32)) + if (action_modify_field->dst.offset + + action_modify_field->width > dst_width) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, - "destination offset is too big" - " or not aligned to 4 bytes"); + "destination offset is too big"); if (action_modify_field->dst.level && action_modify_field->dst.field != RTE_FLOW_FIELD_TAG) return rte_flow_error_set(error, ENOTSUP, @@ -5056,13 +5054,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "modify field action is not" " supported for group 0"); - if ((action_modify_field->src.offset + - action_modify_field->width > src_width) || - (action_modify_field->src.offset % 32)) + if (action_modify_field->src.offset + + action_modify_field->width > src_width) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, - "source offset is too big" - " or not aligned to 4 bytes"); + "source offset is too big"); if (action_modify_field->src.level && action_modify_field->src.field != RTE_FLOW_FIELD_TAG) return rte_flow_error_set(error, ENOTSUP, @@ -5132,11 +5128,10 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, "cannot modify meta without" " extensive registers available"); } - if (action_modify_field->operation != RTE_FLOW_MODIFY_SET) + if (action_modify_field->operation == RTE_FLOW_MODIFY_SUB) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action, - "add and sub operations" - " are not supported"); + "sub operations are not supported"); if (action_modify_field->dst.field == RTE_FLOW_FIELD_IPV4_ECN || action_modify_field->src.field == RTE_FLOW_FIELD_IPV4_ECN || action_modify_field->dst.field == RTE_FLOW_FIELD_IPV6_ECN ||