From patchwork Fri Oct 21 05:20:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118839 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F3C8A0552; Thu, 20 Oct 2022 23:24:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA00C4282D; Thu, 20 Oct 2022 23:24:37 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id CCFF340FAE; Thu, 20 Oct 2022 23:24:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301076; x=1697837076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gwyd+01g6kF0VZMaCZCULw9hNkTDvbEptlyUbPOUevo=; b=aUVTYdnbm3GuLImDnGXWzpbONNapxLSyjvxYtxpc7cePWoBZImbCwe9Q TWpeJa/pvqbAZ9OZFIS5ms3fPFTKOYTXMaHeQm3xnXpuP5MBScYfiOgfr ZMbZlJFxDRpT97prEI8xmp9CLlyJ29wf8iGmRLcDzD3TN2Z/I0/nsm5SK 048qn2SA1BtnCo4CxEsi4EuPR8xDUbInOk0qOR/U67iC1LWD6w5qODu/r bygo63b/KVZ/y4J+hW2X7ZNqt8RhAS0Vn5GE8dN3r4nUGBpGAPxQE9ZaG b6j8+HmJmq0Z2lf8+y0ZAzZiyqg5TDB0S3uwNYV3Dq30CsGZNl3TBWdW2 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887450" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887450" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396794" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396794" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:29 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 01/29] baseband/acc100: fix ring availability calculation Date: Thu, 20 Oct 2022 22:20:34 -0700 Message-Id: <20221021052102.107141-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor of the queue availability computation to prevent the application to dequeue more than what may have been enqueued. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index e5384223d1..3b0c8e41dc 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2861,7 +2861,7 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -2899,7 +2899,7 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i = 0; union acc_dma_desc *desc; int ret, desc_idx = 0; @@ -2949,7 +2949,7 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3011,7 +3011,7 @@ acc100_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -3050,7 +3050,7 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3083,7 +3083,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -3132,7 +3132,7 @@ acc100_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3495,12 +3495,13 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i, dequeued_cbs = 0; struct rte_bbdev_enc_op *op; int ret; - + if (avail == 0) + return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG if (unlikely(ops == NULL || q == NULL)) { rte_bbdev_log_debug("Unexpected undefined pointer"); @@ -3539,7 +3540,7 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0; int ret; @@ -3579,7 +3580,7 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i; uint16_t dequeued_cbs = 0; @@ -3623,7 +3624,7 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i; uint16_t dequeued_cbs = 0; From patchwork Fri Oct 21 05:20:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118840 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75620A0552; Thu, 20 Oct 2022 23:24:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D0A7C42B6F; Thu, 20 Oct 2022 23:24:39 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 28D8A410D1; Thu, 20 Oct 2022 23:24:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; 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d="scan'208";a="755396799" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:29 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 02/29] baseband/acc100: add function to check AQ availability Date: Thu, 20 Oct 2022 22:20:35 -0700 Message-Id: <20221021052102.107141-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org It is possible for some corner case to run more batch enqueue than supported. A protection is required to avoid that corner case. Enhance all ACC100 enqueue operations with check to see if there is room in the atomic queue for enqueueing batches into the queue manager Check room in AQ for the enqueues batches into Qmgr Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 3b0c8e41dc..7fec2283eb 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2983,7 +2983,8 @@ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -2996,7 +2997,8 @@ static uint16_t acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -3164,8 +3166,11 @@ static uint16_t acc100_enqueue_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; + if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_dec_tb(q_data, ops, num); else @@ -3177,11 +3182,9 @@ static uint16_t acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - struct acc_queue *q = q_data->queue_private; - int32_t aq_avail = q->aq_depth + - (q->aq_dequeued - q->aq_enqueued) / 128; + int32_t aq_avail = acc_aq_avail(q_data, num); - if (unlikely((aq_avail == 0) || (num == 0))) + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) @@ -3190,7 +3193,6 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, return acc100_enqueue_ldpc_dec_cb(q_data, ops, num); } - /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, From patchwork Fri Oct 21 05:20:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118841 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06CD0A0552; Thu, 20 Oct 2022 23:24:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BCBAF42B83; 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20 Oct 2022 14:24:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396810" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396810" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:30 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 03/29] baseband/acc100: memory leak fix Date: Thu, 20 Oct 2022 22:20:36 -0700 Message-Id: <20221021052102.107141-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move check for undefined device before allocating queue data structure. Coverity issue: 375803, 375813, 375819, 375827, 375831 Fixes: 060e7672930 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7fec2283eb..7500ef6eb5 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -663,6 +663,10 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc_queue *q; int16_t q_idx; + if (d == NULL) { + rte_bbdev_log(ERR, "Undefined device"); + return -ENODEV; + } /* Allocate the queue data structure. */ q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q), RTE_CACHE_LINE_SIZE, conf->socket); @@ -670,10 +674,6 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, rte_bbdev_log(ERR, "Failed to allocate queue memory"); return -ENOMEM; } - if (d == NULL) { - rte_bbdev_log(ERR, "Undefined device"); - return -ENODEV; - } q->d = d; q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); From patchwork Fri Oct 21 05:20:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118842 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25BB1A0552; Thu, 20 Oct 2022 23:25:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABCC542B8E; Thu, 20 Oct 2022 23:24:41 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id F36AB4281B; Thu, 20 Oct 2022 23:24:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301077; x=1697837077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5F/3gCC20G36+GeZAiT69L2Whdam85RuPFc+652cQj8=; b=I4tGKnBPfD7BxoTNyruF9ALfTHs1UdlPiF4ROC6BFqy/wZOIBirVvouO 1eZg5RmONx26DKzXPALZ8EcrVwRzIgkSj91zfCw+mRR41GLgjLUTtocy+ oCDXvRojFUFKMOfpe8RjYDrjos9pgvbkVsNar2O6tc1TuC9EuEdAuNBny qKQ7MZDKJ4rPaK2MQKN1Z98FbYrvh1xm/T5GCxwMTKR9s/1yYlkVLCsL0 yH7hRTEu6HlS5aytdOPGrjaqD2pHMrHnGsK1HQcLXcnBFok4QOUT+40zS rV+BTcvVEOMmHhUgRjlGxrzHuoaQy9ZXf6QfwNTp8f1Tr/CQ9TR9Lsd/d g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887459" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887459" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396818" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396818" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:30 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 04/29] baseband/acc100: add LDPC encoder padding function Date: Thu, 20 Oct 2022 22:20:37 -0700 Message-Id: <20221021052102.107141-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LDPC Encoder input may need to be padded to avoid small beat for ACC100. Padding 5GDL input buffer length (BLEN) to avoid case (BLEN % 64) <= 8. Adding protection for corner case to avoid for 5GDL occurrence of last beat within the ACC100 fabric with <= 8B which might trigger a fabric corner case hang issue. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 28 ++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7500ef6eb5..577c107e9a 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1017,14 +1017,13 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } -#ifdef RTE_LIBRTE_BBDEV_DEBUG - static inline bool is_acc100(struct acc_queue *q) { return (q->d->device_variant == ACC100_VARIANT); } +#ifdef RTE_LIBRTE_BBDEV_DEBUG static inline bool validate_op_required(struct acc_queue *q) { @@ -1355,12 +1354,28 @@ acc100_dma_fill_blk_type_in(struct acc_dma_req_desc *desc, return next_triplet; } +/* May need to pad LDPC Encoder input to avoid small beat for ACC100. */ +static inline uint16_t +pad_le_in(uint16_t blen, struct acc_queue *q) +{ + uint16_t last_beat; + + if (!is_acc100(q)) + return blen; + + last_beat = blen % 64; + if ((last_beat > 0) && (last_beat <= 8)) + blen += 8; + + return blen; +} + static inline int acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, struct acc_dma_req_desc *desc, struct rte_mbuf **input, struct rte_mbuf *output, uint32_t *in_offset, uint32_t *out_offset, uint32_t *out_length, - uint32_t *mbuf_total_left, uint32_t *seg_total_left) + uint32_t *mbuf_total_left, uint32_t *seg_total_left, struct acc_queue *q) { int next_triplet = 1; /* FCW already done */ uint16_t K, in_length_in_bits, in_length_in_bytes; @@ -1384,8 +1399,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - in_length_in_bytes, - seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -2035,7 +2049,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, acc_header_init(&desc->req); desc->req.numCBs = num; - in_length_in_bytes = ops[0]->ldpc_enc.input.data->data_len; + in_length_in_bytes = pad_le_in(ops[0]->ldpc_enc.input.data->data_len, q); out_length = (enc->cb_params.e + 7) >> 3; desc->req.m2dlen = 1 + num; desc->req.d2mlen = num; @@ -2102,7 +2116,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, ret = acc100_dma_desc_le_fill(op, &desc->req, &input, output, &in_offset, &out_offset, &out_length, &mbuf_total_left, - &seg_total_left); + &seg_total_left, q); if (unlikely(ret < 0)) return ret; From patchwork Fri Oct 21 05:20:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118843 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D747FA0552; Thu, 20 Oct 2022 23:25:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D340A42836; 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20 Oct 2022 14:24:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396824" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396824" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:31 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 05/29] baseband/acc100: check turbo dec/enc input Date: Thu, 20 Oct 2022 22:20:38 -0700 Message-Id: <20221021052102.107141-6-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add NULL check for the turbo decoder and encoder input length. Fixes: 3bfc5f60403 ("baseband/acc100: add debug function to validate input") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 577c107e9a..eba70654e8 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1764,6 +1764,11 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) return -1; } + if (unlikely(turbo_enc->input.length == 0)) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_enc->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -1783,11 +1788,12 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (unlikely(tb->c_neg > 0)) { rte_bbdev_log(ERR, - "c_neg (%u) is out of range 0 <= value <= %u", - tb->c_neg, - RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + "c_neg (%u) expected to be null", + tb->c_neg); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", @@ -2281,6 +2287,11 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) return -1; } + if (unlikely(turbo_dec->input.length == 0)) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_dec->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -2301,11 +2312,13 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (unlikely(tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))) { rte_bbdev_log(ERR, "c_neg (%u) is out of range 0 <= value <= %u", tb->c_neg, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", From patchwork Fri Oct 21 05:20:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118844 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E33BAA0552; Thu, 20 Oct 2022 23:25:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD2C442B9D; Thu, 20 Oct 2022 23:24:43 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 6E11340FAE; Thu, 20 Oct 2022 23:24:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301077; x=1697837077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1KiuvWNIu50GnotuVLWMcDjg+BtQXgO5oPfYN3EHgzY=; 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Fixes: f404dfe35cc ("baseband/acc100: support 4G processing") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index eba70654e8..e8ec70d954 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2180,6 +2180,10 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, r = op->turbo_enc.tb_params.r; while (mbuf_total_left > 0 && r < c) { + if (unlikely(input == NULL)) { + rte_bbdev_log(ERR, "Not enough input segment"); + return -EINVAL; + } seg_total_left = rte_pktmbuf_data_len(input) - in_offset; /* Set up DMA descriptor */ desc = acc_desc(q, total_enqueued_cbs); @@ -3097,6 +3101,8 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, break; enqueued_cbs += ret; } + if (unlikely(enqueued_cbs == 0)) + return 0; /* Nothing to enqueue */ acc_dma_enqueue(q, enqueued_cbs, &q_data->queue_stats); @@ -3625,6 +3631,8 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = acc_op_tail(q, dequeued_cbs); + if (unlikely(op == NULL)) + break; if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); @@ -3670,6 +3678,8 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(op == NULL)) + break; if (op->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); From patchwork Fri Oct 21 05:20:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118846 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C538A0552; Thu, 20 Oct 2022 23:25:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F12D142BB7; Thu, 20 Oct 2022 23:24:45 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id B9B8E4281B; Thu, 20 Oct 2022 23:24:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301078; x=1697837078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w4xotwoAj9Ovucgg2l9BF8Yq4JUc7WzCYcrVVZOz2SY=; b=MAuMoCsytyU4cxrROd3fIFeZ/2jxOFEtydG7QCspaHkZlKD6UjPAig6c pUB51sQPYD57zPYKMinVovPBD3xg1/16HNuimutezqX1o2VA5/Ivcomqn iQbvbfCNuahX8O2/kARGJm87R6X+RQASixBS5MNcvCSy/Si5anNifHAW5 DXADL+p5M7QACg5cEECjSEgmiIinc2kzfFtv3+018otGUHR6o4zi+vF3/ eoFwSk2LTg5uRsPpqmPiZ/f+jFA+1+1N9GUgwZym8KX5rgO4DSD3FRSAZ PGbRCIWcX9XWxB22RJUxNlqMaGdMHZ8a1zwBIV8qcQ1CZdYkuqYaCpJkE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887465" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887465" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396835" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396835" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 07/29] baseband/acc100: enforce additional check on FCW Date: Thu, 20 Oct 2022 22:20:40 -0700 Message-Id: <20221021052102.107141-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc100_pmd.h | 1 + drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc100_pmd.c | 71 ++++++++++++++++++++++----- 3 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index 9486e98521..eb6349c85a 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -87,6 +87,7 @@ #define ACC100_HARQ_DDR (512 * 1) #define ACC100_PRQ_DDR_VER 0x10092020 #define ACC100_DDR_TRAINING_MAX (5000) +#define ACC100_HARQ_ALIGN_COMP 256 struct acc100_registry_addr { unsigned int dma_ring_dl5g_hi; diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 6f141c95ce..97d10b8b40 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -120,6 +120,7 @@ #define ACC_ALGO_SPA 0 #define ACC_ALGO_MSA 1 +#define ACC_HARQ_ALIGN_64B 64 /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index e8ec70d954..13a762cb80 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1040,6 +1040,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, uint16_t harq_index; uint32_t l; bool harq_prun = false; + uint32_t max_hc_in; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1089,13 +1090,22 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP); + + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; - fcw->hcin_size1 = harq_in_length - - harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - harq_layout[harq_index].offset; } else { fcw->hcin_size0 = harq_in_length; fcw->hcin_offset = 0; @@ -1107,6 +1117,21 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } + fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); @@ -1131,15 +1156,27 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcout_en > 0) { parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; - k0_p = (fcw->k0 > parity_offset) ? - fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; - if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && - harq_prun) { + harq_out_length = RTE_MAX(harq_out_length, l); + + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; fcw->hcout_offset = k0_p & 0xFFC0; fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; @@ -1148,6 +1185,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { @@ -1188,6 +1233,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, /* Disable HARQ input in that case to carry forward */ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; } + if (unlikely(fcw->rm_e == 0)) { + rte_bbdev_log(WARNING, "Null E input provided"); + fcw->rm_e = 2; + } fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); From patchwork Fri Oct 21 05:20:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118845 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE8F4A0552; Thu, 20 Oct 2022 23:25:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C34B42BB0; Thu, 20 Oct 2022 23:24:45 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id EED4442836; Thu, 20 Oct 2022 23:24:37 +0200 (CEST) DKIM-Signature: v=1; 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d="scan'208";a="755396841" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 08/29] baseband/acc100: allocate ring/queue mem when NULL Date: Thu, 20 Oct 2022 22:20:41 -0700 Message-Id: <20221021052102.107141-9-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allocate info ring, tail pointers and HARQ layout memory for a device only if it hasn't already been allocated. Fixes: 06531464151 ("baseband/acc100: support interrupt") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 30 ++++++++++++++++++--------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 13a762cb80..b737374d71 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -408,9 +408,9 @@ allocate_info_ring(struct rte_bbdev *dev) reg_addr = &vf_reg_addr; /* Allocate InfoRing */ d->info_ring = rte_zmalloc_socket("Info Ring", - ACC_INFO_RING_NUM_ENTRIES * - sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, - dev->data->socket_id); + ACC_INFO_RING_NUM_ENTRIES * + sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, + dev->data->socket_id); if (d->info_ring == NULL) { rte_bbdev_log(ERR, "Failed to allocate Info Ring for %s:%u", @@ -499,7 +499,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) acc_reg_write(d, reg_addr->ring_size, value); /* Configure tail pointer for use when SDONE enabled */ - d->tail_ptrs = rte_zmalloc_socket( + if (d->tail_ptrs == NULL) + d->tail_ptrs = rte_zmalloc_socket( dev->device->driver->name, ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t), RTE_CACHE_LINE_SIZE, socket_id); @@ -507,8 +508,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) rte_bbdev_log(ERR, "Failed to allocate tail ptr for %s:%u", dev->device->driver->name, dev->data->dev_id); - rte_free(d->sw_rings); - return -ENOMEM; + ret = -ENOMEM; + goto free_sw_rings; } d->tail_ptr_iova = rte_malloc_virt2iova(d->tail_ptrs); @@ -531,15 +532,16 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Continue */ } - d->harq_layout = rte_zmalloc_socket("HARQ Layout", + if (d->harq_layout == NULL) + d->harq_layout = rte_zmalloc_socket("HARQ Layout", ACC_HARQ_LAYOUT * sizeof(*d->harq_layout), RTE_CACHE_LINE_SIZE, dev->data->socket_id); if (d->harq_layout == NULL) { rte_bbdev_log(ERR, "Failed to allocate harq_layout for %s:%u", dev->device->driver->name, dev->data->dev_id); - rte_free(d->sw_rings); - return -ENOMEM; + ret = -ENOMEM; + goto free_tail_ptrs; } /* Mark as configured properly */ @@ -548,8 +550,16 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) rte_bbdev_log_debug( "ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#" PRIx64, dev->data->name, d->sw_rings, d->sw_rings_iova); - return 0; + +free_tail_ptrs: + rte_free(d->tail_ptrs); + d->tail_ptrs = NULL; +free_sw_rings: + rte_free(d->sw_rings_base); + d->sw_rings = NULL; + + return ret; } static int From patchwork Fri Oct 21 05:20:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118847 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 674AAA0552; Thu, 20 Oct 2022 23:25:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08A4142BA3; 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20 Oct 2022 14:24:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396846" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396846" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 09/29] baseband/acc100: reduce input length for CRC24B Date: Thu, 20 Oct 2022 22:20:42 -0700 Message-Id: <20221021052102.107141-10-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Input length should be reduced only for CRC24B. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index b737374d71..7ec63dc470 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1444,8 +1444,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; in_length_in_bits = K - enc->n_filler; - if ((enc->op_flags & RTE_BBDEV_LDPC_CRC_24A_ATTACH) || - (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH) in_length_in_bits -= 24; in_length_in_bytes = in_length_in_bits >> 3; From patchwork Fri Oct 21 05:20:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118848 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D62EA0552; Thu, 20 Oct 2022 23:25:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE44E42BC7; Thu, 20 Oct 2022 23:24:47 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A6D3C42B72; Thu, 20 Oct 2022 23:24:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301078; x=1697837078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LB9QWzP/mv0UgnEkVWOVU52377gQj0Ek2xd3Gf3WZbM=; b=Y4nUzO3okqPZBCnot1hHLsbbibshvaofKmggpIM1shpSjuUKkhJu3vmT HLSxXtPDMV+SUtufdIe8Az/ohUp3CNtCdsGGsAxoVpJVGnZ67FszaN5Xf 9zvH/1GiuBbNIHJ4tUxADiJCCQUXpqIyfyhcl3CBe6Y0iS57IW87TGbXd WHSTu9yW7H4aiUEIwWGdS+HZdR6q8nLmSc3UODMCv5hpwDoWJIzEbP54C 6iNYJxTJxPfKjHuBSh3NZHWbqpJ9BC4Va8KqyLkc/QuYjNX+pI+sK8yML q9Ro1aU7zpD+ceDnGs0DOz/zGDbM/w3ioYnu7Kk9icmGmnB7WmoAJcwVy w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887475" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887475" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396854" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396854" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 10/29] baseband/acc100: fix clearing PF IR outside handler Date: Thu, 20 Oct 2022 22:20:43 -0700 Message-Id: <20221021052102.107141-11-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Clearing of PF info ring outside of handler may cause interrupt to be missed. A condition in the ACC100 PMD implementation may cause an interrupt functional handler call to be missed due to related bit being cleared when checking PF info ring status. Fixes: 06531464151 ("baseband/acc100: support interrupt") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7ec63dc470..3bb93a1e07 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -262,11 +262,12 @@ acc100_check_ir(struct acc_device *acc100_dev) while (ring_data->valid) { if ((ring_data->int_nb < ACC100_PF_INT_DMA_DL_DESC_IRQ) || ( ring_data->int_nb > - ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) + ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) { rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x", ring_data->int_nb, ring_data->detailed_info); - /* Initialize Info Ring entry and move forward */ - ring_data->val = 0; + /* Initialize Info Ring entry and move forward */ + ring_data->val = 0; + } info_ring_head++; ring_data = acc100_dev->info_ring + (info_ring_head & ACC_INFO_RING_MASK); From patchwork Fri Oct 21 05:20:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118849 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E71D3A0552; Thu, 20 Oct 2022 23:25:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF99942BD2; Thu, 20 Oct 2022 23:24:48 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id B455942B7B; Thu, 20 Oct 2022 23:24:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301079; x=1697837079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7Y8g7y0WS+jb0pWTAD2OcdGIhEXQGtuuNFnd3B7a1Do=; b=dHhtxXYwHHqIfs9uFmiTif70xICc4OldGKIJ19d5lNugt/fIamNepqju 6ogRXbWG0+LGwIulYlCK3AqADIYbke++ql989rJdAMXgBMgSbmgBhxqWR wTfFbvkJ7RSNrkN0tmkYOXGJ4e6X80pyZAc8tpioIMC7ZY8sAKbTySfQY aTSsv/xJgBYvzyrUmkKQEfBs0s8xVB4wP+omvH8oRotXDBPrybmzP7LAs jEVXEJG8/LeSXG8N7ei81Bti44CEINIvYTTeNqAt6nokqqRfNy/ApeFp6 kieBb3KF5i5ealNeVVr3quAQoRjQzMde94fxxg7GQOEI3D4y39sDW9w0J w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887478" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887478" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396861" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396861" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 11/29] baseband/acc100: set device min alignment to 1 Date: Thu, 20 Oct 2022 22:20:44 -0700 Message-Id: <20221021052102.107141-12-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Historical mistakes, there should be no 64B alignment requirement for the buffer being processed. Any 1B alignment is sufficient. Fixes: 9200ffa5cd5 ("baseband/acc100: add info get function") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 3bb93a1e07..600a10b9fb 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -938,7 +938,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc_conf.q_ul_4g.num_qgroups - 1; dev_info->default_queue_conf = default_queue_conf; dev_info->cpu_flag_reqs = NULL; - dev_info->min_alignment = 64; + dev_info->min_alignment = 1; dev_info->capabilities = bbdev_capabilities; #ifdef ACC100_EXT_MEM dev_info->harq_buffer_size = d->ddr_size; From patchwork Fri Oct 21 05:20:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118850 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81A8FA0553; Thu, 20 Oct 2022 23:25:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7323342BD6; Thu, 20 Oct 2022 23:24:49 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 1F4B44281B; Thu, 20 Oct 2022 23:24:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301079; x=1697837079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kdAIu9IOqxkPa5j1fajcO4p4M8SKkM6VNr9lVr9ertw=; b=HQlGzvlXRbcNRctRf0EcY0O5n1RIQShRMR5kG4lS1fut7s87IPBuN6qq S0tjSP2wMsgPX/7M7ujy/TTMIolq9pBCo6BNE5C09bt5uAcdMMOFBRak6 H0rzX5CleuFmihftHTFdsnxfT7WSaWb66rWLuoU8lW6iVgeriDDuWSSLp ByvtUEeVczUOzlaIopZYnZFV0GWGakkKEZcrjJqtbeRSKrrfDuQDs8hS9 ZimjV6QvGLZL4gykVH1xUOdR++OaXZsJrqW8/nXgurwAp0M4OXQxwHlty 5uy41J1TDDUC8JMgSiSCkcQay66vIiHy9IiXEnxKJ5KqihjM3hgcYV6r+ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887480" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887480" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396864" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396864" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 12/29] baseband/acc100: add protection for NULL HARQ input Date: Thu, 20 Oct 2022 22:20:45 -0700 Message-Id: <20221021052102.107141-13-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org It is possible to cause an invalid HW operation in case the user provides the BBDEV API and HARQ operation with input enabled and zero input. Adding protection for that case. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 600a10b9fb..a711862892 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1068,6 +1068,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, op->ldpc_dec.tb_params.ea : op->ldpc_dec.tb_params.eb; + if (unlikely(check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + (op->ldpc_dec.harq_combined_input.length == 0))) { + rte_bbdev_log(WARNING, "Null HARQ input size provided"); + /* Disable HARQ input in that case to carry forward. */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); fcw->hcout_en = check_bit(op->ldpc_dec.op_flags, From patchwork Fri Oct 21 05:20:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118852 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5BA9A0552; Thu, 20 Oct 2022 23:26:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6974442BE7; Thu, 20 Oct 2022 23:24:51 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 6F77842836; Thu, 20 Oct 2022 23:24:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301079; x=1697837079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lmulB67DZqUlWA/WD70L85a4Tp1CgXPdLDifCk139iA=; b=GhJ3egR62UFxMqfNswOU5PKshzDjrFFzP1wO7hs7czi+0Ee0rl3YMyCr WOUqK097fAatmmxC5t0WTkyOIqy4TpqhHbPEQ2BeAa/ZIHSoO8W2RqURC /c2YBYCyPXrko/BxMEF9yYKogWJUGMrnUsHokhrAwtSIOjXqxqyhkJA+I L4E7Ymbsx8VPt8gH3OKVylWDAh0TwL1zO2rlS7/llDutGzkt636MiNtQb UvvY4Au69jcuUWD+11cbbOE1p50/7yN+kAvUz7e1mBz0Ic97Rsj6fSDlN rJHTAtdW8qqav/AhNcQFw4rqZaoMwG/raAYiC+8IPEUv0SgxNdum+a4rm Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887484" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887484" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396870" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396870" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:35 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 13/29] baseband/acc100: reset pointer after rte_free Date: Thu, 20 Oct 2022 22:20:46 -0700 Message-Id: <20221021052102.107141-14-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set local pointer to NULL after rte_free. This needs to be set explicitly since logic may check for null pointers. Fixes: 060e7672930 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index a711862892..ad815ed76a 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -618,6 +618,9 @@ acc100_dev_close(struct rte_bbdev *dev) rte_free(d->info_ring); rte_free(d->sw_rings_base); d->sw_rings_base = NULL; + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; } /* Ensure all in flight HW transactions are completed */ usleep(ACC_LONG_WAIT); From patchwork Fri Oct 21 05:20:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118851 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85E22A0552; Thu, 20 Oct 2022 23:26:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9839B42BA7; Thu, 20 Oct 2022 23:24:50 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 8F24D42B6D for ; Thu, 20 Oct 2022 23:24:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301079; x=1697837079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6nNg5WM09R30rM2SfZEIcuATgrDDlove3sYXISj/lgk=; b=fFcJNywZoqCuIpUZzxtUwAwPRWk4aocfrTDj5O5O6Qw9oMaoYFkHg+J4 8ZZPu6GCWlq4F3RIcv/f58v0cB13EDvnPI5lvDLcHl7BvmHiMO37NZNcz sVcTrPJVYswoen7mQaLI2az49Dk1zSlpRTbxb/CzYMtZG8SgInZZUwps4 HJ8lAmswSxGoexi9lvpWIM0qMpzLHSVh+JntKbetzIoyzsvnljDtJehTz 0JiEcKdqQGNki5ATCMzXKryyYlPxcYJYKx/96bROTdq+DO87tsqB3uY0u vKgyJ8/jDeWLVJ71vVtLZwhxTJze87HkPTYrbGsxXoFcxYZKJatB5nmBR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887487" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887487" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396875" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396875" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:35 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 14/29] baseband/acc100: fix debug print for LDPC FCW Date: Thu, 20 Oct 2022 22:20:47 -0700 Message-Id: <20221021052102.107141-15-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Print full size of FCW LDPC structure on debug messages. This is just a cosmetic fix, no need to fix on previous code base. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index ad815ed76a..2896bc0c5e 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2757,7 +2757,7 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_ld, - sizeof(desc->req.fcw_ld) - 8); + sizeof(desc->req.fcw_ld)); rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif From patchwork Fri Oct 21 05:20:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118853 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A97CDA0552; Thu, 20 Oct 2022 23:26:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AFD7E42BEF; Thu, 20 Oct 2022 23:24:52 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id DA09142B78 for ; Thu, 20 Oct 2022 23:24:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301080; x=1697837080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ea7/brtC/pdMWnnU2uTjlsDRla7nUERS0JR0g0SWQeY=; b=hGtPtsJK5oYUpYhPhdxSlKZS18Gb4xDtiJPbbK8vaj9Eafcrv7pfJ7rt k+tHyToOOo8NtsR6Bhr0h/87Nm+fjDxTHncWELH2yjyUjDK11IIhrXmNX DT7JAnEr++t7Mu0JEzoJg2pkPpnEYegKkieF5k9Be12iCnBifQ0YuFSQ6 /zSz8CziCQV3/lM38Y1vULJJ7Tf41oKSL5U3dB6N01Ohme/TCxDiO3UXF xeKObkesrZEq+2siJ3RuAqTIRpUQMcT9qFuFb4MWd+BJ2JKYYmF609K7/ Hsp3IAn1Cq+Fb0LgEI9GS1hjJiOtp8kjvuuiKx9n+A+z3MulkAcC5/Oe2 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887489" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887489" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396879" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396879" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 15/29] baseband/acc100: add enqueue status Date: Thu, 20 Oct 2022 22:20:48 -0700 Message-Id: <20221021052102.107141-16-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add enqueue status as part of rte_bbdev_queue_data. This is a new feature to update queue status and indicate the reason why a previous enqueue may or may not have consumed all requested operations. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 56 ++++++++++++++++++++------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 2896bc0c5e..19aa8db143 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2969,13 +2969,17 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail - 1 < 0)) + if (unlikely(avail - 1 < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; ret = enqueue_enc_one_op_cb(q, ops[i], i); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3007,20 +3011,26 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, int16_t enq, left = num; while (left > 0) { - if (unlikely(avail < 1)) + if (unlikely(avail < 1)) { + acc_enqueue_ring_full(q_data); break; + } avail--; enq = RTE_MIN(left, ACC_MUX_5GDL_DESC); if (check_mux(&ops[i], enq)) { ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i], desc_idx, enq); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } i += enq; } else { ret = enqueue_ldpc_enc_one_op_cb(q, ops[i], desc_idx); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } i++; } desc_idx++; @@ -3058,13 +3068,17 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { cbs_in_tb = get_num_cbs_in_tb_enc(&ops[i]->turbo_enc); /* Check if there are available space for further processing */ - if (unlikely(avail - cbs_in_tb < 0)) + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= cbs_in_tb; ret = enqueue_enc_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } if (unlikely(enqueued_cbs == 0)) @@ -3121,13 +3135,17 @@ acc100_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail - 1 < 0)) + if (unlikely(avail - 1 < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; ret = enqueue_dec_one_op_cb(q, ops[i], i); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3167,8 +3185,10 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, ret = enqueue_ldpc_dec_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } if (unlikely(enqueued_cbs == 0)) @@ -3195,8 +3215,10 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, bool same_op = false; for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail < 1)) + if (unlikely(avail < 1)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; if (i > 0) @@ -3209,8 +3231,10 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3245,13 +3269,17 @@ acc100_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { cbs_in_tb = get_num_cbs_in_tb_dec(&ops[i]->turbo_dec); /* Check if there are available space for further processing */ - if (unlikely(avail - cbs_in_tb < 0)) + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= cbs_in_tb; ret = enqueue_dec_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } From patchwork Fri Oct 21 05:20:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118855 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8BA61A0552; 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a="368887492" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887492" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396886" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396886" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 16/29] baseband/acc100: add scatter-gather support Date: Thu, 20 Oct 2022 22:20:49 -0700 Message-Id: <20221021052102.107141-17-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add flag to support scatter-gather for the mbuf Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 38 ++++++++++++++++++--------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 19aa8db143..bf7383afc7 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1364,6 +1364,8 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, * Store information about device capabilities * @param next_triplet * Index for ACC100 DMA Descriptor triplet + * @param scattergather + * Flag to support scatter-gather for the mbuf * * @return * Returns index of next triplet on success, other value if lengths of @@ -1373,12 +1375,16 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, static inline int acc100_dma_fill_blk_type_in(struct acc_dma_req_desc *desc, struct rte_mbuf **input, uint32_t *offset, uint32_t cb_len, - uint32_t *seg_total_left, int next_triplet) + uint32_t *seg_total_left, int next_triplet, + bool scattergather) { uint32_t part_len; struct rte_mbuf *m = *input; - part_len = (*seg_total_left < cb_len) ? *seg_total_left : cb_len; + if (scattergather) + part_len = (*seg_total_left < cb_len) ? *seg_total_left : cb_len; + else + part_len = cb_len; cb_len -= part_len; *seg_total_left -= part_len; @@ -1469,7 +1475,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet, false); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1557,7 +1563,9 @@ acc100_dma_desc_td_fill(struct rte_bbdev_dec_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, kw, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1659,7 +1667,9 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, input_length, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, @@ -2727,10 +2737,9 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); - /* Special handling when overusing mbuf */ - if (fcw->rm_e < ACC_MAX_E_MBUF) - seg_total_left = rte_pktmbuf_data_len(input) - - in_offset; + /* Special handling when using mbuf or not */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; else seg_total_left = fcw->rm_e; @@ -2805,9 +2814,10 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, r = op->ldpc_dec.tb_params.r; while (mbuf_total_left > 0 && r < c) { - - seg_total_left = rte_pktmbuf_data_len(input) - in_offset; - + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; + else + seg_total_left = op->ldpc_dec.input.length; /* Set up DMA descriptor */ desc = acc_desc(q, total_enqueued_cbs); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; @@ -2832,7 +2842,9 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif - if (seg_total_left == 0) { + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER) + && (seg_total_left == 0)) { /* Go to the next mbuf */ input = input->next; in_offset = 0; From patchwork Fri Oct 21 05:20:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118854 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0557DA0552; Thu, 20 Oct 2022 23:26:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8139742C00; 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20 Oct 2022 14:24:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396892" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396892" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:37 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 17/29] baseband/acc100: add HARQ index helper function Date: Thu, 20 Oct 2022 22:20:50 -0700 Message-Id: <20221021052102.107141-18-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor code to use the HARQ index helper function and make harq_idx uint32. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++-------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index bf7383afc7..f0cd8ada80 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1051,7 +1051,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, union acc_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; - uint16_t harq_index; + uint32_t harq_index; uint32_t l; bool harq_prun = false; uint32_t max_hc_in; @@ -1099,8 +1099,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); - harq_index = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ harq_prun = ((op->ldpc_dec.harq_combined_output.offset % @@ -1778,20 +1777,17 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, *h_out_length = desc->data_ptrs[next_triplet].blen; next_triplet++; - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { - desc->data_ptrs[next_triplet].address = - op->ldpc_dec.harq_combined_output.offset; + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + struct rte_bbdev_dec_op *prev_op; + uint32_t harq_idx, prev_harq_idx; + desc->data_ptrs[next_triplet].address = op->ldpc_dec.harq_combined_output.offset; /* Adjust based on previous operation */ - struct rte_bbdev_dec_op *prev_op = desc->op_addr; + prev_op = desc->op_addr; op->ldpc_dec.harq_combined_output.length = prev_op->ldpc_dec.harq_combined_output.length; - int16_t hq_idx = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; - int16_t prev_hq_idx = - prev_op->ldpc_dec.harq_combined_output.offset - / ACC_HARQ_OFFSET; - harq_layout[hq_idx].val = harq_layout[prev_hq_idx].val; + harq_idx = hq_index(op->ldpc_dec.harq_combined_output.offset); + prev_harq_idx = hq_index(prev_op->ldpc_dec.harq_combined_output.offset); + harq_layout[harq_idx].val = harq_layout[prev_harq_idx].val; #ifndef ACC100_EXT_MEM struct rte_bbdev_op_data ho = op->ldpc_dec.harq_combined_output; @@ -2535,6 +2531,9 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *hq_output_head, *hq_output; uint16_t harq_dma_length_in, harq_dma_length_out; uint16_t harq_in_length = op->ldpc_dec.harq_combined_input.length; + bool ddr_mem_in; + union acc_harq_layout_data *harq_layout; + uint32_t harq_index; if (harq_in_length == 0) { rte_bbdev_log(ERR, "Loopback of invalid null size\n"); @@ -2554,13 +2553,12 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, } harq_dma_length_out = harq_dma_length_in; - bool ddr_mem_in = check_bit(op->ldpc_dec.op_flags, + ddr_mem_in = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE); - union acc_harq_layout_data *harq_layout = q->d->harq_layout; - uint16_t harq_index = (ddr_mem_in ? + harq_layout = q->d->harq_layout; + harq_index = hq_index(ddr_mem_in ? op->ldpc_dec.harq_combined_input.offset : - op->ldpc_dec.harq_combined_output.offset) - / ACC_HARQ_OFFSET; + op->ldpc_dec.harq_combined_output.offset); desc = acc_desc(q, total_enqueued_cbs); fcw = &desc->req.fcw_ld; From patchwork Fri Oct 21 05:20:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118856 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 767FBA0552; Thu, 20 Oct 2022 23:26:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1876342C05; Thu, 20 Oct 2022 23:24:55 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A307342B80 for ; Thu, 20 Oct 2022 23:24:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301080; x=1697837080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T9QSzboniMma2aed0lqU/ZFa7cAJYJtdmchbAEJ0UJA=; b=LLVyMnSTg0Hu4T/Ii7lP6D3WfQiPnTCPBxmrsxWo2ffjDHWjUfTf6M+L Sp2zd7e3Qg8jS1Wi/cqJD3FSv7AB9OuMxdXdwJto0Ni5xhYX2VQSQyRbL hixFCbcKe9lVH350ZxQUvaFn/Js3fql3EUuSXjW1HyL/E9VSeM5JEjUKV bUTVPDKiW1EPhG1Qi7WPZwrGD/m4RhCpY6uLp0xiLTAI5RWJ870scRMTy bfs2nhF3kh3mW7sitXB9e/wwCEppo/TNcj0/nAzcMu52vHY4NOSCToqXa ybL3fm5UYz68+mEY4Y1MHyheQGa2NIHavlLrdHdyvzMMG9hgE0oHrwgha w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887495" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887495" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396896" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396896" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:37 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 18/29] baseband/acc100: enable input validation by default Date: Thu, 20 Oct 2022 22:20:51 -0700 Message-Id: <20221021052102.107141-19-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable validation functions by default and provide a new flag RTE_LIBRTE_SKIP_VALIDATE if the user wants to run without validating input to save cycles. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- doc/guides/bbdevs/acc100.rst | 7 +++++ drivers/baseband/acc/rte_acc100_pmd.c | 38 +++++++++++++-------------- 2 files changed, 26 insertions(+), 19 deletions(-) diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst index 8b29b92a9d..db46023044 100644 --- a/doc/guides/bbdevs/acc100.rst +++ b/doc/guides/bbdevs/acc100.rst @@ -65,6 +65,13 @@ ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities: - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity +* PMD Specific build flags: + The ACC100 PMD includes some optional build flags which may be used for troubleshooting. + Recommended build configuration is for these to be kept as default. + - ``RTE_LIBRTE_BBDEV_SKIP_VALIDATE`` : option to skip API input validation. + Recommended value is to keep the validation enable by default as a protection for negative + scenarios at a cost of some cycles spent to enforce these checks. + Installation ------------ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index f0cd8ada80..5cbd417199 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1037,7 +1037,7 @@ is_acc100(struct acc_queue *q) return (q->d->device_variant == ACC100_VARIANT); } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE static inline bool validate_op_required(struct acc_queue *q) { @@ -1801,7 +1801,7 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, desc->op_addr = op; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo encoder parameters */ static inline int validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) @@ -2064,10 +2064,10 @@ enqueue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2116,10 +2116,10 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, uint16_t in_length_in_bytes; struct rte_bbdev_op_ldpc_enc *enc = &ops[0]->ldpc_enc; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_enc_op(ops[0], q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2176,10 +2176,10 @@ enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2232,10 +2232,10 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_idx, current_enqueued_cbs = 0; uint64_t fcw_offset; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2306,7 +2306,7 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) @@ -2464,10 +2464,10 @@ enqueue_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *input, *h_output_head, *h_output, *s_output_head, *s_output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif @@ -2687,10 +2687,10 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, return ret; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -2788,10 +2788,10 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint64_t fcw_offset; union acc_harq_layout_data *harq_layout; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -2880,10 +2880,10 @@ enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint16_t desc_idx, current_enqueued_cbs = 0; uint64_t fcw_offset; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif From patchwork Fri Oct 21 05:20:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118858 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82BF4A0552; Thu, 20 Oct 2022 23:26:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0EF2342BDE; Thu, 20 Oct 2022 23:25:03 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 088ED42836 for ; Thu, 20 Oct 2022 23:24:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301081; x=1697837081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=txCFnXhQvFnbX2fEn/kMxBvEc2oftxE0MX2DllOYy30=; b=agjD/3HBwEC+D2u+DaMKlmV7Oc9kDHUKylFn3J3nnvmuFNFWQ7RPmk0s yCjfOudU165UMNyjybq743js+uf2P51iim4+lfM0ZLcF3reFS3reIlojS 1nbGXi8vNvd5plA6/lk3ih2aLpzLSzW9HFOVd4k3Yf2gzU3hKx0GXr/ER FlxmeIJQBYg2WtOyYV6vTCUguhL3R6tulLYg1ZZQtb+dYSIqgLzhjvxOR WUCSgnc7n2edMjz7EoGUjZB2BE4RN3LScEK4kEt1u2i2tQ9GjCOMyVTKY Wva1ud7eemmSZU+F/PKUlB9fJYmRQekDUWOFlVuoPreCJDqZ59hD+BWj0 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887496" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887496" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396901" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396901" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 19/29] baseband/acc100: added LDPC transport block support Date: Thu, 20 Oct 2022 22:20:52 -0700 Message-Id: <20221021052102.107141-20-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added LDPC enqueue functions to handle transport blocks. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 164 +++++++++++++++++++++++++- 1 file changed, 163 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 5cbd417199..4c890b28f1 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2165,6 +2165,56 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, return num; } +/* Enqueue one encode operations for ACC100 device for a partial TB + * all codes blocks have same configuration multiplexed on the same descriptor. + */ +static inline void +enqueue_ldpc_enc_part_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, + uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e, + uint16_t in_len_bytes, uint32_t out_len_bytes, uint32_t *in_offset, + uint32_t *out_offset) +{ + union acc_dma_desc *desc = NULL; + struct rte_mbuf *output_head, *output; + int i, next_triplet; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) & q->sw_ring_wrap_mask); + + desc = q->ring_addr + desc_idx; + acc_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e); + + /* This could be done at polling. */ + acc_header_init(&desc->req); + desc->req.numCBs = num_cbs; + + desc->req.m2dlen = 1 + num_cbs; + desc->req.d2mlen = num_cbs; + next_triplet = 1; + + for (i = 0; i < num_cbs; i++) { + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->input.data, *in_offset); + *in_offset += in_len_bytes; + desc->req.data_ptrs[next_triplet].blen = in_len_bytes; + next_triplet++; + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->output.data, *out_offset); + *out_offset += out_len_bytes; + desc->req.data_ptrs[next_triplet].blen = out_len_bytes; + next_triplet++; + enc->output.length += out_len_bytes; + output_head = output = enc->output.data; + mbuf_append(output_head, output, out_len_bytes); + } + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + rte_memdump(stderr, "FCW", &desc->req.fcw_le, + sizeof(desc->req.fcw_le) - 8); + rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); +#endif + +} + /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, @@ -2306,6 +2356,76 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } +/* Enqueue one encode operations for ACC100 device in TB mode. + * returns the number of descs used. + */ +static inline int +enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, + uint16_t enq_descs, uint8_t cbs_in_tb) +{ +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE + if (validate_ldpc_enc_op(op, q) == -1) { + rte_bbdev_log(ERR, "LDPC encoder validation failed"); + return -EINVAL; + } +#endif + uint8_t num_a, num_b; + uint16_t desc_idx; + uint8_t r = op->ldpc_enc.tb_params.r; + uint8_t cab = op->ldpc_enc.tb_params.cab; + union acc_dma_desc *desc; + uint16_t init_enq_descs = enq_descs; + uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) * + op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3; + uint32_t in_offset = 0, out_offset = 0; + uint16_t return_descs; + + if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + input_len_B -= 3; + + if (r < cab) { + num_a = cab - r; + num_b = cbs_in_tb - cab; + } else { + num_a = 0; + num_b = cbs_in_tb - r; + } + + while (num_a > 0) { + uint32_t e = op->ldpc_enc.tb_params.ea; + uint32_t out_len_bytes = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_a, ACC_MUX_5GDL_DESC); + num_a -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_bytes, &in_offset, &out_offset); + enq_descs++; + } + while (num_b > 0) { + uint32_t e = op->ldpc_enc.tb_params.eb; + uint32_t out_len_bytes = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_b, ACC_MUX_5GDL_DESC); + num_b -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_bytes, &in_offset, &out_offset); + enq_descs++; + } + + return_descs = enq_descs - init_enq_descs; + /* Keep total number of CBs in first TB. */ + desc_idx = ((q->sw_ring_head + init_enq_descs) & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors. */ + desc->req.op_addr = op; + + /* Set SDone on last CB descriptor for TB mode. */ + desc_idx = ((q->sw_ring_head + enq_descs - 1) & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.sdone_enable = 1; + desc->req.irq_enable = q->irq_enable; + desc->req.op_addr = op; + return return_descs; +} + #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int @@ -2882,6 +3002,10 @@ enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ + if (cbs_in_tb == 0) { + rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs"); + return -EINVAL; + } if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; @@ -3103,6 +3227,44 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, return i; } +/* Enqueue LDPC encode operations for ACC100 device in TB mode. */ +static uint16_t +acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + struct acc_queue *q = q_data->queue_private; + int32_t avail = acc_ring_avail_enq(q); + uint16_t i, enqueued_descs = 0; + uint8_t cbs_in_tb; + int descs_used; + + for (i = 0; i < num; ++i) { + cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc); + /* Check if there are available space for further processing. */ + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); + break; + } + descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i], enqueued_descs, cbs_in_tb); + if (descs_used < 0) { + acc_enqueue_invalid(q_data); + break; + } + enqueued_descs += descs_used; + avail -= descs_used; + } + if (unlikely(enqueued_descs == 0)) + return 0; /* Nothing to enqueue. */ + + acc_dma_enqueue(q, enqueued_descs, &q_data->queue_stats); + + /* Update stats. */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + /* Enqueue encode operations for ACC100 device. */ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, @@ -3126,7 +3288,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - return acc100_enqueue_enc_tb(q_data, ops, num); + return acc100_enqueue_ldpc_enc_tb(q_data, ops, num); else return acc100_enqueue_ldpc_enc_cb(q_data, ops, num); } From patchwork Fri Oct 21 05:20:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118857 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE52BA0552; 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a="368887497" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887497" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396905" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396905" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 20/29] baseband/acc100: update validate LDPC enc/dec Date: Thu, 20 Oct 2022 22:20:53 -0700 Message-Id: <20221021052102.107141-21-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update validate functions to check for valid LDPC parameters to avoid any HW issues. Adding protection for null corner case and for HARQ inbound size out of range. HARQ input size from application may be invalid and causing HW issue. Add checks to ensure that if HARQ is invalid, set to some valid size to ensure HW issues do not occur. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- doc/guides/bbdevs/acc100.rst | 2 + drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc100_pmd.c | 285 +++++++++++++++++++++++--- 3 files changed, 257 insertions(+), 31 deletions(-) diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst index db46023044..6c7025e019 100644 --- a/doc/guides/bbdevs/acc100.rst +++ b/doc/guides/bbdevs/acc100.rst @@ -71,6 +71,8 @@ ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities: - ``RTE_LIBRTE_BBDEV_SKIP_VALIDATE`` : option to skip API input validation. Recommended value is to keep the validation enable by default as a protection for negative scenarios at a cost of some cycles spent to enforce these checks. + - ``ACC100_EXT_MEM`` : default option with memory external to CPU on the PCie card DDR itself. + Alternative build option will use CPU memory (not recommended). Installation ------------ diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 97d10b8b40..eae7eab4e9 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -121,6 +121,7 @@ #define ACC_ALGO_SPA 0 #define ACC_ALGO_MSA 1 #define ACC_HARQ_ALIGN_64B 64 +#define ACC_MAX_ZC 384 /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 4c890b28f1..383f71b6be 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1954,14 +1954,11 @@ static inline int validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) { struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; + int K, N, q_m, crc24; if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); - return -1; - } if (ldpc_enc->input.data == NULL) { rte_bbdev_log(ERR, "Invalid input pointer"); return -1; @@ -1970,17 +1967,12 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) rte_bbdev_log(ERR, "Invalid output pointer"); return -1; } - if (ldpc_enc->input.length > - RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { - rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", - ldpc_enc->input.length, - RTE_BBDEV_LDPC_MAX_CB_SIZE); + if (ldpc_enc->input.length == 0) { + rte_bbdev_log(ERR, "CB size (%u) is null", ldpc_enc->input.length); return -1; } if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) { - rte_bbdev_log(ERR, - "BG (%u) is out of range 1 <= value <= 2", - ldpc_enc->basegraph); + rte_bbdev_log(ERR, "BG (%u) is out of range 1 <= value <= 2", ldpc_enc->basegraph); return -1; } if (ldpc_enc->rv_index > 3) { @@ -1995,13 +1987,89 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) ldpc_enc->code_block_mode); return -1; } - int K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; - if (ldpc_enc->n_filler >= K) { - rte_bbdev_log(ERR, - "K and F are not compatible %u %u", - K, ldpc_enc->n_filler); + if (ldpc_enc->z_c > ACC_MAX_ZC) { + rte_bbdev_log(ERR, "Zc (%u) is out of range", ldpc_enc->z_c); + return -1; + } + + K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; + N = (ldpc_enc->basegraph == 1 ? ACC_N_ZC_1 : ACC_N_ZC_2) * ldpc_enc->z_c; + q_m = ldpc_enc->q_m; + crc24 = 0; + + if (check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24A_ATTACH) || + check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + crc24 = 24; + if ((K - ldpc_enc->n_filler) % 8 > 0) { + rte_bbdev_log(ERR, "K - F not byte aligned %u", K - ldpc_enc->n_filler); + return -1; + } + if (ldpc_enc->n_filler > (K - 2 * ldpc_enc->z_c)) { + rte_bbdev_log(ERR, "K - F invalid %u %u", K, ldpc_enc->n_filler); + return -1; + } + if ((ldpc_enc->n_cb > N) || (ldpc_enc->n_cb <= K)) { + rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", ldpc_enc->n_cb, K, N); return -1; } + if (!check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && + ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, "Qm (%u) is out of range", ldpc_enc->q_m); + return -1; + } + if (ldpc_enc->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_enc->cb_params.e == 0) { + rte_bbdev_log(ERR, "E is null"); + return -1; + } + if (q_m > 0) { + if (ldpc_enc->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (ldpc_enc->cb_params.e > 3456)) { + rte_bbdev_log(ERR, "E too large for small block"); + return -1; + } + if (ldpc_enc->input.length > + RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { + rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", + ldpc_enc->input.length, + RTE_BBDEV_LDPC_MAX_CB_SIZE); + return -1; + } + if (K < (int) (ldpc_enc->input.length * 8 + ldpc_enc->n_filler) + crc24) { + rte_bbdev_log(ERR, + "K and F not matching input size %u %u %u", + K, ldpc_enc->n_filler, + ldpc_enc->input.length); + return -1; + } + } else { + if ((ldpc_enc->tb_params.c == 0) || + (ldpc_enc->tb_params.ea == 0) || + (ldpc_enc->tb_params.eb == 0)) { + rte_bbdev_log(ERR, "TB parameter is null"); + return -1; + } + if (q_m > 0) { + if ((ldpc_enc->tb_params.ea % q_m > 0) || + (ldpc_enc->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (RTE_MAX(ldpc_enc->tb_params.ea, + ldpc_enc->tb_params.eb) > 3456)) { + rte_bbdev_log(ERR, "E too large for small block"); + return -1; + } + } return 0; } @@ -2010,24 +2078,30 @@ static inline int validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) { struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; + int K, N, q_m; + uint32_t min_harq_input; if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); + if (ldpc_dec->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (ldpc_dec->hard_output.data == NULL) { + rte_bbdev_log(ERR, "Invalid output pointer"); + return -1; + } + if (ldpc_dec->input.length == 0) { + rte_bbdev_log(ERR, "input is null"); return -1; } if ((ldpc_dec->basegraph > 2) || (ldpc_dec->basegraph == 0)) { - rte_bbdev_log(ERR, - "BG (%u) is out of range 1 <= value <= 2", - ldpc_dec->basegraph); + rte_bbdev_log(ERR, "BG (%u) is out of range 1 <= value <= 2", ldpc_dec->basegraph); return -1; } if (ldpc_dec->iter_max == 0) { - rte_bbdev_log(ERR, - "iter_max (%u) is equal to 0", - ldpc_dec->iter_max); + rte_bbdev_log(ERR, "iter_max (%u) is equal to 0", ldpc_dec->iter_max); return -1; } if (ldpc_dec->rv_index > 3) { @@ -2042,13 +2116,162 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) ldpc_dec->code_block_mode); return -1; } - int K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; - if (ldpc_dec->n_filler >= K) { - rte_bbdev_log(ERR, - "K and F are not compatible %u %u", - K, ldpc_dec->n_filler); + /* Check Zc is valid value. */ + if ((ldpc_dec->z_c > ACC_MAX_ZC) || (ldpc_dec->z_c < 2)) { + rte_bbdev_log(ERR, "Zc (%u) is out of range", ldpc_dec->z_c); + return -1; + } + if (ldpc_dec->z_c > 256) { + if ((ldpc_dec->z_c % 32) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 128) { + if ((ldpc_dec->z_c % 16) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 64) { + if ((ldpc_dec->z_c % 8) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 32) { + if ((ldpc_dec->z_c % 4) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 16) { + if ((ldpc_dec->z_c % 2) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } + + K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; + N = (ldpc_dec->basegraph == 1 ? ACC_N_ZC_1 : ACC_N_ZC_2) * ldpc_dec->z_c; + q_m = ldpc_dec->q_m; + + if (ldpc_dec->n_filler >= K - 2 * ldpc_dec->z_c) { + rte_bbdev_log(ERR, "K and F are not compatible %u %u", K, ldpc_dec->n_filler); + return -1; + } + if ((ldpc_dec->n_cb > N) || (ldpc_dec->n_cb <= K)) { + rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", ldpc_dec->n_cb, K, N); + return -1; + } + if (((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, "Qm (%u) is out of range", ldpc_dec->q_m); + return -1; + } + if (ldpc_dec->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_dec->cb_params.e == 0) { + rte_bbdev_log(ERR, "E is null"); + return -1; + } + if (ldpc_dec->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + if (ldpc_dec->cb_params.e > 512 * ldpc_dec->z_c) { + rte_bbdev_log(ERR, "E too high"); + return -1; + } + } else { + if ((ldpc_dec->tb_params.c == 0) || + (ldpc_dec->tb_params.ea == 0) || + (ldpc_dec->tb_params.eb == 0)) { + rte_bbdev_log(ERR, "TB parameter is null"); + return -1; + } + if ((ldpc_dec->tb_params.ea % q_m > 0) || + (ldpc_dec->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + if ((ldpc_dec->tb_params.ea > 512 * ldpc_dec->z_c) || + (ldpc_dec->tb_params.eb > 512 * ldpc_dec->z_c)) { + rte_bbdev_log(ERR, "E too high"); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DECODE_BYPASS)) { + rte_bbdev_log(ERR, "Avoid LDPC Decode bypass"); + return -1; + } + + /* Avoid HARQ compression for small block size */ + if ((check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) && (K < 2048)) + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; + + min_harq_input = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION) ? 256 : 64; + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + ldpc_dec->harq_combined_input.length < + min_harq_input) { + rte_bbdev_log(ERR, "HARQ input size is too small %d < %d", + ldpc_dec->harq_combined_input.length, + min_harq_input); return -1; } + + /* Enforce in-range HARQ input size */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + uint32_t max_harq_input = RTE_ALIGN_CEIL(ldpc_dec->n_cb - ldpc_dec->n_filler, 64); + + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) + max_harq_input = max_harq_input * 3 / 4; + + if (ldpc_dec->harq_combined_input.length > max_harq_input) { + rte_bbdev_log(ERR, + "HARQ input size out of range %d > %d, Ncb %d F %d K %d N %d", + ldpc_dec->harq_combined_input.length, + max_harq_input, ldpc_dec->n_cb, + ldpc_dec->n_filler, K, N); + /* Fallback to flush HARQ combine */ + ldpc_dec->harq_combined_input.length = 0; + + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + } + +#ifdef ACC100_EXT_MEM + /* Enforce in-range HARQ offset */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + if ((op->ldpc_dec.harq_combined_input.offset >> 10) >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQin offset out of range %d > %d", + op->ldpc_dec.harq_combined_input.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_input.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQin offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_input.offset); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + if ((op->ldpc_dec.harq_combined_output.offset >> 10) >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQout offset out of range %d > %d", + op->ldpc_dec.harq_combined_output.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_output.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQout offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_output.offset); + return -1; + } + } +#endif + return 0; } #endif @@ -2686,7 +2909,7 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, memset(fcw, 0, sizeof(struct acc_fcw_ld)); fcw->FCWversion = ACC_FCW_VER; fcw->qm = 2; - fcw->Zc = 384; + fcw->Zc = ACC_MAX_ZC; if (harq_in_length < 16 * ACC_N_ZC_1) fcw->Zc = 16; fcw->ncb = fcw->Zc * ACC_N_ZC_1; From patchwork Fri Oct 21 05:20:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118859 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA15FA0552; Thu, 20 Oct 2022 23:26:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE45542BF3; Thu, 20 Oct 2022 23:25:03 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 7118B42B80 for ; Thu, 20 Oct 2022 23:24:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301081; x=1697837081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cLFzepQQinEyzBqDQqsMJ2Z/+5Y4dFwDbUPOU/+mM2M=; b=Hg3tHZ/NgUu7BqqVSrT3ONdzTyBKHP5JzfWqsY6a54iZfvx50Mttk24v IhXUcPQedC2w/F8kbhhb9y1E+rcpzDEURXGR4GNfGuDdCrFJ+ULwaxDu4 1kszj9DbGebeZwlNIwZVSnxBs2vSIbX8pAKngrRd6wl6aDNiejLAj2EL8 1Fyux8UdJR8oAIuMg4xYlPjcOg0+Tdb+uQjIza9PJ9SA1NhbFE/0WT1Fh oNjLfQCvsS9UfaUIAbPvl2zTFVKZRUI4pHNMUOyDQp9JHsces9m840uoG 4qo97nchswp/NlP5Y5Ew1qdEwIwyJ3G7sgrS1Whctgs5t1HaDFOwNb+W9 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887499" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887499" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396909" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396909" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 21/29] baseband/acc100: implement configurable queue depth Date: Thu, 20 Oct 2022 22:20:54 -0700 Message-Id: <20221021052102.107141-22-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to make queue depth configurable based on decode or encode mode. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 383f71b6be..983290e8c1 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -776,9 +776,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; - q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ? - (1 << d->acc_conf.q_ul_4g.aq_depth_log2) : - (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + q->aq_depth = 0; + if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_5g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2); q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, queue_offset(d->pf_device, From patchwork Fri Oct 21 05:20:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118861 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E26A3A0552; Thu, 20 Oct 2022 23:27:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E60342C11; Thu, 20 Oct 2022 23:25:05 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id E4E0042836 for ; Thu, 20 Oct 2022 23:24:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301082; x=1697837082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kfm8WNEpM6slmxvZPRJBz5P76GzQ1jD6Yz+GDZbYCs4=; b=ZIVnpxrrwh06RTm3KsyIDJ7/dLwDgkH552YtlaEJsyEah9YaskUvqg5j hnkItRkBx+ImwIpsXAlERe97F9QzCCUXapc9jkvnsZWspDht/xuIeDPMD D0ev7N/D+KOsQuTsahgIoR/PsLjRxeb3gFWUSO2nwDySj0zkZNTNtLcyQ zJR92PpWFohk595yNyhj/Kh/XOxG1HFFWTM2Tp4YAxxOTh/hWnitaYc8I RSkCtna9Qocl/J/Gzbn2OX2lJmr1/MZlYdzghBstCAFs80gwwxKpSaQuL obdChlrDVNhhxWymC7sY9qXltGgZix/l01WITSz9pyL5DBaGYD2+E9uqH Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887500" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887500" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396913" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396913" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 22/29] baseband/acc100: add queue stop operation Date: Thu, 20 Oct 2022 22:20:55 -0700 Message-Id: <20221021052102.107141-23-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to stop queue operation. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 983290e8c1..aa019e3248 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -799,6 +799,65 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return 0; } +static inline void +acc100_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type, + uint16_t index) +{ + if (op == NULL) + return; + if (op_type == RTE_BBDEV_OP_LDPC_DEC) + rte_bbdev_log(DEBUG, + " Op 5GUL %d %d %d %d %d %d %d %d %d %d %d %d", + index, + op->ldpc_dec.basegraph, op->ldpc_dec.z_c, + op->ldpc_dec.n_cb, op->ldpc_dec.q_m, + op->ldpc_dec.n_filler, op->ldpc_dec.cb_params.e, + op->ldpc_dec.op_flags, op->ldpc_dec.rv_index, + op->ldpc_dec.iter_max, op->ldpc_dec.iter_count, + op->ldpc_dec.harq_combined_input.length + ); + else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { + struct rte_bbdev_enc_op *op_dl = (struct rte_bbdev_enc_op *) op; + rte_bbdev_log(DEBUG, + " Op 5GDL %d %d %d %d %d %d %d %d %d", + index, + op_dl->ldpc_enc.basegraph, op_dl->ldpc_enc.z_c, + op_dl->ldpc_enc.n_cb, op_dl->ldpc_enc.q_m, + op_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e, + op_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index + ); + } +} + +static int +acc100_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct acc_queue *q; + struct rte_bbdev_dec_op *op; + uint16_t i; + + q = dev->data->queues[queue_id].queue_private; + rte_bbdev_log(INFO, "Queue Stop %d H/T/D %d %d %x OpType %d", + queue_id, q->sw_ring_head, q->sw_ring_tail, + q->sw_ring_depth, q->op_type); + for (i = 0; i < q->sw_ring_depth; ++i) { + op = (q->ring_addr + i)->req.op_addr; + acc100_print_op(op, q->op_type, i); + } + /* ignore all operations in flight and clear counters */ + q->sw_ring_tail = q->sw_ring_head; + q->aq_enqueued = 0; + q->aq_dequeued = 0; + dev->data->queues[queue_id].queue_stats.enqueued_count = 0; + dev->data->queues[queue_id].queue_stats.dequeued_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_err_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_err_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_warn_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_warn_count = 0; + + return 0; +} + /* Release ACC100 queue */ static int acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) @@ -991,6 +1050,7 @@ static const struct rte_bbdev_ops acc100_bbdev_ops = { .info_get = acc100_dev_info_get, .queue_setup = acc100_queue_setup, .queue_release = acc100_queue_release, + .queue_stop = acc100_queue_stop, .queue_intr_enable = acc100_queue_intr_enable, .queue_intr_disable = acc100_queue_intr_disable }; From patchwork Fri Oct 21 05:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118860 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 037E0A0552; Thu, 20 Oct 2022 23:26:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6AA642C08; Thu, 20 Oct 2022 23:25:04 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id F40D742B6D for ; Thu, 20 Oct 2022 23:24:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301082; x=1697837082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=utggVSfF3YHAtgXz+nnewm3Fb9pMBnWKCVZLgdzsWFI=; b=G/GqoivsVfvJng2YYKVgZQGSS+bkQcNg3sGwFKpiWbWIRZ+gKD0daZ3k /RhaunvcOC7twcXk0eFI9mAvY5ZjQj0cSGNW95O89AliZsrJtM+bb6plr BE2JIt/wFbKEGF+Oz6Gzn6wuFybC5eG8izHouzW/6n4U0VOHEFCA4D4pP 7MCdbP76tRMHwzEWK4ZSooehnOT/d7PX8Bq71oOl9hgfRXvgVXvrNowkU QxzTya7yYQYytX61fKsvBNYu83mgtzcLBbP4uJiogbs3VhcNkDx2v2mY8 pf6XBTw5zbpxNjZtSz+h14aYOtTu1CDPU0B0+UnXtdA/7HzIG1xiDBeHn w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887502" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887502" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396918" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396918" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 23/29] baseband/acc100: update uplink CB input length Date: Thu, 20 Oct 2022 22:20:56 -0700 Message-Id: <20221021052102.107141-24-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use the FCW E parameter for rate matching as the code block input length. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index aa019e3248..8e804eb3a4 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1714,7 +1714,7 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, crc24_overlap = 24; /* Compute some LDPC BG lengths */ - input_length = dec->cb_params.e; + input_length = fcw->rm_e; if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION)) input_length = (input_length * 3 + 3) / 4; From patchwork Fri Oct 21 05:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118862 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58AF8A0552; Thu, 20 Oct 2022 23:27:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2F99542C15; Thu, 20 Oct 2022 23:25:06 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 28C4C42B79 for ; Thu, 20 Oct 2022 23:24:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301083; x=1697837083; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cCHzhNk6lg+Nla4i5Ix7y7CuEyeKgf1rJ9bJY7DYALs=; b=HosTPFnZ9rZSZjFZVdAWWHNRd2ywgep7cKpIGyNSQSqvi8nJsdnr0v04 w/pL8XocrGIqoA9Yk8/UujfrBkihCa/kB2iq8Blfq0QjFzoYXr/J25fTO opwkl2R5t+KW2jwF6tOU06hNKcZZXCEjgUn18Io1f5Uz//JE7CqpwuOa4 OsJfvZXBOuIdVw5FDuc2VV8J+f5phU7EL2z95E90YVnGeEB1QJTDKXUdn K5G+SbiNiayYv470IkPcxSj/EJQsI/VXanNl/nwKXGkDW/jN0MLIQK9vr ibCO9PNO5OIdjFC8LK1cGf6TccoXMxM+TT0vbBWxlP0bzEH7O2XzkBu+Y w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887517" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887517" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396933" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396933" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:40 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 24/29] baseband/acc100: update log messages Date: Thu, 20 Oct 2022 22:20:57 -0700 Message-Id: <20221021052102.107141-25-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add extra values for some log messages. No functional impact. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 8e804eb3a4..3d22f642ae 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -979,6 +979,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, /* Read and save the populated config from ACC100 registers */ fetch_acc100_config(dev); + /* Check the status of device */ dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; /* Expose number of queues */ @@ -2654,7 +2655,7 @@ enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, { #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -3877,8 +3878,9 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, - rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", + desc, rsp.val, + cb_idx, cbs_in_tb); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); @@ -3974,6 +3976,7 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data, return -1; rsp.val = atom_desc.rsp.val; + rte_bbdev_log_debug("Resp. desc %p: %x\n", desc, rsp.val); /* Dequeue */ op = desc->req.op_addr; From patchwork Fri Oct 21 05:20:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118863 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2C48FA0552; Thu, 20 Oct 2022 23:27:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8C1342C1B; Thu, 20 Oct 2022 23:25:06 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id BE94842B93 for ; Thu, 20 Oct 2022 23:24:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301083; x=1697837083; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nw+JEn4osjtctOtZSqnV9ozhMIlRnTyTY7oBMazxjIQ=; b=fbCGCgqGs30lDQevKf7uJE7a4vDAv/t73zkdruZ1N8m52Urh/zqyUEY1 /fa6RcCuS7B59XtNEi4b3Ts7DcRFKSLvajFxpo/fZ4lcxkYIyu1CdzC+S 3i8UN+LhPKxJELGfVWLDRA/KDbAeUyCOVGeLnGwDrsTva4E8nHKlRXTqR e63MorMJzNwAeKRbdQmWm4PB64qzfMSS7Ft+oP8AJrOulJH5kJsWkokFp QExjWARWD38Q83BvOl+eDayoiEdMxev2/HLtzsbm9AhlZMio6x8QBJDH5 tGpIMWnG069UxwBLQWIsuetaXS07tHIMyfj3vS5D6qNtcq0x19NiIa6Bl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887519" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887519" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396937" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396937" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 25/29] baseband/acc100: store FCW from first CB descriptor Date: Thu, 20 Oct 2022 22:20:58 -0700 Message-Id: <20221021052102.107141-26-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the descriptor from the first code block from a transport block. Copy the LDPC FCW from the first descriptor into the rest of the CBs in that TB. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 3d22f642ae..0e67166744 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -3189,6 +3189,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint16_t total_enqueued_cbs, uint8_t cbs_in_tb) { union acc_dma_desc *desc = NULL; + union acc_dma_desc *desc_first = NULL; int ret; uint8_t r, c; uint32_t in_offset, h_out_offset, @@ -3208,6 +3209,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, desc_idx = acc_desc_idx(q, total_enqueued_cbs); desc = q->ring_addr + desc_idx; + desc_first = desc; fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET; harq_layout = q->d->harq_layout; q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); @@ -3230,6 +3232,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, desc = acc_desc(q, total_enqueued_cbs); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; desc->req.data_ptrs[0].blen = ACC_FCW_LD_BLEN; + rte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, ACC_FCW_LD_BLEN); ret = acc100_dma_desc_ld_fill(op, &desc->req, &input, h_output, &in_offset, &h_out_offset, &h_out_length, From patchwork Fri Oct 21 05:20:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118864 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ADEE1A0552; Thu, 20 Oct 2022 23:27:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BE43642C22; Thu, 20 Oct 2022 23:25:07 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id F168E42BA0 for ; Thu, 20 Oct 2022 23:24:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301084; x=1697837084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OLGqVdZ9GMz91g69Yu+VYXWs9c1T6e6Veae9hk77L7k=; b=ars0C0SEWDES/qF+/3pSsA7GRxCMGHpEbIej2iTQZs/hWkZybDjwjUVr I74bHNVE+jhH52yCcP03NhqAarGjcQWCZ6uiu+nB2HIUVXHUFUbIG+BQb v+cz8EQtVNyU5I8pgVIjpg41V+Q/INKjS1/E1+qWAyloM6z/FQFSaHm9N J6nVDOg/gIOT/uJQYHH4FmvEOda0QBpWkmbfMx287d0HXsFQw4ncnXeG1 e4ZpPHOJ47LCOGSHOD3N1CHA4ed4irYxez++zM5jinoijAPnMGZwvYVKT 0XuxEpY6lPm4viOcbmdttirJIZY7J67MTadRHaOlvH6ILsK+WxvmowE4e g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887523" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887523" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396941" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396941" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:43 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 26/29] baseband/acc100: update device info Date: Thu, 20 Oct 2022 22:20:59 -0700 Message-Id: <20221021052102.107141-27-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove unused capabilities, use dummy operation as start count for number of queues. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 0e67166744..d37ae986c2 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -885,7 +885,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, { struct acc_device *d = dev->data->dev_private; int i; - static const struct rte_bbdev_op_cap bbdev_capabilities[] = { { .type = RTE_BBDEV_OP_TURBO_DEC, @@ -897,7 +896,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, RTE_BBDEV_TURBO_EARLY_TERMINATION | RTE_BBDEV_TURBO_DEC_INTERRUPTS | RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | - RTE_BBDEV_TURBO_MAP_DEC | RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_DEC_CRC_24B_DROP | RTE_BBDEV_TURBO_DEC_SCATTER_GATHER, @@ -992,12 +990,13 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc_conf.q_ul_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_aqs_per_groups * d->acc_conf.q_dl_5g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_FFT] = 0; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc_conf.q_ul_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc_conf.q_dl_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc_conf.q_ul_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_qgroups; dev_info->max_num_queues = 0; - for (i = RTE_BBDEV_OP_TURBO_DEC; i <= RTE_BBDEV_OP_LDPC_ENC; i++) + for (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_LDPC_ENC; i++) dev_info->max_num_queues += dev_info->num_queues[i]; dev_info->queue_size_lim = ACC_MAX_QUEUE_DEPTH; dev_info->hardware_accelerated = true; From patchwork Fri Oct 21 05:21:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118865 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B651DA0552; Thu, 20 Oct 2022 23:27:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9835E42C26; Thu, 20 Oct 2022 23:25:08 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 62FE242BA5 for ; Thu, 20 Oct 2022 23:24:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301084; x=1697837084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D2oSXYYQ0ZK0q799K0ov39k/2V193GEvTerdMwZZXFc=; b=m6U6fQtenWVR5JYMi++axxiqV68OvPT1bJcC1Sn436TY0excTqYm9PCm dDbyXW5eWbrhPQxVOp8e5tT5iOiDZE/nBBeOf9HtJpx9ubQ4vQCA7Q74D oSImQipIpilsvmSpfLz2HvQPwDWK0bEwIKyIJkM1DPFd7cicPaZEqp4i4 12PeEZx/40ndO2jbZuB0VGdfWY6G0EGhHBahtCuKUb8ju7r4ZZjm+3+on Q8Djd7MA8ug06VmBzLP6EXs16VCRVcajPjuO6vxLIyon1wSX9a5i0KHat Axh+pbBVXiZor2nfU+NVI6S21RPQFGeET3Fr6plSGnNtlFM+tI7lCceH9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887525" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887525" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396947" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396947" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:43 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 27/29] baseband/acc100: add ring companion address Date: Thu, 20 Oct 2022 22:21:00 -0700 Message-Id: <20221021052102.107141-28-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the virtual address of companion ring as part of queue information. Use this address to calculate the op address. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 179 +++++++++++++++++--------- 1 file changed, 116 insertions(+), 63 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index d37ae986c2..23bc5d25bb 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -676,6 +676,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc_device *d = dev->data->dev_private; struct acc_queue *q; int16_t q_idx; + int ret; if (d == NULL) { rte_bbdev_log(ERR, "Undefined device"); @@ -734,8 +735,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, RTE_CACHE_LINE_SIZE, conf->socket); if (q->lb_in == NULL) { rte_bbdev_log(ERR, "Failed to allocate lb_in memory"); - rte_free(q); - return -ENOMEM; + ret = -ENOMEM; + goto free_q; } q->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in); q->lb_out = rte_zmalloc_socket(dev->device->driver->name, @@ -743,11 +744,18 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, RTE_CACHE_LINE_SIZE, conf->socket); if (q->lb_out == NULL) { rte_bbdev_log(ERR, "Failed to allocate lb_out memory"); - rte_free(q->lb_in); - rte_free(q); - return -ENOMEM; + ret = -ENOMEM; + goto free_lb_in; } q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out); + q->companion_ring_addr = rte_zmalloc_socket(dev->device->driver->name, + d->sw_ring_max_depth * sizeof(*q->companion_ring_addr), + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->companion_ring_addr == NULL) { + rte_bbdev_log(ERR, "Failed to allocate companion_ring memory"); + ret = -ENOMEM; + goto free_lb_out; + } /* * Software queue ring wraps synchronously with the HW when it reaches @@ -767,10 +775,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { - rte_free(q->lb_in); - rte_free(q->lb_out); - rte_free(q); - return -1; + ret = -EINVAL; + goto free_companion_ring_addr; } q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; @@ -797,6 +803,21 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, dev->data->queues[queue_id].queue_private = q; return 0; + +free_companion_ring_addr: + rte_free(q->companion_ring_addr); + q->companion_ring_addr = NULL; +free_lb_out: + rte_free(q->lb_out); + q->lb_out = NULL; +free_lb_in: + rte_free(q->lb_in); + q->lb_in = NULL; +free_q: + rte_free(q); + q = NULL; + + return ret; } static inline void @@ -869,6 +890,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF - (uint64_t) (1 << q->aq_id)); + rte_free(q->companion_ring_addr); rte_free(q->lb_in); rte_free(q->lb_out); rte_free(q); @@ -2396,7 +2418,7 @@ enqueue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, - uint16_t total_enqueued_cbs, int16_t num) + uint16_t total_enqueued_descs, int16_t num) { union acc_dma_desc *desc = NULL; uint32_t out_length; @@ -2413,7 +2435,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, } #endif - desc = acc_desc(q, total_enqueued_cbs); + desc = acc_desc(q, total_enqueued_descs); acc_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); /** This could be done at polling */ @@ -2443,6 +2465,11 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, } desc->req.op_addr = ops[0]; + /* Keep track of pointers even when multiplexed in single descriptor */ + struct acc_ptrs *context_ptrs = q->companion_ring_addr + + acc_desc_idx(q, total_enqueued_descs); + for (i = 0; i < num; i++) + context_ptrs->ptr[i].op_addr = ops[i]; #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_le, @@ -3791,7 +3818,8 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc_dma_desc *desc, atom_desc; union acc_dma_rsp_desc rsp; @@ -3799,7 +3827,7 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, int i; uint16_t desc_idx; - desc_idx = acc_desc_idx_tail(q, total_dequeued_cbs); + desc_idx = acc_desc_idx_tail(q, *dequeued_descs); desc = q->ring_addr + desc_idx; atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -3809,7 +3837,7 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x num %d\n", desc, rsp.val, desc->req.numCBs); /* Dequeue */ op = desc->req.op_addr; @@ -3829,27 +3857,35 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.add_info_0 = 0; /*Reserved bits */ desc->rsp.add_info_1 = 0; /*Reserved bits */ - /* Flag that the muxing cause loss of opaque data */ - op->opaque_data = (void *)-1; - for (i = 0 ; i < desc->req.numCBs; i++) - ref_op[i] = op; + ref_op[0] = op; + struct acc_ptrs *context_ptrs = q->companion_ring_addr + desc_idx; + for (i = 1 ; i < desc->req.numCBs; i++) + ref_op[i] = context_ptrs->ptr[i].op_addr; + + /* One CB (op) was successfully dequeued */ + /* One op was successfully dequeued */ + (*dequeued_descs)++; + *dequeued_ops += desc->req.numCBs; /* One CB (op) was successfully dequeued */ return desc->req.numCBs; } -/* Dequeue one encode operations from ACC100 device in TB mode */ +/* Dequeue one LDPC encode operations from ACC100 device in TB mode + * That operation may cover multiple descriptors + */ static inline int dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc_dma_desc *desc, *last_desc, atom_desc; union acc_dma_rsp_desc rsp; struct rte_bbdev_enc_op *op; uint8_t i = 0; - uint16_t current_dequeued_cbs = 0, cbs_in_tb; + uint16_t current_dequeued_descs = 0, descs_in_tb; - desc = acc_desc_tail(q, total_dequeued_cbs); + desc = acc_desc_tail(q, *dequeued_descs); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -3858,9 +3894,9 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; /* Get number of CBs in dequeued TB */ - cbs_in_tb = desc->req.cbs_in_tb; + descs_in_tb = desc->req.cbs_in_tb; /* Get last CB */ - last_desc = acc_desc_tail(q, total_dequeued_cbs + cbs_in_tb - 1); + last_desc = acc_desc_tail(q, *dequeued_descs + descs_in_tb - 1); /* Check if last CB in TB is ready to dequeue (and thus * the whole TB) - checking sdone bit. If not return. */ @@ -3875,14 +3911,13 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, /* Clearing status, it will be set based on response */ op->status = 0; - while (i < cbs_in_tb) { - desc = acc_desc_tail(q, total_dequeued_cbs); + while (i < descs_in_tb) { + desc = acc_desc_tail(q, *dequeued_descs); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", - desc, rsp.val, - cb_idx, cbs_in_tb); + rte_bbdev_log_debug("Resp. desc %p: %x descs %d cbs %d\n", + desc, rsp.val, descs_in_tb, desc->req.numCBs); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); @@ -3896,14 +3931,15 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.val = ACC_DMA_DESC_TYPE; desc->rsp.add_info_0 = 0; desc->rsp.add_info_1 = 0; - total_dequeued_cbs++; - current_dequeued_cbs++; + (*dequeued_descs)++; + current_dequeued_descs++; i++; } *ref_op = op; - return current_dequeued_cbs; + (*dequeued_ops)++; + return current_dequeued_descs; } /* Dequeue one decode operation from ACC100 device in CB mode */ @@ -4093,12 +4129,12 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - uint16_t dequeue_num; uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t i, dequeued_cbs = 0; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; + int ret, cbm; struct rte_bbdev_enc_op *op; - int ret; + if (avail == 0) return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG @@ -4107,30 +4143,36 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, return 0; } #endif + op = (q->ring_addr + (q->sw_ring_tail & + q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; + cbm = op->turbo_enc.code_block_mode; - dequeue_num = (avail < num) ? avail : num; - - for (i = 0; i < dequeue_num; ++i) { - op = acc_op_tail(q, dequeued_cbs); - if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs, - &aq_dequeued); + for (i = 0; i < num; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); else - ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs, - &aq_dequeued); + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; + + if (dequeued_ops >= num) + break; } q->aq_dequeued += aq_dequeued; - q->sw_ring_tail += dequeued_cbs; + q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += i; + q_data->queue_stats.dequeued_count += dequeued_ops; - return i; + return dequeued_ops; } /* Dequeue LDPC encode operations from ACC100 device. */ @@ -4141,24 +4183,36 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct acc_queue *q = q_data->queue_private; uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0; - int ret; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; + int ret, cbm; + struct rte_bbdev_enc_op *op; + union acc_dma_desc *desc; + if (q == NULL) + return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG - if (unlikely(ops == 0 && q == NULL)) + if (unlikely(ops == 0)) return 0; #endif - - dequeue_num = RTE_MIN(avail, num); - - for (i = 0; i < dequeue_num; i++) { - ret = dequeue_enc_one_op_cb(q, &ops[dequeued_cbs], - dequeued_descs, &aq_dequeued); + desc = q->ring_addr + (q->sw_ring_tail & q->sw_ring_wrap_mask); + if (unlikely(desc == NULL)) + return 0; + op = desc->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; + cbm = op->ldpc_enc.code_block_mode; + for (i = 0; i < avail; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); + else + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; - dequeued_descs++; - if (dequeued_cbs >= num) + if (dequeued_ops >= num) break; } @@ -4166,12 +4220,11 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += dequeued_cbs; + q_data->queue_stats.dequeued_count += dequeued_ops; - return dequeued_cbs; + return dequeued_ops; } - /* Dequeue decode operations from ACC100 device. */ static uint16_t acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, From patchwork Fri Oct 21 05:21:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118866 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F220A0552; Thu, 20 Oct 2022 23:27:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 838D242C2E; Thu, 20 Oct 2022 23:25:09 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id D945742BAC for ; Thu, 20 Oct 2022 23:24:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301085; x=1697837085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=llLq6WL7+gmw60ZCeZtK7Hfwp6A/Nhm6KW6YU3OkTzk=; b=jEJH727qCUuO11l4whHJjHmXrZmBWogcK847AWijFBL3Yd/h/tP6ocya QKIayziqXUnRkOhWkSgUdvAOy6FNMza6cpDf0drm8CgQ4RUqe99Q8B82W TPAIzGDB2NqFrEEyi1M75CrIPLhhu6TNuTOgo0GAo2aeyC2Qu8HGnupLr 9AoeLCjj3HYtiS7pphvRc4RYOGqICbhEVrHKS9EctK0TJj73D4WjGOlZL uhBWLccR45MRgbcNzcdJavJ2JS46uuCJ5beldOwN4FfW5mmGF7S9GJthi xYif6H9xrKJr6/1QrYvpkhpaE5ChFW7eDOP+DB0mVrNz2DPvVnMQKgjuv g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887531" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887531" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396958" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396958" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 28/29] baseband/acc100: add workaround for deRM corner cases Date: Thu, 20 Oct 2022 22:21:01 -0700 Message-Id: <20221021052102.107141-29-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add function to support de-ratematch pre-processing for SW corner cases. Some specific 5GUL FEC corner cases may cause unintended back pressure and in some cases potential stability issue on the ACC100. To be able to avoid completly such potential issue, the PMD can preempt such code block configuration so that to process the first level deRM in SW using the SDK libraries prior to running the rest of the FEC decoding in HW using an amended code block configuration. In case meson build system doesn't find such SDK libraries, the fall method is to run in HW as is with a warning. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc_common.h | 8 ++ drivers/baseband/acc/meson.build | 21 +++++ drivers/baseband/acc/rte_acc100_pmd.c | 108 +++++++++++++++++++++++++- 3 files changed, 134 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index eae7eab4e9..5e8972b40a 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -123,6 +123,14 @@ #define ACC_HARQ_ALIGN_64B 64 #define ACC_MAX_ZC 384 +/* De-ratematch code rate limitation when padding is required */ +#define ACC_LIM_03 2 /* 0.03 */ +#define ACC_LIM_09 6 /* 0.09 */ +#define ACC_LIM_14 9 /* 0.14 */ +#define ACC_LIM_21 14 /* 0.21 */ +#define ACC_LIM_31 20 /* 0.31 */ +#define ACC_MAX_E (128 * 1024 - 2) + /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ rte_log(RTE_LOG_ ## level, RTE_LOG_NOTICE, fmt "\n", \ diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build index 77c393b533..a5fc4fed01 100644 --- a/drivers/baseband/acc/meson.build +++ b/drivers/baseband/acc/meson.build @@ -1,6 +1,27 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2020 Intel Corporation +# Check for FlexRAN SDK libraries +dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false) + +if dep_dec5g.found() + ext_deps += cc.find_library('libstdc++', required: true) + ext_deps += cc.find_library('libirc', required: true) + ext_deps += cc.find_library('libimf', required: true) + ext_deps += cc.find_library('libipps', required: true) + ext_deps += cc.find_library('libsvml', required: true) + ext_deps += dep_dec5g + ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true) + ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true) + ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true) + ext_deps += dependency('flexran_sdk_turbo', required: true) + ext_deps += dependency('flexran_sdk_crc', required: true) + ext_deps += dependency('flexran_sdk_rate_matching', required: true) + ext_deps += dependency('flexran_sdk_common', required: true) + cflags += ['-DRTE_BBDEV_SDK_AVX2'] + cflags += ['-DRTE_BBDEV_SDK_AVX512'] +endif + deps += ['bbdev', 'bus_pci'] sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c') diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 23bc5d25bb..e8b230e563 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -25,6 +25,10 @@ #include "acc101_pmd.h" #include "acc200_cfg.h" +#ifdef RTE_BBDEV_SDK_AVX512 +#include +#endif + #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); #else @@ -756,6 +760,14 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, ret = -ENOMEM; goto free_lb_out; } + q->derm_buffer = rte_zmalloc_socket(dev->device->driver->name, + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10, + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->derm_buffer == NULL) { + rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory"); + ret = -ENOMEM; + goto free_companion_ring_addr; + } /* * Software queue ring wraps synchronously with the HW when it reaches @@ -776,7 +788,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { ret = -EINVAL; - goto free_companion_ring_addr; + goto free_derm_buffer; } q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; @@ -804,6 +816,9 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, dev->data->queues[queue_id].queue_private = q; return 0; +free_derm_buffer: + rte_free(q->derm_buffer); + q->derm_buffer = NULL; free_companion_ring_addr: rte_free(q->companion_ring_addr); q->companion_ring_addr = NULL; @@ -890,6 +905,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF - (uint64_t) (1 << q->aq_id)); + rte_free(q->derm_buffer); rte_free(q->companion_ring_addr); rte_free(q->lb_in); rte_free(q->lb_out); @@ -3111,10 +3127,44 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, return 1; } +/** Assess whether a work around is required for the deRM corner cases */ +static inline bool +derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_queue *q) +{ + if (!is_acc100(q)) + return false; + int32_t e = ldpc_dec->cb_params.e; + int q_m = ldpc_dec->q_m; + int z_c = ldpc_dec->z_c; + int K = (ldpc_dec->basegraph == 1 ? ACC_K_ZC_1 : ACC_K_ZC_2) + * z_c; + + bool required = false; + if (ldpc_dec->basegraph == 1) { + if ((q_m == 4) && (z_c >= 320) && (e * ACC_LIM_31 > K * 64)) + required = true; + else if ((e * ACC_LIM_21 > K * 64)) + required = true; + } else { + if (q_m <= 2) { + if ((z_c >= 208) && (e * ACC_LIM_09 > K * 64)) + required = true; + else if ((z_c < 208) && (e * ACC_LIM_03 > K * 64)) + required = true; + } else if (e * ACC_LIM_14 > K * 64) + required = true; + } + if (required) + rte_bbdev_log(INFO, "Running deRM pre-processing in SW"); + + return required; +} + /** Enqueue one decode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, - uint16_t total_enqueued_cbs, bool same_op) + uint16_t total_enqueued_cbs, bool same_op, + struct rte_bbdev_queue_data *q_data) { int ret; if (unlikely(check_bit(op->ldpc_dec.op_flags, @@ -3168,6 +3218,58 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, } else { struct acc_fcw_ld *fcw; uint32_t seg_total_left; + + if (derm_workaround_required(&op->ldpc_dec, q)) { + #ifdef RTE_BBDEV_SDK_AVX512 + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + struct bblib_rate_dematching_5gnr_request derm_req; + struct bblib_rate_dematching_5gnr_response derm_resp; + uint8_t *in; + + /* Checking input size is matching with E */ + if (dec->input.data->data_len < dec->cb_params.e) { + rte_bbdev_log(ERR, "deRM: Input size mismatch"); + return -EFAULT; + } + /* Run first deRM processing in SW */ + in = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset); + derm_req.p_in = (int8_t *) in; + derm_req.p_harq = (int8_t *) q->derm_buffer; + derm_req.base_graph = dec->basegraph; + derm_req.zc = dec->z_c; + derm_req.ncb = dec->n_cb; + derm_req.e = dec->cb_params.e; + if (derm_req.e > ACC_MAX_E) { + rte_bbdev_log(WARNING, + "deRM: E %d > %d max", + derm_req.e, ACC_MAX_E); + derm_req.e = ACC_MAX_E; + } + derm_req.k0 = 0; /* Actual output from SDK */ + derm_req.isretx = false; + derm_req.rvid = dec->rv_index; + derm_req.modulation_order = dec->q_m; + derm_req.start_null_index = + (dec->basegraph == 1 ? 22 : 10) + * dec->z_c - 2 * dec->z_c + - dec->n_filler; + derm_req.num_of_null = dec->n_filler; + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); + /* Force back the HW DeRM */ + dec->q_m = 1; + dec->cb_params.e = dec->n_cb - dec->n_filler; + dec->rv_index = 0; + rte_memcpy(in, q->derm_buffer, dec->cb_params.e); + /* Capture counter when pre-processing is used */ + q_data->queue_stats.enqueue_warn_count++; + #else + RTE_SET_USED(q_data); + rte_bbdev_log(WARNING, + "Corner case may require deRM pre-processing in SDK" + ); + #endif + } + fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); @@ -3721,7 +3823,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); - ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); + ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data); if (ret < 0) { acc_enqueue_invalid(q_data); break; From patchwork Fri Oct 21 05:21:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118867 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90820A0552; Thu, 20 Oct 2022 23:27:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3408742C45; Thu, 20 Oct 2022 23:25:14 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id AF16E42C2C for ; Thu, 20 Oct 2022 23:25:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301108; x=1697837108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tPBOkEwKOXMhl3og3EQSQuZyO6z/sJsxMw/bY++NRfI=; b=UGONVDs+r0rtX3J86N/vgXcGkTGbk42dRSxxGHCPYQ0R8lroC9yZ+1kz 89POl/wPiy0MrebqSgNF8FcHGq2gReaJ4WzclLHlwfXOmDe5RwGtuMBm8 bKQV5hRimKFhMs1ymM+5PvsmT5bPCqw1ihij4qoB+tWa8sWhreeV4RPXx E676hjMkaFgPnuvKOv496fQZe1KjBO6Uk8ZFKx/vvoM/Eg3xCxbH3py/g VZMGkB7wBSX+nval+VEFglOqNXdKnXqvXNIet110rXIKOSIpwLMQvcRa7 /qPvpIeCuNbImbFML/88VCQb0Uh5bjJPuzzkgaZnTrIUHf0xq/SY6aLQd g==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887532" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887532" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396967" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396967" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:44 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v5 29/29] baseband/acc100: configure PMON control registers Date: Thu, 20 Oct 2022 22:21:02 -0700 Message-Id: <20221021052102.107141-30-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc100_pmd.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index eb6349c85a..8c0aec5ed8 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -115,6 +115,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -144,6 +146,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure holding registry addresses for VF */