From patchwork Thu Oct 20 11:14:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118780 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ADF88A0552; Thu, 20 Oct 2022 13:15:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF0EA42D3F; Thu, 20 Oct 2022 13:15:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BA83442D3A for ; Thu, 20 Oct 2022 13:15:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29K8Klck022018 for ; Thu, 20 Oct 2022 04:14:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=K/Pyv0NAxP12p02y/+Wtey8xZcw3mfomvzv9AnlJuIE=; b=dBpKIMK0L6WoxAOI36KVOG5d1ZkuxhFW4JQZkS2qXVb0jUKmpB9ISwrOUHDvc5Qn3Kx0 8+4CR6qBFL5rFJeWAObH67bFeP2xM5AxwtAFzmeQ/cn4v+H54CNHrN/4w8BZc2MlzdmB GBfQsLwZPkQT2XlA8e64QwagbdaUzflTjJFtKwwj+ktCQyD7/7yfSV5bvfliQYjybkE/ tSZ4R57lXTR5wBJmwF2mUIa9n+ARiBxqsOTkOb63KMUNeN7Sti9+XmLSVH4MLppgAIav MhRpg5oM1yDJUNGMpKZ0VLWc9JeEZ/LodwZOZzN0fSVTW5bI9pKj9NtDQJ53ydCno6Cr nQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3kb2qx8jc0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 20 Oct 2022 04:14:59 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:14:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 20 Oct 2022 04:14:58 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 4AFD33F7079; Thu, 20 Oct 2022 04:14:56 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Subject: [PATCH 08/13] common/cnxk: add opad ipad gen for md5 Date: Thu, 20 Oct 2022 16:44:48 +0530 Message-ID: <20221020111453.1982947-2-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: IkTC_V_JvVIT0ZmemOpBRWkUdZN_x6Ab X-Proofpoint-ORIG-GUID: IkTC_V_JvVIT0ZmemOpBRWkUdZN_x6Ab X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add support to generate ipad and opad for md5. Skip the call to additional command WRITE_SA during SA creation. Instead use the software defined function to generate opad and ipad. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/cnxk_security.c | 49 ++++----- drivers/common/cnxk/roc_cpt.c | 95 ----------------- drivers/common/cnxk/roc_cpt.h | 3 - drivers/common/cnxk/roc_hash.c | 155 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_hash.h | 1 + drivers/common/cnxk/roc_ie_on.h | 2 - drivers/common/cnxk/roc_nix_inl.c | 6 -- drivers/common/cnxk/version.map | 2 +- drivers/crypto/cnxk/cn9k_ipsec.c | 7 -- drivers/net/cnxk/cn9k_ethdev_sec.c | 8 -- 10 files changed, 178 insertions(+), 150 deletions(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index f220d2577f..68ed0d08b4 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -28,6 +28,10 @@ ipsec_hmac_opad_ipad_gen(struct rte_crypto_sym_xform *auth_xform, * per packet computation */ switch (auth_xform->auth.algo) { + case RTE_CRYPTO_AUTH_MD5_HMAC: + roc_hash_md5_gen(opad, (uint32_t *)&hmac_opad_ipad[0]); + roc_hash_md5_gen(ipad, (uint32_t *)&hmac_opad_ipad[24]); + break; case RTE_CRYPTO_AUTH_SHA1_HMAC: roc_hash_sha1_gen(opad, (uint32_t *)&hmac_opad_ipad[0]); roc_hash_sha1_gen(ipad, (uint32_t *)&hmac_opad_ipad[24]); @@ -1218,9 +1222,7 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec, struct roc_ie_on_sa_ctl *ctl; struct rte_ipv6_hdr *ip6; struct rte_ipv4_hdr *ip4; - const uint8_t *auth_key; uint16_t sport, dport; - int auth_key_len = 0; size_t ctx_len; int ret; @@ -1343,29 +1345,14 @@ cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec, ctx_len += RTE_ALIGN_CEIL(ctx_len, 8); if (crypto_xform->type != RTE_CRYPTO_SYM_XFORM_AEAD) { - auth_key = auth_xform->auth.key.data; - auth_key_len = auth_xform->auth.key.length; + uint8_t *hmac_opad_ipad = (uint8_t *)&out_sa->sha2; - switch (auth_xform->auth.algo) { - case RTE_CRYPTO_AUTH_AES_GMAC: - case RTE_CRYPTO_AUTH_NULL: - break; - case RTE_CRYPTO_AUTH_MD5_HMAC: - case RTE_CRYPTO_AUTH_SHA1_HMAC: - memcpy(out_sa->sha1.hmac_key, auth_key, auth_key_len); - break; - case RTE_CRYPTO_AUTH_SHA256_HMAC: - case RTE_CRYPTO_AUTH_SHA384_HMAC: - case RTE_CRYPTO_AUTH_SHA512_HMAC: - memcpy(out_sa->sha2.hmac_key, auth_key, auth_key_len); - break; - case RTE_CRYPTO_AUTH_AES_XCBC_MAC: - memcpy(out_sa->aes_xcbc.key, auth_key, auth_key_len); - break; - default: - plt_err("Unsupported auth algorithm %u", - auth_xform->auth.algo); - return -ENOTSUP; + if (auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) { + const uint8_t *auth_key = auth_xform->auth.key.data; + + roc_aes_xcbc_key_derive(auth_key, hmac_opad_ipad); + } else if (auth_xform->auth.algo != RTE_CRYPTO_AUTH_NULL) { + ipsec_hmac_opad_ipad_gen(auth_xform, hmac_opad_ipad); } } @@ -1390,9 +1377,9 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec, if (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD || auth_xform->auth.algo == RTE_CRYPTO_AUTH_NULL || auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) { - ctx_len = offsetof(struct roc_ie_on_inb_sa, - sha1_or_gcm.hmac_key[0]); + ctx_len = offsetof(struct roc_ie_on_inb_sa, sha1_or_gcm.hmac_key[0]); } else { + uint8_t *hmac_opad_ipad = (uint8_t *)&in_sa->sha2; auth_key = auth_xform->auth.key.data; auth_key_len = auth_xform->auth.key.length; @@ -1419,10 +1406,16 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec, aes_xcbc.selector); break; default: - plt_err("Unsupported auth algorithm %u", - auth_xform->auth.algo); + plt_err("Unsupported auth algorithm %u", auth_xform->auth.algo); return -ENOTSUP; } + if (auth_xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) { + const uint8_t *auth_key = auth_xform->auth.key.data; + + roc_aes_xcbc_key_derive(auth_key, hmac_opad_ipad); + } else if (auth_xform->auth.algo != RTE_CRYPTO_AUTH_NULL) { + ipsec_hmac_opad_ipad_gen(auth_xform, hmac_opad_ipad); + } } return ctx_len; diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 311f0a08c4..fb97ec89b2 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -1079,98 +1079,3 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, return 0; } - -int -roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb, - uint16_t ctx_len, uint8_t egrp) -{ - union cpt_res_s res, *hw_res; - struct cpt_inst_s inst; - uint64_t lmt_status; - int ret = 0; - - hw_res = plt_zmalloc(sizeof(*hw_res), ROC_CPT_RES_ALIGN); - if (unlikely(hw_res == NULL)) { - plt_err("Couldn't allocate memory for result address"); - return -ENOMEM; - } - - hw_res->cn9k.compcode = CPT_COMP_NOT_DONE; - - inst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND; - if (inb) - inst.w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND; - inst.w4.s.opcode_minor = ctx_len >> 3; - inst.w4.s.param1 = 0; - inst.w4.s.param2 = 0; - inst.w4.s.dlen = ctx_len; - inst.dptr = sa; - inst.rptr = 0; - inst.w7.s.cptr = sa; - inst.w7.s.egrp = egrp; - - inst.w0.u64 = 0; - inst.w2.u64 = 0; - inst.w3.u64 = 0; - inst.res_addr = (uintptr_t)hw_res; - - plt_io_wmb(); - - do { - /* Copy CPT command to LMTLINE */ - roc_lmt_mov64((void *)lf->lmt_base, &inst); - lmt_status = roc_lmt_submit_ldeor(lf->io_addr); - } while (lmt_status == 0); - - const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz(); - - /* Wait until CPT instruction completes */ - do { - res.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED); - if (unlikely(plt_tsc_cycles() > timeout)) { - plt_err("Request timed out"); - ret = -ETIMEDOUT; - goto free; - } - } while (res.cn9k.compcode == CPT_COMP_NOT_DONE); - - if (unlikely(res.cn9k.compcode != CPT_COMP_GOOD)) { - ret = res.cn9k.compcode; - switch (ret) { - case CPT_COMP_INSTERR: - plt_err("Request failed with instruction error"); - break; - case CPT_COMP_FAULT: - plt_err("Request failed with DMA fault"); - break; - case CPT_COMP_HWERR: - plt_err("Request failed with hardware error"); - break; - default: - plt_err("Request failed with unknown hardware completion code : 0x%x", - ret); - } - ret = -EINVAL; - goto free; - } - - if (unlikely(res.cn9k.uc_compcode != ROC_IE_ON_UCC_SUCCESS)) { - ret = res.cn9k.uc_compcode; - switch (ret) { - case ROC_IE_ON_AUTH_UNSUPPORTED: - plt_err("Invalid auth type"); - break; - case ROC_IE_ON_ENCRYPT_UNSUPPORTED: - plt_err("Invalid encrypt type"); - break; - default: - plt_err("Request failed with unknown microcode completion code : 0x%x", - ret); - } - ret = -ENOTSUP; - } - -free: - plt_free(hw_res); - return ret; -} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 57e9bea83a..bc9cc19edd 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -174,7 +174,4 @@ int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len); - -int __roc_api roc_on_cpt_ctx_write(struct roc_cpt_lf *lf, uint64_t sa, bool inb, - uint16_t ctx_len, uint8_t egrp); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/roc_hash.c b/drivers/common/cnxk/roc_hash.c index 4a34c7fbf8..1b9030e693 100644 --- a/drivers/common/cnxk/roc_hash.c +++ b/drivers/common/cnxk/roc_hash.c @@ -9,6 +9,161 @@ #define lrot64(bits, word) (((word) << (bits)) | ((word) >> (64 - (bits)))) #define rrot64(bits, word) lrot64(64 - (bits), word) +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) + +/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4. + * Rotation is separate from addition to prevent recomputation. + */ + +#define FF(a, b, c, d, x, s, ac) \ + { \ + (a) += F((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT((a), (s)); \ + (a) += (b); \ + } + +#define GG(a, b, c, d, x, s, ac) \ + { \ + (a) += G((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT((a), (s)); \ + (a) += (b); \ + } + +#define HH(a, b, c, d, x, s, ac) \ + { \ + (a) += H((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT((a), (s)); \ + (a) += (b); \ + } + +#define II(a, b, c, d, x, s, ac) \ + { \ + (a) += I((b), (c), (d)) + (x) + (uint32_t)(ac); \ + (a) = ROTATE_LEFT((a), (s)); \ + (a) += (b); \ + } + +/* + * Compute a partial hash with the assumption that msg is the first block. + * Based on implementation from RFC 1321 + */ +void +roc_hash_md5_gen(uint8_t *msg, uint32_t *hash) +{ + uint32_t state[4] = {0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476}; + uint32_t a = state[0]; + uint32_t b = state[1]; + uint32_t c = state[2]; + uint32_t d = state[3]; + uint32_t x[16]; + + memcpy(x, msg, 64); + + /* Round 1 */ + FF(a, b, c, d, x[0], S11, 0xd76aa478); /* 1 */ + FF(d, a, b, c, x[1], S12, 0xe8c7b756); /* 2 */ + FF(c, d, a, b, x[2], S13, 0x242070db); /* 3 */ + FF(b, c, d, a, x[3], S14, 0xc1bdceee); /* 4 */ + FF(a, b, c, d, x[4], S11, 0xf57c0faf); /* 5 */ + FF(d, a, b, c, x[5], S12, 0x4787c62a); /* 6 */ + FF(c, d, a, b, x[6], S13, 0xa8304613); /* 7 */ + FF(b, c, d, a, x[7], S14, 0xfd469501); /* 8 */ + FF(a, b, c, d, x[8], S11, 0x698098d8); /* 9 */ + FF(d, a, b, c, x[9], S12, 0x8b44f7af); /* 10 */ + FF(c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ + FF(b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */ + FF(a, b, c, d, x[12], S11, 0x6b901122); /* 13 */ + FF(d, a, b, c, x[13], S12, 0xfd987193); /* 14 */ + FF(c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ + FF(b, c, d, a, x[15], S14, 0x49b40821); /* 16 */ + + /* Round 2 */ + GG(a, b, c, d, x[1], S21, 0xf61e2562); /* 17 */ + GG(d, a, b, c, x[6], S22, 0xc040b340); /* 18 */ + GG(c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */ + GG(b, c, d, a, x[0], S24, 0xe9b6c7aa); /* 20 */ + GG(a, b, c, d, x[5], S21, 0xd62f105d); /* 21 */ + GG(d, a, b, c, x[10], S22, 0x2441453); /* 22 */ + GG(c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */ + GG(b, c, d, a, x[4], S24, 0xe7d3fbc8); /* 24 */ + GG(a, b, c, d, x[9], S21, 0x21e1cde6); /* 25 */ + GG(d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */ + GG(c, d, a, b, x[3], S23, 0xf4d50d87); /* 27 */ + GG(b, c, d, a, x[8], S24, 0x455a14ed); /* 28 */ + GG(a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ + GG(d, a, b, c, x[2], S22, 0xfcefa3f8); /* 30 */ + GG(c, d, a, b, x[7], S23, 0x676f02d9); /* 31 */ + GG(b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */ + + /* Round 3 */ + HH(a, b, c, d, x[5], S31, 0xfffa3942); /* 33 */ + HH(d, a, b, c, x[8], S32, 0x8771f681); /* 34 */ + HH(c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */ + HH(b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */ + HH(a, b, c, d, x[1], S31, 0xa4beea44); /* 37 */ + HH(d, a, b, c, x[4], S32, 0x4bdecfa9); /* 38 */ + HH(c, d, a, b, x[7], S33, 0xf6bb4b60); /* 39 */ + HH(b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */ + HH(a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */ + HH(d, a, b, c, x[0], S32, 0xeaa127fa); /* 42 */ + HH(c, d, a, b, x[3], S33, 0xd4ef3085); /* 43 */ + HH(b, c, d, a, x[6], S34, 0x4881d05); /* 44 */ + HH(a, b, c, d, x[9], S31, 0xd9d4d039); /* 45 */ + HH(d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ + HH(c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */ + HH(b, c, d, a, x[2], S34, 0xc4ac5665); /* 48 */ + + /* Round 4 */ + II(a, b, c, d, x[0], S41, 0xf4292244); /* 49 */ + II(d, a, b, c, x[7], S42, 0x432aff97); /* 50 */ + II(c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */ + II(b, c, d, a, x[5], S44, 0xfc93a039); /* 52 */ + II(a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */ + II(d, a, b, c, x[3], S42, 0x8f0ccc92); /* 54 */ + II(c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */ + II(b, c, d, a, x[1], S44, 0x85845dd1); /* 56 */ + II(a, b, c, d, x[8], S41, 0x6fa87e4f); /* 57 */ + II(d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */ + II(c, d, a, b, x[6], S43, 0xa3014314); /* 59 */ + II(b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */ + II(a, b, c, d, x[4], S41, 0xf7537e82); /* 61 */ + II(d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */ + II(c, d, a, b, x[2], S43, 0x2ad7d2bb); /* 63 */ + II(b, c, d, a, x[9], S44, 0xeb86d391); /* 64 */ + + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + + hash[0] = state[0]; + hash[1] = state[1]; + hash[2] = state[2]; + hash[3] = state[3]; +} + /* * Compute a partial hash with the assumption that msg is the first block. * Based on implementation from RFC 3174 diff --git a/drivers/common/cnxk/roc_hash.h b/drivers/common/cnxk/roc_hash.h index 1bc9222445..8940faa6eb 100644 --- a/drivers/common/cnxk/roc_hash.h +++ b/drivers/common/cnxk/roc_hash.h @@ -9,6 +9,7 @@ * Compute a partial hash with the assumption that msg is the first block. * Based on implementation from RFC 3174 */ +void __roc_api roc_hash_md5_gen(uint8_t *msg, uint32_t *hash); void __roc_api roc_hash_sha1_gen(uint8_t *msg, uint32_t *hash); void __roc_api roc_hash_sha256_gen(uint8_t *msg, uint32_t *hash); void __roc_api roc_hash_sha512_gen(uint8_t *msg, uint64_t *hash, int hash_size); diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h index 5d02684e34..057ff95362 100644 --- a/drivers/common/cnxk/roc_ie_on.h +++ b/drivers/common/cnxk/roc_ie_on.h @@ -8,8 +8,6 @@ /* CN9K IPsec LA */ /* CN9K IPsec LA opcodes */ -#define ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_OUTBOUND 0x20 -#define ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND 0x21 #define ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23 #define ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24 diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index cdf31b1f0c..669236c5af 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1301,12 +1301,6 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, /* Nothing much to do on cn9k */ if (roc_model_is_cn9k()) { - nix = roc_nix_to_nix_priv(roc_nix); - outb_lf = nix->cpt_lf_base; - rc = roc_on_cpt_ctx_write(outb_lf, (uint64_t)sa_dptr, inb, - sa_len, ROC_CPT_DFLT_ENG_GRP_SE_IE); - if (rc) - return rc; return 0; } diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 276fec3660..8358fb5979 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -78,13 +78,13 @@ INTERNAL { roc_cpt_parse_hdr_dump; roc_cpt_rxc_time_cfg; roc_cpt_ctx_write; - roc_on_cpt_ctx_write; roc_dpi_configure; roc_dpi_dev_fini; roc_dpi_dev_init; roc_dpi_disable; roc_dpi_enable; roc_error_msg_get; + roc_hash_md5_gen; roc_hash_sha1_gen; roc_hash_sha256_gen; roc_hash_sha512_gen; diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c index 9ae7c73b37..fa00c428e6 100644 --- a/drivers/crypto/cnxk/cn9k_ipsec.c +++ b/drivers/crypto/cnxk/cn9k_ipsec.c @@ -81,10 +81,6 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp, ctx_len = ret; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; - ret = roc_on_cpt_ctx_write(&qp->lf, (uintptr_t)sa, false, ctx_len, egrp); - - if (ret) - return ret; w4.u64 = 0; w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_OUTBOUND_IPSEC | ROC_IE_ON_INPLACE_BIT; @@ -169,9 +165,6 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp, ctx_len = ret; egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; - ret = roc_on_cpt_ctx_write(&qp->lf, (uint64_t)sa, true, ctx_len, egrp); - if (ret) - return ret; w4.u64 = 0; w4.s.opcode_major = ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC | ROC_IE_ON_INPLACE_BIT; diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index af3f74046a..67966a4e49 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -600,14 +600,6 @@ cn9k_eth_sec_session_create(void *device, } ctx_len = rc; - rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa, inb_sa, inbound, - ctx_len); - if (rc) { - snprintf(tbuf, sizeof(tbuf), - "Failed to create inbound sa, rc=%d", rc); - goto err; - } - inb_priv = roc_nix_inl_on_ipsec_inb_sa_sw_rsvd(inb_sa); /* Back pointer to get eth_sec */ inb_priv->eth_sec = eth_sec; From patchwork Thu Oct 20 11:14:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118781 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79F4EA0552; Thu, 20 Oct 2022 13:15:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0ACF442D52; Thu, 20 Oct 2022 13:15:04 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E8D1642D4F for ; Thu, 20 Oct 2022 13:15:02 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29K6Qiaw010176 for ; Thu, 20 Oct 2022 04:15:02 -0700 DKIM-Signature: v=1; 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Thu, 20 Oct 2022 04:15:00 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 517373F7044; Thu, 20 Oct 2022 04:14:58 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 09/13] crypto/cnxk: support PDCP AAD in CPT PMD Date: Thu, 20 Oct 2022 16:44:49 +0530 Message-ID: <20221020111453.1982947-3-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x X-Proofpoint-ORIG-GUID: Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for PDCP AAD in 96xx crypto pmd. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 10 +-- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 4 +- drivers/crypto/cnxk/cnxk_se.h | 86 +++++++++++------------- 3 files changed, 48 insertions(+), 52 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index e0ceaa32d5..a9c42205e6 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -27,11 +27,13 @@ cnxk_cpt_get_mlen(void) len = 2 * sizeof(uint64_t); len += ROC_SE_MAX_MAC_LEN * sizeof(uint8_t); + /* For PDCP_CHAIN passthrough alignment */ + len += 8; len += ROC_SE_OFF_CTRL_LEN + ROC_CPT_AES_CBC_IV_LEN; - len += RTE_ALIGN_CEIL((ROC_SE_SG_LIST_HDR_SIZE + - (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >> - 2) * ROC_SE_SG_ENTRY_SIZE), - 8); + len += RTE_ALIGN_CEIL( + (ROC_SE_SG_LIST_HDR_SIZE + + (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >> 2) * ROC_SE_SG_ENTRY_SIZE), + 8); return len; } diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 2064120505..13c90444d6 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -10,8 +10,8 @@ #include "roc_api.h" -#define CNXK_CPT_MIN_HEADROOM_REQ 24 -#define CNXK_CPT_MIN_TAILROOM_REQ 102 +#define CNXK_CPT_MIN_HEADROOM_REQ 32 +#define CNXK_CPT_MIN_TAILROOM_REQ 102 /* Default command timeout in seconds */ #define DEFAULT_COMMAND_TIMEOUT 4 diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 9ce75c07e0..abb9965d3e 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1393,12 +1393,11 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, static __rte_always_inline int cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, - struct roc_se_fc_params *params, - struct cpt_inst_s *inst) + struct roc_se_fc_params *params, struct cpt_inst_s *inst) { + uint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len; uint32_t encr_offset, auth_offset, iv_offset = 0; uint8_t *auth_iv = NULL, *cipher_iv = NULL; - uint32_t encr_data_len, auth_data_len; uint8_t pdcp_ci_alg, pdcp_auth_alg; union cpt_inst_w4 cpt_inst_w4; struct roc_se_ctx *se_ctx; @@ -1413,12 +1412,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, encr_offset = ROC_SE_ENCR_OFFSET(d_offs); auth_offset = ROC_SE_AUTH_OFFSET(d_offs); - if (auth_offset != encr_offset) { - plt_dp_err("encr_offset and auth_offset are not same"); - plt_dp_err("enc_offset: %d", encr_offset); - plt_dp_err("auth_offset: %d", auth_offset); - return -1; - } + aad_len = encr_offset - auth_offset; if (unlikely(encr_offset >> 16)) { plt_dp_err("Offset not supported"); @@ -1433,12 +1427,16 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, encr_data_len = ROC_SE_ENCR_DLEN(d_lens); auth_data_len = ROC_SE_AUTH_DLEN(d_lens); + auth_data_len -= aad_len; + + encr_offset += iv_len; + auth_offset = encr_offset - aad_len; + passthr_len = RTE_ALIGN_CEIL(auth_offset, 8); - if ((auth_data_len + mac_len) != encr_data_len) { - plt_dp_err("(auth_data_len + mac_len) != encr_data_len"); - plt_dp_err("auth_data_len: %d", auth_data_len); - plt_dp_err("encr_data_len: %d", encr_data_len); - plt_dp_err("mac_len: %d", mac_len); + if (unlikely((aad_len >> 16) || (passthr_len >> 8))) { + plt_dp_err("Length not supported"); + plt_dp_err("AAD_len: %d", aad_len); + plt_dp_err("Passthrough_len: %d", passthr_len); return -1; } @@ -1454,12 +1452,15 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, if (likely(params->cipher_iv_len)) cipher_iv = params->iv_buf; - encr_offset += iv_len; + pad_len = passthr_len - auth_offset; + hdr_len = iv_len + pad_len; if (se_ctx->auth_then_ciph) - inputlen = encr_offset + auth_data_len; + inputlen = auth_data_len; else - inputlen = encr_offset + encr_data_len; + inputlen = encr_data_len; + + inputlen += (encr_offset + pad_len); if (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) && ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { @@ -1468,19 +1469,18 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* Use Direct mode */ - offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - - ROC_SE_OFF_CTRL_LEN - iv_len); + offset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len); /* DPTR */ inst->dptr = (uint64_t)offset_vaddr; /* RPTR should just exclude offset control word */ - inst->rptr = (uint64_t)dm_vaddr - iv_len; + inst->rptr = (uint64_t)PLT_PTR_SUB(dm_vaddr, hdr_len); cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; *(uint64_t *)offset_vaddr = - rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | - ((uint64_t)(encr_offset))); + rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) | + ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len))); iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); @@ -1499,8 +1499,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* save space for IV */ offset_vaddr = m_vaddr; - m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + - RTE_ALIGN_CEIL(iv_len, 8); + m_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + RTE_ALIGN_CEIL(hdr_len, 8)); cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; @@ -1519,11 +1518,11 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* Offset control word followed by iv */ i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, - ROC_SE_OFF_CTRL_LEN + iv_len); + ROC_SE_OFF_CTRL_LEN + hdr_len); *(uint64_t *)offset_vaddr = - rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | - ((uint64_t)(encr_offset))); + rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) | + ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len))); iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); @@ -1532,11 +1531,10 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); /* input data */ - size = inputlen - iv_len; + size = inputlen - hdr_len; if (size) { - i = fill_sg_comp_from_iov(gather_comp, i, - params->src_iov, 0, &size, - NULL, 0); + i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL, + 0); if (unlikely(size)) { plt_dp_err("Insufficient buffer space," " size %d needed", @@ -1553,29 +1551,25 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, */ i = 0; - scatter_comp = - (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + - g_size_bytes); + scatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes); - if (iv_len) { + if ((hdr_len)) { i = fill_sg_comp(scatter_comp, i, - (uint64_t)offset_vaddr + - ROC_SE_OFF_CTRL_LEN, - iv_len); + (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN, hdr_len); } /* Add output data */ - if (se_ctx->ciph_then_auth && - (req_flags & ROC_SE_VALID_MAC_BUF)) - size = inputlen - iv_len; + if (se_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF)) + size = inputlen; else /* Output including mac */ - size = inputlen - iv_len + mac_len; + size = inputlen + mac_len; + + size -= hdr_len; if (size) { - i = fill_sg_comp_from_iov(scatter_comp, i, - params->dst_iov, 0, &size, - NULL, 0); + i = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL, + 0); if (unlikely(size)) { plt_dp_err("Insufficient buffer space," @@ -2399,7 +2393,7 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt, *flags |= ROC_SE_SINGLE_BUF_INPLACE; headroom = rte_pktmbuf_headroom(pkt); - if (likely(headroom >= 24)) + if (likely(headroom >= CNXK_CPT_MIN_HEADROOM_REQ)) *flags |= ROC_SE_SINGLE_BUF_HEADROOM; param->bufs[0].vaddr = seg_data; From patchwork Thu Oct 20 11:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118782 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D40A7A0552; Thu, 20 Oct 2022 13:15:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D93DB42D54; Thu, 20 Oct 2022 13:15:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B01CA42D45 for ; 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Thu, 20 Oct 2022 04:15:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:15:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Oct 2022 04:15:02 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 55B063F7079; Thu, 20 Oct 2022 04:15:00 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Subject: [PATCH 10/13] crypto/cnxk: acquire lock while updating antireplay Date: Thu, 20 Oct 2022 16:44:50 +0530 Message-ID: <20221020111453.1982947-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xEn9y9WcjZuG_Y0EjQFeSUz7sTWtNYW4 X-Proofpoint-ORIG-GUID: xEn9y9WcjZuG_Y0EjQFeSUz7sTWtNYW4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Acquire locks in antireplay logic to avoid race condition Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 2a5c00eadd..04c004bc7a 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -500,6 +500,7 @@ ipsec_antireplay_check(struct cn9k_sec_session *sess, uint32_t win_sz, if (unlikely(seq == 0)) return IPSEC_ANTI_REPLAY_FAILED; + rte_spinlock_lock(&sess->ar.lock); ret = cnxk_on_anti_replay_check(seq, &sess->ar, win_sz); if (esn && !ret) { esn_low = rte_be_to_cpu_32(common_sa->seq_t.tl); @@ -510,6 +511,7 @@ ipsec_antireplay_check(struct cn9k_sec_session *sess, uint32_t win_sz, common_sa->seq_t.th = rte_cpu_to_be_32(seqh); } } + rte_spinlock_unlock(&sess->ar.lock); return ret; } From patchwork Thu Oct 20 11:14:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118783 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 32E1BA0552; Thu, 20 Oct 2022 13:15:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B543142D5B; Thu, 20 Oct 2022 13:15:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2FFF142D45 for ; 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Thu, 20 Oct 2022 04:15:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:15:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Oct 2022 04:15:04 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 6156E3F70BE; Thu, 20 Oct 2022 04:15:02 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 11/13] crypto/cnxk: switch to SG when metabuf is allocated Date: Thu, 20 Oct 2022 16:44:51 +0530 Message-ID: <20221020111453.1982947-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: gDq9rUstLrkTKfMs6FxAUVRuSjGEZ5Sd X-Proofpoint-ORIG-GUID: gDq9rUstLrkTKfMs6FxAUVRuSjGEZ5Sd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Metabuf would be allocated only when SG is required. Check the pointer instead of flags. Coverity issue: 381018 Fixes: d3bff77cc371 ("crypto/cnxk: separate out PDCP chain datapath") Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_se.h | 33 ++++++--------------------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index abb9965d3e..ac97b864b9 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1177,14 +1177,7 @@ cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, offset_ctrl = rte_cpu_to_be_64(((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) | ((uint64_t)auth_offset)); - /* - * In cn9k, cn10k since we have a limitation of - * IV & Offset control word not part of instruction - * and need to be part of Data Buffer, we check if - * head room is there and then only do the Direct mode processing - */ - if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) && - (flags & ROC_SE_SINGLE_BUF_HEADROOM))) { + if (likely(fc_params->meta_buf.vaddr == NULL)) { void *dm_vaddr = fc_params->bufs[0].vaddr; /* Use Direct mode */ @@ -1336,13 +1329,7 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, offset_ctrl = rte_cpu_to_be_64(((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) | ((uint64_t)auth_offset)); - /* - * In cn9k, cn10k since we have a limitation of - * IV & Offset control word not part of instruction - * and need to be part of Data Buffer, we check if - * head room is there and then only do the Direct mode processing - */ - if (likely((flags & ROC_SE_SINGLE_BUF_INPLACE) && (flags & ROC_SE_SINGLE_BUF_HEADROOM))) { + if (likely(fc_params->meta_buf.vaddr == NULL)) { void *dm_vaddr = fc_params->bufs[0].vaddr; /* Use Direct mode */ @@ -1398,6 +1385,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, uint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len; uint32_t encr_offset, auth_offset, iv_offset = 0; uint8_t *auth_iv = NULL, *cipher_iv = NULL; + void *m_vaddr = params->meta_buf.vaddr; uint8_t pdcp_ci_alg, pdcp_auth_alg; union cpt_inst_w4 cpt_inst_w4; struct roc_se_ctx *se_ctx; @@ -1462,8 +1450,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, inputlen += (encr_offset + pad_len); - if (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) && - ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { + if (likely(m_vaddr == NULL)) { dm_vaddr = params->bufs[0].vaddr; @@ -1489,9 +1476,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); } else { - struct roc_se_sglist_comp *scatter_comp, *gather_comp; - void *m_vaddr = params->meta_buf.vaddr; uint32_t i, g_size_bytes, s_size_bytes; uint8_t *in_buffer; uint32_t size; @@ -1711,14 +1696,7 @@ cpt_pdcp_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, cpt_inst_w4.s.param1 = encr_data_len; cpt_inst_w4.s.param2 = auth_data_len; - /* - * In cn9k, cn10k since we have a limitation of - * IV & Offset control word not part of instruction - * and need to be part of Data Buffer, we check if - * head room is there and then only do the Direct mode processing - */ - if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) && - (req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) { + if (likely(params->meta_buf.vaddr == NULL)) { void *dm_vaddr = params->bufs[0].vaddr; /* Use Direct mode */ @@ -2889,6 +2867,7 @@ fill_pdcp_chain_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, } } + fc_params.meta_buf.vaddr = NULL; if (unlikely(!((flags & ROC_SE_SINGLE_BUF_INPLACE) && (flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { mdata = alloc_op_meta(&fc_params.meta_buf, m_info->mlen, m_info->pool, infl_req); From patchwork Thu Oct 20 11:14:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118784 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E67BA0552; Thu, 20 Oct 2022 13:15:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A176042D5D; Thu, 20 Oct 2022 13:15:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AE65942D5D for ; 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Thu, 20 Oct 2022 04:15:07 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:15:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Oct 2022 04:15:06 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 5F35D3F707D; Thu, 20 Oct 2022 04:15:04 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 12/13] crypto/cnxk: verify IV length during session create Date: Thu, 20 Oct 2022 16:44:52 +0530 Message-ID: <20221020111453.1982947-6-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: L1A6i6t8SaGFyPlzrTMvanZPa1NCZy3h X-Proofpoint-ORIG-GUID: L1A6i6t8SaGFyPlzrTMvanZPa1NCZy3h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph For Kasumi cipher operation, IV is a must. Verify the arg provided in session creation and remove datapath check. Coverity issue: 381020 381019 Fixes: 7a59ccc1b502 ("crypto/cnxk: remove extra indirection for FC and Kasumi") Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_se.h | 44 ++++++++++++++--------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index ac97b864b9..4675512bbc 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1753,35 +1753,17 @@ cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, auth_data_len = ROC_SE_AUTH_DLEN(d_lens); se_ctx = params->ctx; + iv_s = params->iv_buf; flags = se_ctx->zsk_flags; mac_len = se_ctx->mac_len; - if (flags == 0x0) - iv_s = params->iv_buf; - else - iv_s = params->auth_iv_buf; - dir = iv_s[8] & 0x1; - cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_SE_DMA_MODE; - - /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */ - cpt_inst_w4.s.opcode_minor = ((1 << 6) | (se_ctx->k_ecb << 5) | - (dir << 4) | (0 << 3) | (flags & 0x7)); - - /* - * GP op header, lengths are expected in bits. - */ - cpt_inst_w4.s.param1 = encr_data_len; - cpt_inst_w4.s.param2 = auth_data_len; - - /* consider iv len */ if (flags == 0x0) { + /* Consider IV len */ encr_offset += iv_len; auth_offset += iv_len; - } - if (flags == 0x0) { inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8); outputlen = inputlen; /* iv offset is 0 */ @@ -1803,6 +1785,15 @@ cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, } } + cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_KASUMI | ROC_SE_DMA_MODE; + + /* Indicate ECB/CBC, direction, CTX from CPTR, IV from DPTR */ + cpt_inst_w4.s.opcode_minor = + ((1 << 6) | (se_ctx->k_ecb << 5) | (dir << 4) | (0 << 3) | (flags & 0x7)); + + cpt_inst_w4.s.param1 = encr_data_len; + cpt_inst_w4.s.param2 = auth_data_len; + inst->w4.u64 = cpt_inst_w4.u64; if (is_sg_ver2) sg2_inst_prep(params, inst, offset_ctrl, iv_s, iv_len, 0, 0, inputlen, outputlen, 0, @@ -2017,6 +2008,8 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) case RTE_CRYPTO_CIPHER_KASUMI_F8: if (sess->chained_op) return -ENOTSUP; + if (c_form->iv.length != 8) + return -EINVAL; enc_type = ROC_SE_KASUMI_F8_ECB; cipher_key_len = 16; zsk_flag = ROC_SE_K_F8; @@ -2433,15 +2426,12 @@ fill_fc_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, fc_params.mac_buf.size = 0; fc_params.mac_buf.vaddr = 0; - if (likely(sess->iv_length)) { + if (likely(is_kasumi || sess->iv_length)) { flags |= ROC_SE_VALID_IV_BUF; - fc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, - sess->iv_offset); + fc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset); if (!is_aead && sess->aes_ctr && unlikely(sess->iv_length != 16)) { memcpy((uint8_t *)iv_buf, - rte_crypto_op_ctod_offset(cop, uint8_t *, - sess->iv_offset), - 12); + rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 12); iv_buf[3] = rte_cpu_to_be_32(0x1); fc_params.iv_buf = iv_buf; } @@ -3017,7 +3007,7 @@ fill_digest_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, /* Store it at end of auth iv */ iv_buf[8] = direction; - params.auth_iv_buf = iv_buf; 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Thu, 20 Oct 2022 04:15:08 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 8829D3F7091; Thu, 20 Oct 2022 04:15:06 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 13/13] crypto/cnxk: remove dead code Date: Thu, 20 Oct 2022 16:44:53 +0530 Message-ID: <20221020111453.1982947-7-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8aKxazLl16zObxhTTY6DkKgE99SBWTo6 X-Proofpoint-ORIG-GUID: 8aKxazLl16zObxhTTY6DkKgE99SBWTo6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Coverity issue: 381022 Fixes: d94414d1627f ("crypto/cnxk: separate out PDCP cipher datapath") Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_se.h | 38 ++++++++++++++--------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 4675512bbc..47516592a3 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -2675,6 +2675,8 @@ fill_pdcp_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, fc_params.dst_iov = fc_params.src_iov = (void *)src; prepare_iov_from_pkt_inplace(m_src, &fc_params, &flags); } else { + uint32_t pkt_len; + /* Out of place processing */ fc_params.src_iov = (void *)src; fc_params.dst_iov = (void *)dst; @@ -2686,33 +2688,23 @@ fill_pdcp_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, goto err_exit; } - if (unlikely(m_dst != NULL)) { - uint32_t pkt_len; - - /* Try to make room as much as src has */ - pkt_len = rte_pktmbuf_pkt_len(m_dst); - - if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) { - pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len; - if (!rte_pktmbuf_append(m_dst, pkt_len)) { - plt_dp_err("Not enough space in " - "m_dst %p, need %u" - " more", - m_dst, pkt_len); - ret = -EINVAL; - goto err_exit; - } - } + /* Try to make room as much as src has */ + pkt_len = rte_pktmbuf_pkt_len(m_dst); - if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) { - plt_dp_err("Prepare dst iov failed for " - "m_dst %p", - m_dst); + if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) { + pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len; + if (unlikely(rte_pktmbuf_append(m_dst, pkt_len) == NULL)) { + plt_dp_err("Not enough space in m_dst %p, need %u more", m_dst, + pkt_len); ret = -EINVAL; goto err_exit; } - } else { - fc_params.dst_iov = (void *)src; + } + + if (unlikely(prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0))) { + plt_dp_err("Prepare dst iov failed for m_dst %p", m_dst); + ret = -EINVAL; + goto err_exit; } }