From patchwork Wed Sep 21 16:28:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 116585 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29A62A00C3; Wed, 21 Sep 2022 18:29:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC41140691; Wed, 21 Sep 2022 18:29:00 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 2E2F74067C for ; Wed, 21 Sep 2022 18:28:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663777738; x=1695313738; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=reGO35qZV6Plf7RAF6oJNjy9L6mb6C8mBWTTy2NQfvo=; b=RHIoaLX2Yg2rv+YLmnzvvxqBO/MbFkUkb+vU3lXrn2kjwNlc3jLqUSmo jn8eO6HBw7ZDTi48GKjP5ptXPezwzO3+B1IrkizUPNbdUKMPKFRXhi1Ww CnYVLp7CpOxYYFikJ4HpGDfESUvFcfbATIaKFT1zGqpVMyfb/czygXDWF 31nGzmbHMp9w210Njn/Py1U8g+r94VIcfIFgZZI7Xrzy8vaokCN2YhfJg 0HqYedmUsUH+IuM0DGb0CrGY7wo4DeaFsNy2fN1/mLPEfxdeRJxdwJKJm QaN3p5EcChKD8VuAVRENzKOu1s23fR22+UFkwu00+6oHoRIczK1l3Agip A==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="301456469" X-IronPort-AV: E=Sophos;i="5.93,333,1654585200"; d="scan'208";a="301456469" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 09:28:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,333,1654585200"; d="scan'208";a="948222382" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmsmga005.fm.intel.com with ESMTP; 21 Sep 2022 09:28:55 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, rashmi.shetty@intel.com, pravin.pathak@intel.com, mike.ximing.chen@intel.com, timothy.mcdaniel@intel.com, shivani.doneria@intel.com, tirthendu.sarkar@intel.com, Abdullah Sevincer Subject: [PATCH v3] event/dlb2: fix max cq_depth/enq_depth cli override Date: Wed, 21 Sep 2022 11:28:53 -0500 Message-Id: <20220921162853.739427-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921161911.737899-1-abdullah.sevincer@intel.com> References: <20220921161911.737899-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch addresses an issue of enqueuing more than max_enq_depth and not able to dequeuing events equal to max_cq_depth in a single call of rte_event_enqueue_burst and rte_event_dequeue_burst. Apply fix for restricting enqueue of events to max_enq_depth so that in a single rte_event_enqueue_burst() call at most max_enq_depth events are enqueued. Also set per port and domain history list sizes based on cq_depth. This results in dequeing correct number of events as set by max_cq_depth. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 5a443acff8..e8c21c41fd 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -813,7 +813,7 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2, cfg->num_ldb_queues; cfg->num_hist_list_entries = resources_asked->num_ldb_ports * - DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; + evdev_dlb2_default_info.max_event_port_dequeue_depth; if (device_version == DLB2_HW_V2_5) { DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\n", @@ -1538,7 +1538,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2, cfg.cq_depth = rte_align32pow2(dequeue_depth); cfg.cq_depth_threshold = 1; - cfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; + cfg.cq_history_list_size = cfg.cq_depth; cfg.cos_id = ev_port->cos_id; cfg.cos_strict = 0;/* best effots */ @@ -2966,6 +2966,7 @@ __dlb2_event_enqueue_burst(void *event_port, struct dlb2_port *qm_port = &ev_port->qm_port; struct process_local_port_data *port_data; int retries = ev_port->enq_retries; + int num_tx; int i; RTE_ASSERT(ev_port->enq_configured); @@ -2974,8 +2975,8 @@ __dlb2_event_enqueue_burst(void *event_port, i = 0; port_data = &dlb2_port[qm_port->id][PORT_TYPE(qm_port)]; - - while (i < num) { + num_tx = RTE_MIN(num, ev_port->conf.enqueue_depth); + while (i < num_tx) { uint8_t sched_types[DLB2_NUM_QES_PER_CACHE_LINE]; uint8_t queue_ids[DLB2_NUM_QES_PER_CACHE_LINE]; int pop_offs = 0;