From patchwork Tue Aug 30 20:00:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honnappa Nagarahalli X-Patchwork-Id: 115664 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D1225A00C5; Tue, 30 Aug 2022 22:00:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4D0740F18; Tue, 30 Aug 2022 22:00:47 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id B569D40F17; Tue, 30 Aug 2022 22:00:46 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58FD71042; Tue, 30 Aug 2022 13:00:52 -0700 (PDT) Received: from 2p2660v4-1.austin.arm.com (2p2660v4-1.austin.arm.com [10.118.13.211]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1535F3F7B4; Tue, 30 Aug 2022 13:00:46 -0700 (PDT) From: Honnappa Nagarahalli To: dev@dpdk.org, honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com, matan@nvidia.com, shahafs@nvidia.com, viacheslavo@nvidia.com Cc: nd@arm.com, matan@mellanox.com, stable@dpdk.org Subject: [PATCH v2] net/mlx5: use just sufficient barrier for Arm platforms Date: Tue, 30 Aug 2022 15:00:38 -0500 Message-Id: <20220830200038.1694160-1-honnappa.nagarahalli@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210606164948.35997-1-honnappa.nagarahalli@arm.com> References: <20210606164948.35997-1-honnappa.nagarahalli@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org cqe->op_own indicates if the CQE is owned by the NIC. The rest of the fields in CQE should be read only after op_own is read. On Arm platforms using "dmb ishld" is sufficient to enforce this. Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error handling") Cc: matan@mellanox.com Cc: stable@dpdk.org Signed-off-by: Honnappa Nagarahalli Reviewed-by: Ruifeng Wang --- drivers/common/mlx5/mlx5_common.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 5028a05b49..ac2e85b15f 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -195,7 +195,11 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) return MLX5_CQE_STATUS_HW_OWN; - rte_io_rmb(); + /* Prevent speculative reading of other fields in CQE until + * CQE is valid. + */ + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + if (unlikely(op_code == MLX5_CQE_RESP_ERR || op_code == MLX5_CQE_REQ_ERR)) return MLX5_CQE_STATUS_ERR;