From patchwork Thu Jul 7 17:04:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 113780 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F066FA0540; Thu, 7 Jul 2022 11:06:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DDA0940A7B; Thu, 7 Jul 2022 11:06:50 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 970CD406B4 for ; Thu, 7 Jul 2022 11:06:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657184809; x=1688720809; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VsTV8pH3ZUn48D4FtM0sk0afEWrPhLF0rdhqE8z3Gfk=; b=TQpTsiq8tOTYUGEAa0prydSdlzHYqw2ouwMJuBwvjSKLTUekS4/9kFF5 4cU+3tPcI3/c1I0ApihVnJnbOprE/IeK+u69N8cRwkygwS8tjC1NApGP8 YkLI+g4lQfHFq1+SK5dcAbLxPw/EJSXjznt4NS0JQ0k8YO2jC7eRHdWM9 Vo2E1fhSv0WWvHPeS182RitJIu1M7ny+KUhbkxYaV8XfpCKjF4Vi5Nqmm MPdMt7xtEktgC+mLvnyu8ClBawvIWnUT5OKr9Hcp8NCKWf7+2nmGFD3Na QmEkvwzoe8B4ep9Ws9zV+Z4076nepLP0LYs9AR0cbVaW4H90Ly9d9RLOC g==; X-IronPort-AV: E=McAfee;i="6400,9594,10400"; a="347958319" X-IronPort-AV: E=Sophos;i="5.92,252,1650956400"; d="scan'208";a="347958319" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 02:06:33 -0700 X-IronPort-AV: E=Sophos;i="5.92,252,1650956400"; d="scan'208";a="651054106" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 02:06:31 -0700 From: Kevin Liu To: dev@dpdk.org Cc: beilei.xing@intel.com, Yuying.Zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH v4] net/i40e: restore disable double VLAN by default Date: Thu, 7 Jul 2022 17:04:34 +0000 Message-Id: <20220707170434.2159759-1-kevinx.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220707104732.1816933-1-kevinx.liu@intel.com> References: <20220707104732.1816933-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously, QinQ is enabled by default and can't be disabled, but there'll be performance drop if QinQ is enabled. So, disable QinQ by default. Fixes: ae97b8b89826 ("net/i40e: fix error disable double VLAN") Signed-off-by: Kevin Liu Acked-by: Beilei Xing --- v2: update doc and refine commit log --- v3: refine commit log --- v4: update doc --- doc/guides/nics/i40e.rst | 13 ++++++++----- drivers/net/i40e/i40e_ethdev.c | 12 ------------ 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index 85fdc4944d..d5938fa8e4 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -969,11 +969,14 @@ it will fail and return the info "Conflict with the first rule's input set", which means the current rule's input set conflicts with the first rule's. Remove the first rule if want to change the input set of the PCTYPE. -Disable QinQ is not supported when FW >= 8.4 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -If upgrade FW to version 8.4 and higher, enable QinQ by default and disable QinQ is not supported. - +Vlan related Features miss when FW >= 8.4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If FW version >= 8.4, there'll be some Vlan related issues: +1. TCI input set for QinQ is invalid. +2. Fail to configure TPID for QinQ. +3. Need to enable QinQ before enabling Vlan filter. +4. Fail to strip outer Vlan. Example of getting best performance with l3fwd example ------------------------------------------------------ diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 684e095026..117dd85c11 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -4027,12 +4027,6 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) } if (mask & RTE_ETH_VLAN_EXTEND_MASK) { - /* Double VLAN not allowed to be disabled.*/ - if (pf->fw8_3gt && !(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { - PMD_DRV_LOG(WARNING, - "Disable double VLAN is not allowed after firmwarev8.3!"); - return 0; - } i = 0; num = vsi->mac_num; mac_filter = rte_zmalloc("mac_filter_info_data", @@ -6296,7 +6290,6 @@ int i40e_vsi_cfg_inner_vlan_stripping(struct i40e_vsi *vsi, bool on) static int i40e_dev_init_vlan(struct rte_eth_dev *dev) { - struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_eth_dev_data *data = dev->data; int ret; int mask = 0; @@ -6307,11 +6300,6 @@ i40e_dev_init_vlan(struct rte_eth_dev *dev) RTE_ETH_VLAN_FILTER_MASK | RTE_ETH_VLAN_EXTEND_MASK; - /* Double VLAN be enabled by default.*/ - if (pf->fw8_3gt) { - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; - rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; - } ret = i40e_vlan_offload_set(dev, mask); if (ret) { PMD_DRV_LOG(INFO, "Failed to update vlan offload");