From patchwork Thu May 26 00:55:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111866 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4449AA0548; Thu, 26 May 2022 03:04:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C0BD44067B; Thu, 26 May 2022 03:04:29 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id F109040146; Thu, 26 May 2022 03:04:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653527067; x=1685063067; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=kbK4Q1BQ6WkHndgLrdzVnCfWf4jFzb8itFrx1CEfqrI=; b=iAAlJgNma1xZXRwg3OJluGH1+I1EUcxie0sK+2647jsQ9ZXd++5bJf0L WylNjPPgHow3Nz7aL+FD94U3M0zpKCWXMFko9a2clY2Egkubztkowct3N N9E2nhEwx9n7ZuvhCZwj1PC9k+53qWiFxq1j5Hi+FCtT7QV7+ftAri+YE yr0FeIr/PyjI+wg4ITjxtt4wpCyBm/Bl4KG/ZmZw5m/69nw5oucoXEMKn 45M/dFFlR/8FhnECIesSdXGF8084iStxCdC3SWETi7wXktDPNRTia6glk j0I8gWBRJB1HMuG5uhnRnsvem2PUdrYmg8KtLTMtjCF9EPGuc99qCRzeZ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="274089446" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="274089446" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 18:04:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="549294863" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga006.jf.intel.com with ESMTP; 25 May 2022 18:04:23 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru , stable@dpdk.org Subject: [PATCH v6 1/5] baseband/acc100: update companion PF configure function Date: Wed, 25 May 2022 17:55:19 -0700 Message-Id: <1653526523-68839-2-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update of the device configuration function from PF used for bbdev-test to latest sequence for ACC199 PRQ device and matching version in pf_bb_config 22.03. Fixes: b17d70922d5d ("baseband/acc100: add configure function") Cc: stable@dpdk.org Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++ drivers/baseband/acc100/rte_acc100_pmd.c | 150 ++++++++++++++++++++++++------- drivers/baseband/acc100/rte_acc100_pmd.h | 15 ++++ 3 files changed, 151 insertions(+), 32 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h index a1ee416..2fba667 100644 --- a/drivers/baseband/acc100/acc100_pf_enum.h +++ b/drivers/baseband/acc100/acc100_pf_enum.h @@ -238,6 +238,24 @@ enum { HWPfPermonBTotalLatLowBusMon = 0x00BAC504, HWPfPermonBTotalLatUpperBusMon = 0x00BAC508, HWPfPermonBTotalReqCntBusMon = 0x00BAC50C, + HwPfFabI2MArbCntrlReg = 0x00BB0000, + HWPfFabricMode = 0x00BB1000, + HwPfFabI2MGrp0DebugReg = 0x00BBF000, + HwPfFabI2MGrp1DebugReg = 0x00BBF004, + HwPfFabI2MGrp2DebugReg = 0x00BBF008, + HwPfFabI2MGrp3DebugReg = 0x00BBF00C, + HwPfFabI2MBuf0DebugReg = 0x00BBF010, + HwPfFabI2MBuf1DebugReg = 0x00BBF014, + HwPfFabI2MBuf2DebugReg = 0x00BBF018, + HwPfFabI2MBuf3DebugReg = 0x00BBF01C, + HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020, + HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024, + HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028, + HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C, + HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030, + HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034, + HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038, + HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C, HWPfFecUl5gCntrlReg = 0x00BC0000, HWPfFecUl5gI2MThreshReg = 0x00BC0004, HWPfFecUl5gVersionReg = 0x00BC0100, diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index de7e4bc..9135c0e 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) { rte_bbdev_log(INFO, "rte_acc100_configure"); uint32_t value, address, status; - int qg_idx, template_idx, vf_idx, acc, i; + int qg_idx, template_idx, vf_idx, acc, i, j; struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); /* Compile time checks */ @@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) /* Store configuration */ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf)); + value = acc100_reg_read(d, HwPfPcieGpexBridgeControl); + bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE); + /* PCIe Bridge configuration */ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE); for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++) @@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) value = 1; acc100_reg_write(d, address, value); - /* DDR Configuration */ - address = HWPfDdrBcTim6; - value = acc100_reg_read(d, address); - value &= 0xFFFFFFFB; /* Bit 2 */ -#ifdef ACC100_DDR_ECC_ENABLE - value |= 0x4; -#endif - acc100_reg_write(d, address, value); - address = HWPfDdrPhyDqsCountNum; -#ifdef ACC100_DDR_ECC_ENABLE - value = 9; -#else - value = 8; -#endif + /* Enable granular dynamic clock gating */ + address = HWPfHiClkGateHystReg; + value = ACC100_CLOCK_GATING_EN; acc100_reg_write(d, address, value); /* Set default descriptor signature */ @@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) address = HWPfDmaAxcacheReg; acc100_reg_write(d, address, value); + /* Adjust PCIe Lane adaptation */ + for (i = 0; i < ACC100_QUAD_NUMS; i++) + for (j = 0; j < ACC100_LANES_PER_QUAD; j++) + acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET + + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT); + + /* Enable PCIe live adaptation */ + for (i = 0; i < ACC100_QUAD_NUMS; i++) + acc100_reg_write(d, HwPfPciePcsEqControl + + i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ); + /* Default DMA Configuration (Qmgr Enabled) */ address = HWPfDmaConfig0Reg; value = 0; @@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) value = HWPfQmgrEgressQueuesTemplate; acc100_reg_write(d, address, value); + /* Default Fabric Mode */ + address = HWPfFabricMode; + value = ACC100_FABRIC_MODE; + acc100_reg_write(d, address, value); + /* ===== Qmgr Configuration ===== */ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */ int totalQgs = conf->q_ul_4g.num_qgroups + @@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) } /* Template Priority in incremental order */ - for (template_idx = 0; template_idx < ACC100_NUM_TMPL; - template_idx++) { - address = HWPfQmgrGrpTmplateReg0Indx + - ACC100_BYTES_IN_WORD * (template_idx % 8); + for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) { + address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx; value = ACC100_TMPL_PRI_0; acc100_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg1Indx + - ACC100_BYTES_IN_WORD * (template_idx % 8); + address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx; value = ACC100_TMPL_PRI_1; acc100_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg2indx + - ACC100_BYTES_IN_WORD * (template_idx % 8); + address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx; value = ACC100_TMPL_PRI_2; acc100_reg_write(d, address, value); - address = HWPfQmgrGrpTmplateReg3Indx + - ACC100_BYTES_IN_WORD * (template_idx % 8); + address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx; value = ACC100_TMPL_PRI_3; acc100_reg_write(d, address, value); } @@ -4623,7 +4626,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) } /* Queue Group Function mapping */ - int qman_func_id[5] = {0, 2, 1, 3, 4}; + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0}; address = HWPfQmgrGrpFunction0; value = 0; for (qg_idx = 0; qg_idx < 8; qg_idx++) { @@ -4654,7 +4657,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) } } - /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */ + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */ uint32_t aram_address = 0; for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { @@ -4679,6 +4682,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) /* ==== HI Configuration ==== */ + /* No Info Ring/MSI by default */ + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0); + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0); + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF); + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF); /* Prevent Block on Transmit Error */ address = HWPfHiBlockTransmitOnErrorEn; value = 0; @@ -4691,10 +4699,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) address = HWPfHiPfMode; value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0; acc100_reg_write(d, address, value); - /* Enable Error Detection in HW */ - address = HWPfDmaErrorDetectionEn; - value = 0x3D7; - acc100_reg_write(d, address, value); /* QoS overflow init */ value = 1; @@ -4704,7 +4708,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) acc100_reg_write(d, address, value); /* HARQ DDR Configuration */ - unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */ + unsigned int ddrSizeInMb = ACC100_HARQ_DDR; for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { address = HWPfDmaVfDdrBaseRw + vf_idx * 0x10; @@ -4718,6 +4722,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) if (numEngines < (ACC100_SIG_UL_5G_LAST + 1)) poweron_cleanup(bbdev, d, conf); + uint32_t version = 0; + for (i = 0; i < 4; i++) + version += acc100_reg_read(d, + HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i); + if (version != ACC100_PRQ_DDR_VER) { + printf("* Note: Not on DDR PRQ version %8x != %08x\n", + version, ACC100_PRQ_DDR_VER); + } else if (firstCfg) { + /* ---- DDR configuration at boot up --- */ + /* Read Clear Ddr training status */ + acc100_reg_read(d, HWPfChaDdrStDoneStatus); + /* Reset PHY/IDTM/UMMC */ + acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3); + acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2); + acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2); + acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3); + acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2); + usleep(ACC100_MS_IN_US); + /* Reset WB and APB resets */ + acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2); + acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3); + /* Configure PHY-IDTM */ + acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8); + /* IDTM timing registers */ + acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13); + acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15); + acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011); + /* Configure SDRAM MRS registers */ + acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70); + acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50); + acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30); + acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00); + acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000); + /* Configure active lanes */ + acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9); + acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9); + /* Configure WR/RD leveling timing registers */ + acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212); + /* Configure what trainings to execute */ + acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c); + /* Releasing PHY reset */ + acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3); + /* Configure Memory Controller registers */ + acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3); + acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003); + acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31); + /* Configure UMMC BC timing registers */ + acc100_reg_write(d, HWPfDdrBcRef, 0xa22); + acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501); + acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476); + acc100_reg_write(d, HWPfDdrBcTim2, 0x103); + acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1); + acc100_reg_write(d, HWPfDdrBcTim4, 0x23300); + acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276); + acc100_reg_write(d, HWPfDdrBcTim6, 0x857914); + acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232); + acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce); + acc100_reg_write(d, HWPfDdrBcTim9, 0x50020); + acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee); + /* Configure UMMC DFI timing registers */ + acc100_reg_write(d, HWPfDdrDfiInit, 0x5000); + acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006); + acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305); + acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1); + acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f); + /* Release IDTM CPU out of reset */ + acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2); + /* Wait PHY-IDTM to finish static training */ + for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) { + usleep(ACC100_MS_IN_US); + value = acc100_reg_read(d, + HWPfChaDdrStDoneStatus); + if (value & 1) + break; + } + printf("DDR Training completed in %d ms", i); + /* Enable Memory Controller */ + acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401); + /* Release AXI interface reset */ + acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3); + } + rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name); return 0; } diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h index cbcece2..8fea322 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.h +++ b/drivers/baseband/acc100/rte_acc100_pmd.h @@ -153,6 +153,12 @@ #define ACC100_CFG_QMGR_HI_P 0x0F0F #define ACC100_CFG_PCI_AXI 0xC003 #define ACC100_CFG_PCI_BRIDGE 0x40006033 +#define ACC100_QUAD_NUMS 4 +#define ACC100_LANES_PER_QUAD 4 +#define ACC100_PCIE_LANE_OFFSET 0x200 +#define ACC100_PCIE_QUAD_OFFSET 0x2000 +#define ACC100_PCS_EQ 0x6007 +#define ACC100_ADAPT 0x8400 #define ACC100_ENGINE_OFFSET 0x1000 #define ACC100_RESET_HI 0x20100 #define ACC100_RESET_LO 0x20000 @@ -160,6 +166,15 @@ #define ACC100_ENGINES_MAX 9 #define ACC100_LONG_WAIT 1000 #define ACC100_GPEX_AXIMAP_NUM 17 +#define ACC100_CLOCK_GATING_EN 0x30000 +#define ACC100_FABRIC_MODE 0xB +/* DDR Size per VF - 512MB by default + * Can be increased up to 4 GB with single PF/VF + */ +#define ACC100_HARQ_DDR (512 * 1) +#define ACC100_PRQ_DDR_VER 0x10092020 +#define ACC100_MS_IN_US (1000) +#define ACC100_DDR_TRAINING_MAX (5000) /* ACC100 DMA Descriptor triplet */ struct acc100_dma_triplet { From patchwork Thu May 26 00:55:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111867 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3CB3FA0548; Thu, 26 May 2022 03:04:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CDE5F427F5; Thu, 26 May 2022 03:04:30 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id AA07340150; Thu, 26 May 2022 03:04:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653527068; x=1685063068; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WliwIJAHSrqJX0JkohDXfNc2G2g+MqDMbxRN/NP82Og=; b=Kn5qscSjVb3t8XjKXRZulPAjEeu8e8rCO2y+M0ttrMjH1LETcNXmzaFc 2PXVqHYXl+10DG30WoArQ+J4nYMqzjkX9u4ymIlOqR7MGIQkyV98LapkP M3k7fZncsCWmHJCIJXqcHKW4NtQSUS4JXXyBLbMdbEfkdDMTm57anBs4j X2fluaU6NQ2w8iYEx2/IW+/uzlHEXQVbKGXnmXYTCQgvpNHjAFa5xj69C aetYZnEbNZ3AArz+YCsl7yL42WJthewZvnKOBHw7unP3PtcI/m8/bR8El fx8Z00Oadng+McK75/nCTYDE6vMimYlZpB0YcKnZ/aurs44UF4189sKX4 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="274089449" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="274089449" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 18:04:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="549294867" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga006.jf.intel.com with ESMTP; 25 May 2022 18:04:23 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru , stable@dpdk.org Subject: [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario Date: Wed, 25 May 2022 17:55:20 -0700 Message-Id: <1653526523-68839-3-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Catch exception in PMD in case of invalid input parameter. Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 9135c0e..3fdf17d 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1236,6 +1236,8 @@ return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c; } /* LBRM case - includes a division by N */ + if (unlikely(z_c == 0)) + return 0; if (rv_index == 1) return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb) / n) * z_c; @@ -1764,6 +1766,10 @@ /* Soft output */ if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) { + if (op->turbo_dec.soft_output.data == 0) { + rte_bbdev_log(ERR, "Soft output is not defined"); + return -1; + } if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_EQUALIZER)) *s_out_length = e; From patchwork Thu May 26 00:55:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111868 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03A72A0548; Thu, 26 May 2022 03:04:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E7FCE4281B; Thu, 26 May 2022 03:04:31 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 28A6140146 for ; Thu, 26 May 2022 03:04:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653527068; x=1685063068; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=m/UzerDGJTE88OpH6L0K1iO6hlsYrksK8WdZv1xLpZE=; b=TNmD8vYwIdewBc9mI5O+zjJrYkSQwafSmL2Vqx0LpP4H9iyGOTG+0cu/ olQq+XV9TkK/STjro04urBTfekyfocJWtS1OwgUuOKPzw3kfqcnOcDZH3 L3RJvQ9owngcbUj/2VF3+auoyfS5/ADYRQ2gYacEC0YHRw6yAkE0DrhmE +8P4SPfhoN94pFsL6HsmbIjxIDm8HfAT4/FP/xeUPu7kXFrBl/a2BHmvJ zfaab9IDoULdwhjZTG13ASDqb/urk7GsGseoAZAzZGHMsgELcWYfrwLQ9 KLk9MEbz1w1NohdK747of5JRsK9WLEb15Xe9Y78hH6LkgXBuqp1/bmgva g==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="274089452" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="274089452" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 18:04:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="549294873" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga006.jf.intel.com with ESMTP; 25 May 2022 18:04:24 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Date: Wed, 25 May 2022 17:55:21 -0700 Message-Id: <1653526523-68839-4-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support for ACC101 as a derivative of ACC100. Integrated in unified driver and reusing existing code when possible. Signed-off-by: Nicolas Chautru --- MAINTAINERS | 1 + doc/guides/bbdevs/acc100.rst | 37 +++++--- doc/guides/bbdevs/features/acc101.ini | 13 +++ doc/guides/rel_notes/release_22_07.rst | 3 + drivers/baseband/acc100/rte_acc100_pmd.c | 153 +++++++++++++++++++++++++++++-- drivers/baseband/acc100/rte_acc100_pmd.h | 11 +++ drivers/baseband/acc100/rte_acc101_pmd.h | 55 +++++++++++ 7 files changed, 254 insertions(+), 19 deletions(-) create mode 100644 doc/guides/bbdevs/features/acc101.ini create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h diff --git a/MAINTAINERS b/MAINTAINERS index 17a0559..0610128 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini F: drivers/baseband/acc100/ F: doc/guides/bbdevs/acc100.rst F: doc/guides/bbdevs/features/acc100.ini +F: doc/guides/bbdevs/features/acc101.ini Null baseband M: Nicolas Chautru diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst index 9fff6ab..ff07ed9 100644 --- a/doc/guides/bbdevs/acc100.rst +++ b/doc/guides/bbdevs/acc100.rst @@ -1,17 +1,19 @@ .. SPDX-License-Identifier: BSD-3-Clause Copyright(c) 2020 Intel Corporation -Intel(R) ACC100 5G/4G FEC Poll Mode Driver -========================================== +Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers +====================================================== The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an implementation of a VRAN FEC wireless acceleration function. This device is also known as Mount Bryce. +The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce +with functional and capacity improvements but still with the same exposed BBDEV capabilities. Features -------- -ACC100 5G/4G FEC PMD supports the following features: +ACC100 and ACC101 5G/4G FEC PMDs support the following features: - LDPC Encode in the DL (5GNR) - LDPC Decode in the UL (5GNR) @@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features: - MSI - SR-IOV -ACC100 5G/4G FEC PMD supports the following BBDEV capabilities: +ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities: * For the LDPC encode operation: - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s) @@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using: Initialization -------------- -When the device first powers up, its PCI Physical Functions (PF) can be listed through this command: +When the device first powers up, its PCI Physical Functions (PF) can be listed through these +commands for ACC100 and ACC101 respectively: .. code-block:: console sudo lspci -vd8086:0d5c + sudo lspci -vd8086:57c4 The physical and virtual functions are compatible with Linux UIO drivers: -``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G +``vfio`` and ``igb_uio``. However, in order to work the 5G/4G FEC device first needs to be bound to one of these linux drivers through DPDK. @@ -97,7 +101,8 @@ Bind PF UIO driver(s) Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver. -The igb_uio driver may be bound to the PF PCI device using one of two methods: +The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100 +(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``): 1. PCI functions (physical or virtual, depending on the use case) can be bound to @@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function. where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c -In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device. +In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device. Enable Virtual Functions @@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the device to perform FEC functions. This configuration needs to be executed at least once after reboot or PCI FLR and can -be achieved by using the function ``acc100_configure()``, which sets up the -parameters defined in ``acc100_conf`` structure. +be achieved by using the functions ``acc100_configure()`` or ``acc101_configure()``, +which sets up the parameters defined in the compatible ``acc100_conf`` structure. Test Application ---------------- BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing -the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's +the functionality of the device 5G/4G FEC encode and decode, depending on the device's capabilities. The test application is located under app->test-bbdev folder and has the following options: @@ -212,7 +217,7 @@ Test Vectors In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides a range of additional tests under the test_vectors folder, which may be useful. The results -of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some +of these tests will depend on the device 5G/4G FEC capabilities which may cause some testcases to be skipped, but no failure should be reported. @@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used: ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data + +Specifically for the BBDEV ACC101 PMD, the command below can be used: + +.. code-block:: console + + ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data + diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini new file mode 100644 index 0000000..0e2c21a --- /dev/null +++ b/doc/guides/bbdevs/features/acc101.ini @@ -0,0 +1,13 @@ +; +; Supported features of the 'acc101' bbdev driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Turbo Decoder (4G) = Y +Turbo Encoder (4G) = Y +LDPC Decoder (5G) = Y +LDPC Encoder (5G) = Y +LLR/HARQ Compression = Y +External DDR Access = Y +HW Accelerated = Y diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index e49cace..1803947 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -104,6 +104,9 @@ New Features * ``RTE_EVENT_QUEUE_ATTR_WEIGHT`` * ``RTE_EVENT_QUEUE_ATTR_AFFINITY`` +* **Added Intel ACC101 baseband PMD.** + + * Added a new baseband PMD for Intel ACC101 device. Removed Items ------------- diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 3fdf17d..6a2123b 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -22,6 +22,7 @@ #include #include #include "rte_acc100_pmd.h" +#include "rte_acc101_pmd.h" #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1133,7 +1134,10 @@ /* ACC100 PCI PF address map */ static struct rte_pci_id pci_id_acc100_pf_map[] = { { - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID) + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID), + }, + { + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID), }, {.device_id = 0}, }; @@ -1141,7 +1145,10 @@ /* ACC100 PCI VF address map */ static struct rte_pci_id pci_id_acc100_vf_map[] = { { - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID) + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID), + }, + { + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID), }, {.device_id = 0}, }; @@ -1290,7 +1297,7 @@ /* Fill in a frame control word for LDPC decoding. */ static inline void -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, union acc100_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; @@ -1414,6 +1421,128 @@ } } +/* Convert offset to harq index for harq_layout structure */ +static inline uint32_t hq_index(uint32_t offset) +{ + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK; +} + +/* Fill in a frame control word for LDPC decoding for ACC101 */ +static inline void +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, + union acc100_harq_layout_data *harq_layout) +{ + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; + uint32_t harq_index; + uint32_t l; + + fcw->qm = op->ldpc_dec.q_m; + fcw->nfiller = op->ldpc_dec.n_filler; + fcw->BG = (op->ldpc_dec.basegraph - 1); + fcw->Zc = op->ldpc_dec.z_c; + fcw->ncb = op->ldpc_dec.n_cb; + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph, + op->ldpc_dec.rv_index); + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK) + fcw->rm_e = op->ldpc_dec.cb_params.e; + else + fcw->rm_e = (op->ldpc_dec.tb_params.r < + op->ldpc_dec.tb_params.cab) ? + op->ldpc_dec.tb_params.ea : + op->ldpc_dec.tb_params.eb; + + if (unlikely(check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + (op->ldpc_dec.harq_combined_input.length == 0))) { + rte_bbdev_log(WARNING, "Null HARQ input size provided"); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); + fcw->crc_select = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK); + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DECODE_BYPASS); + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS); + if (op->ldpc_dec.q_m == 1) { + fcw->bypass_intlv = 1; + fcw->qm = 2; + } + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_LLR_COMPRESSION); + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); + if (fcw->hcin_en > 0) { + harq_in_length = op->ldpc_dec.harq_combined_input.length; + if (fcw->hcin_decomp_mode > 0) + harq_in_length = harq_in_length * 8 / 6; + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); + fcw->hcin_size0 = harq_in_length; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } else { + fcw->hcin_size0 = 0; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } + + fcw->itmax = op->ldpc_dec.iter_max; + fcw->itstop = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); + fcw->synd_precoder = fcw->itstop; + /* + * These are all implicitly set + * fcw->synd_post = 0; + * fcw->so_en = 0; + * fcw->so_bypass_rm = 0; + * fcw->so_bypass_intlv = 0; + * fcw->dec_convllr = 0; + * fcw->hcout_convllr = 0; + * fcw->hcout_size1 = 0; + * fcw->so_it = 0; + * fcw->hcout_offset = 0; + * fcw->negstop_th = 0; + * fcw->negstop_it = 0; + * fcw->negstop_en = 0; + * fcw->gain_i = 1; + * fcw->gain_h = 1; + */ + if (fcw->hcout_en > 0) { + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; + k0_p = (fcw->k0 > parity_offset) ? + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + ncb_p = fcw->ncb - op->ldpc_dec.n_filler; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); + harq_out_length = (uint16_t) fcw->hcin_size0; + harq_out_length = RTE_MAX(harq_out_length, l); + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); + fcw->hcout_size0 = harq_out_length; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + harq_layout[harq_index].offset = fcw->hcout_offset; + harq_layout[harq_index].size0 = fcw->hcout_size0; + } else { + fcw->hcout_size0 = 0; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + } +} + /** * Fills descriptor with data pointers of one block type. * @@ -2966,7 +3095,7 @@ struct acc100_fcw_ld *fcw; uint32_t seg_total_left; fcw = &desc->req.fcw_ld; - acc100_fcw_ld_fill(op, fcw, harq_layout); + q->d->fcw_ld_fill(op, fcw, harq_layout); /* Special handling when overusing mbuf */ if (fcw->rm_e < ACC100_MAX_E_MBUF) @@ -3033,7 +3162,7 @@ desc = q->ring_addr + desc_idx; uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; union acc100_harq_layout_data *harq_layout = q->d->harq_layout; - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); + q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); input = op->ldpc_dec.input.data; h_output_head = h_output = op->ldpc_dec.hard_output.data; @@ -4145,9 +4274,19 @@ dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc; dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec; + /* Device variant specific handling */ + if ((pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) || + (pci_dev->id.device_id == RTE_ACC100_VF_DEVICE_ID)) { + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT; + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill; + } else { + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT; + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill; + } + ((struct acc100_device *) dev->data->dev_private)->pf_device = - !strcmp(drv->driver.name, - RTE_STR(ACC100PF_DRIVER_NAME)); + !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME)); + ((struct acc100_device *) dev->data->dev_private)->mmio_base = pci_dev->mem_resource[0].addr; diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h index 8fea322..39d5f22 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.h +++ b/drivers/baseband/acc100/rte_acc100_pmd.h @@ -22,6 +22,9 @@ #define rte_bbdev_log_debug(fmt, ...) #endif +#define ACC100_VARIANT 0 +#define ACC101_VARIANT 1 + /* ACC100 PF and VF driver names */ #define ACC100PF_DRIVER_NAME intel_acc100_pf #define ACC100VF_DRIVER_NAME intel_acc100_vf @@ -67,6 +70,8 @@ #define ACC100_HARQ_LAYOUT (64*1024*1024) /* Assume offset for HARQ in memory */ #define ACC100_HARQ_OFFSET (32*1024) +#define ACC100_HARQ_OFFSET_SHIFT 15 +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff /* Mask used to calculate an index in an Info Ring array (not a byte offset) */ #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1) /* Number of Virtual Functions ACC100 supports */ @@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue { struct acc100_device *d; }; +typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op, + struct acc100_fcw_ld *fcw, + union acc100_harq_layout_data *harq_layout); + /* Private data structure for each ACC100 device */ struct acc100_device { void *mmio_base; /**< Base address of MMIO registers (BAR0) */ @@ -605,6 +614,8 @@ struct acc100_device { uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS]; bool pf_device; /**< True if this is a PF ACC100 device */ bool configured; /**< True if this ACC100 device is configured */ + uint16_t device_variant; /**< Device variant */ + acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */ }; /** diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h new file mode 100644 index 0000000..8f1f4ab --- /dev/null +++ b/drivers/baseband/acc100/rte_acc101_pmd.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + */ + +/* ACC101 PCI vendor & device IDs */ +#define RTE_ACC101_VENDOR_ID (0x8086) +#define RTE_ACC101_PF_DEVICE_ID (0x57c4) +#define RTE_ACC101_VF_DEVICE_ID (0x57c5) + +/* Define as 1 to use only a single FEC engine */ +#ifndef RTE_ACC101_SINGLE_FEC +#define RTE_ACC101_SINGLE_FEC 0 +#endif + +/* Number of Virtual Functions ACC101 supports */ +#define ACC101_NUM_VFS 16 +#define ACC101_NUM_QGRPS 8 +#define ACC101_NUM_AQS 16 +/* All ACC101 Registers alignment are 32bits = 4B */ +#define ACC101_BYTES_IN_WORD 4 + +#define ACC101_TMPL_PRI_0 0x03020100 +#define ACC101_TMPL_PRI_1 0x07060504 +#define ACC101_TMPL_PRI_2 0x0b0a0908 +#define ACC101_TMPL_PRI_3 0x0f0e0d0c +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4) + +#define ACC101_NUM_TMPL 32 +/* Mapping of signals for the available engines */ +#define ACC101_SIG_UL_5G 0 +#define ACC101_SIG_UL_5G_LAST 8 +#define ACC101_SIG_DL_5G 13 +#define ACC101_SIG_DL_5G_LAST 15 +#define ACC101_SIG_UL_4G 16 +#define ACC101_SIG_UL_4G_LAST 19 +#define ACC101_SIG_DL_4G 27 +#define ACC101_SIG_DL_4G_LAST 31 +#define ACC101_NUM_ACCS 5 +#define ACC101_PF_VAL 2 + +/* ACC101 Configuration */ +#define ACC101_CFG_DMA_ERROR 0x3D7 +#define ACC101_CFG_AXI_CACHE 0x11 +#define ACC101_CFG_QMGR_HI_P 0x0F0F +#define ACC101_CFG_PCI_AXI 0xC003 +#define ACC101_CFG_PCI_BRIDGE 0x40006033 +#define ACC101_ENGINE_OFFSET 0x1000 +#define ACC101_LONG_WAIT 1000 +#define ACC101_GPEX_AXIMAP_NUM 17 +#define ACC101_CLOCK_GATING_EN 0x30000 +#define ACC101_DMA_INBOUND 0x104 +/* DDR Size per VF - 512MB by default + * Can be increased up to 4 GB with single PF/VF + */ +#define ACC101_HARQ_DDR (512 * 1) From patchwork Thu May 26 00:55:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111869 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69FE0A0548; Thu, 26 May 2022 03:04:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA46242B6D; Thu, 26 May 2022 03:04:32 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 8CE4040150 for ; Thu, 26 May 2022 03:04:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653527068; x=1685063068; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=qz7cl5cAeiostfqsmc8K0TOFKiOW5752fz69WVYUqtY=; b=kwovt/Sus/5vUUUoN5D0pge0v1fwD1xoIGrt1KNfy60VIKnIjlN5BU4V BkV27UV9z8px8AVVuDt+GNd/n/QOo9pv1i3Wm41YWRX/pkp6K6x5xy/RH ybMMmQ+91X+tMHRmkFEdCuc+0Xw122Av531Jy5judJgFduqsSWov/xbJA uTUaUPoaK4SuZThtJST2NXzumpkHVuPyMMcKO6pfNUwJ2JYyQ3gXy86k6 VMarHuT88B66eT6Q++YXiDe0KQMF7Yh9ag2haGAOcGhsDIhptUqICedUR IelEnofw9N288njZ9x8Betet4f1cMuo2zxhYjwa2Trh8z9j2wcmeTyyQu w==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="274089456" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="274089456" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 18:04:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="549294878" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga006.jf.intel.com with ESMTP; 25 May 2022 18:04:24 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v6 4/5] baseband/acc100: modify validation code for ACC101 Date: Wed, 25 May 2022 17:55:22 -0700 Message-Id: <1653526523-68839-5-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The validation requirement is different for the two devices. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/rte_acc100_pmd.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 6a2123b..a057edf 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1295,6 +1295,21 @@ RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } +#ifdef RTE_LIBRTE_BBDEV_DEBUG + +static inline bool +is_acc100(struct acc100_queue *q) +{ + return (q->d->device_variant == ACC100_VARIANT); +} + +static inline bool +validate_op_required(struct acc100_queue *q) +{ + return is_acc100(q); +} +#endif + /* Fill in a frame control word for LDPC decoding. */ static inline void acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, @@ -2182,8 +2197,10 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validates turbo encoder parameters */ static inline int -validate_enc_op(struct rte_bbdev_enc_op *op) +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc; struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL; struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL; @@ -2320,8 +2337,10 @@ static inline uint32_t hq_index(uint32_t offset) } /* Validates LDPC encoder parameters */ static inline int -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; if (op->mempool == NULL) { @@ -2373,8 +2392,10 @@ static inline uint32_t hq_index(uint32_t offset) /* Validates LDPC decoder parameters */ static inline int -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; if (op->mempool == NULL) { @@ -2429,7 +2450,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_enc_op(op) == -1) { + if (validate_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo encoder validation failed"); return -EINVAL; } @@ -2483,7 +2504,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_enc_op(ops[0]) == -1) { + if (validate_ldpc_enc_op(ops[0], q) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation failed"); return -EINVAL; } @@ -2545,7 +2566,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_enc_op(op) == -1) { + if (validate_ldpc_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation failed"); return -EINVAL; } @@ -2602,7 +2623,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_enc_op(op) == -1) { + if (validate_enc_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo encoder validation failed"); return -EINVAL; } @@ -2675,8 +2696,10 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validates turbo decoder parameters */ static inline int -validate_dec_op(struct rte_bbdev_dec_op *op) +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) { + if (!validate_op_required(q)) + return 0; struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec; struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL; struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL; @@ -2822,7 +2845,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_dec_op(op) == -1) { + if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation failed"); return -EINVAL; } @@ -3047,7 +3070,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_dec_op(op) == -1) { + if (validate_ldpc_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC decoder validation failed"); return -EINVAL; } @@ -3151,7 +3174,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_ldpc_dec_op(op) == -1) { + if (validate_ldpc_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "LDPC decoder validation failed"); return -EINVAL; } @@ -3241,7 +3264,7 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ - if (validate_dec_op(op) == -1) { + if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation failed"); return -EINVAL; } From patchwork Thu May 26 00:55:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111870 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B4F4A0548; Thu, 26 May 2022 03:05:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B07242B70; Thu, 26 May 2022 03:04:34 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id B77514067B for ; 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25 May 2022 18:04:24 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Date: Wed, 25 May 2022 17:55:23 -0700 Message-Id: <1653526523-68839-6-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding companion function common to ACC100/ACC101 which can be called from bbdev-test when running from PF. Signed-off-by: Nicolas Chautru --- app/test-bbdev/test_bbdev_perf.c | 6 +- drivers/baseband/acc100/rte_acc100_cfg.h | 4 +- drivers/baseband/acc100/rte_acc100_pmd.c | 323 ++++++++++++++++++++++++++++++- drivers/baseband/acc100/version.map | 3 +- 4 files changed, 327 insertions(+), 9 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 0fa119a..718e5ef 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -711,11 +711,11 @@ typedef int (test_case_function)(struct active_device *ad, #endif #ifdef RTE_BASEBAND_ACC100 if ((get_init_device() == true) && - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { + (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { struct rte_acc100_conf conf; unsigned int i; - printf("Configure ACC100 FEC Driver %s with default values\n", + printf("Configure ACC100/ACC101 FEC Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ @@ -760,7 +760,7 @@ typedef int (test_case_function)(struct active_device *ad, conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; /* setup PF with configuration information */ - ret = rte_acc100_configure(info->dev_name, &conf); + ret = rte_acc10x_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, "Failed to configure ACC100 PF for bbdev %s", info->dev_name); diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h index d233e42..b70803d 100644 --- a/drivers/baseband/acc100/rte_acc100_cfg.h +++ b/drivers/baseband/acc100/rte_acc100_cfg.h @@ -90,7 +90,7 @@ struct rte_acc100_conf { }; /** - * Configure a ACC100 device + * Configure a ACC100/ACC101 device in PF mode notably for bbdev-test * * @param dev_name * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. @@ -104,7 +104,7 @@ struct rte_acc100_conf { */ __rte_experimental int -rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf); +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf); #ifdef __cplusplus } diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index a057edf..86545cc 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) } /* Initial configuration of a ACC100 device prior to running configure() */ -int -rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf) +static int +acc100_configure(const char *dev_name, struct rte_acc100_conf *conf) { rte_bbdev_log(INFO, "rte_acc100_configure"); uint32_t value, address, status; @@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name); return 0; } + + +/* Initial configuration of a ACC101 device prior to running configure() */ +static int +acc101_configure(const char *dev_name, struct rte_acc100_conf *conf) +{ + rte_bbdev_log(INFO, "rte_acc101_configure"); + uint32_t value, address, status; + int qg_idx, template_idx, vf_idx, acc, i; + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + + /* Compile time checks */ + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32); + + if (bbdev == NULL) { + rte_bbdev_log(ERR, + "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct acc100_device *d = bbdev->data->dev_private; + + /* Store configuration */ + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf)); + + /* PCIe Bridge configuration */ + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE); + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++) + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0); + + /* Prevent blocking AXI read on BRESP for AXI Write */ + address = HwPfPcieGpexAxiPioControl; + value = ACC101_CFG_PCI_AXI; + acc100_reg_write(d, address, value); + + /* Explicitly releasing AXI including a 2ms delay on ACC101 */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* Set the default 5GDL DMA configuration */ + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND); + + /* Enable granular dynamic clock gating */ + address = HWPfHiClkGateHystReg; + value = ACC101_CLOCK_GATING_EN; + acc100_reg_write(d, address, value); + + /* Set default descriptor signature */ + address = HWPfDmaDescriptorSignatuture; + value = 0; + acc100_reg_write(d, address, value); + + /* Enable the Error Detection in DMA */ + value = ACC101_CFG_DMA_ERROR; + address = HWPfDmaErrorDetectionEn; + acc100_reg_write(d, address, value); + + /* AXI Cache configuration */ + value = ACC101_CFG_AXI_CACHE; + address = HWPfDmaAxcacheReg; + acc100_reg_write(d, address, value); + + /* Default DMA Configuration (Qmgr Enabled) */ + address = HWPfDmaConfig0Reg; + value = 0; + acc100_reg_write(d, address, value); + address = HWPfDmaQmanen; + value = 0; + acc100_reg_write(d, address, value); + + /* Default RLIM/ALEN configuration */ + address = HWPfDmaConfig1Reg; + int alen_r = 0xF; + int alen_w = 0x7; + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r; + acc100_reg_write(d, address, value); + + /* Configure DMA Qmanager addresses */ + address = HWPfDmaQmgrAddrReg; + value = HWPfQmgrEgressQueuesTemplate; + acc100_reg_write(d, address, value); + + /* ===== Qmgr Configuration ===== */ + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */ + int totalQgs = conf->q_ul_4g.num_qgroups + + conf->q_ul_5g.num_qgroups + + conf->q_dl_4g.num_qgroups + + conf->q_dl_5g.num_qgroups; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrDepthLog2Grp + + ACC101_BYTES_IN_WORD * qg_idx; + value = aqDepth(qg_idx, conf); + acc100_reg_write(d, address, value); + address = HWPfQmgrTholdGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1)); + acc100_reg_write(d, address, value); + } + + /* Template Priority in incremental order */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_0; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_1; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_2; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_3; + acc100_reg_write(d, address, value); + } + + address = HWPfQmgrGrpPriority; + value = ACC101_CFG_QMGR_HI_P; + acc100_reg_write(d, address, value); + + /* Template Configuration */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + value = 0; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 4GUL */ + int numQgs = conf->q_ul_4g.num_qgroups; + int numQqsAcc = 0; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_4G; + template_idx <= ACC101_SIG_UL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 5GUL */ + numQqsAcc += numQgs; + numQgs = conf->q_ul_5g.num_qgroups; + value = 0; + int numEngines = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_5G; + template_idx <= ACC101_SIG_UL_5G_LAST; + template_idx++) { + /* Check engine power-on status */ + address = HwPfFecUl5gIbDebugReg + + ACC101_ENGINE_OFFSET * template_idx; + status = (acc100_reg_read(d, address) >> 4) & 0xF; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + if (status == 1) { + acc100_reg_write(d, address, value); + numEngines++; + } else + acc100_reg_write(d, address, 0); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + printf("Number of 5GUL engines %d\n", numEngines); + /* 4GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_4g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_4G; + template_idx <= ACC101_SIG_DL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + /* 5GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_5g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_5G; + template_idx <= ACC101_SIG_DL_5G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + + /* Queue Group Function mapping */ + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0}; + address = HWPfQmgrGrpFunction0; + value = 0; + for (qg_idx = 0; qg_idx < 8; qg_idx++) { + acc = accFromQgid(qg_idx, conf); + value |= qman_func_id[acc]<<(qg_idx * 4); + } + acc100_reg_write(d, address, value); + + /* Configuration of the Arbitration QGroup depth to 1 */ + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrArbQDepthGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = 0; + acc100_reg_write(d, address, value); + } + + /* Enabling AQueues through the Queue hierarchy*/ + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) { + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) { + value = 0; + if (vf_idx < conf->num_vf_bundles && + qg_idx < totalQgs) + value = (1 << aqNum(qg_idx, conf)) - 1; + address = HWPfQmgrAqEnableVf + + vf_idx * ACC101_BYTES_IN_WORD; + value += (qg_idx << 16); + acc100_reg_write(d, address, value); + } + } + + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */ + uint32_t aram_address = 0; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfQmgrVfBaseAddr + vf_idx + * ACC101_BYTES_IN_WORD + qg_idx + * ACC101_BYTES_IN_WORD * 64; + value = aram_address; + acc100_reg_write(d, address, value); + /* Offset ARAM Address for next memory bank + * - increment of 4B + */ + aram_address += aqNum(qg_idx, conf) * + (1 << aqDepth(qg_idx, conf)); + } + } + + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) { + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n", + aram_address, ACC101_WORDS_IN_ARAM_SIZE); + return -EINVAL; + } + + /* ==== HI Configuration ==== */ + + /* No Info Ring/MSI by default */ + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0); + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0); + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF); + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF); + /* Prevent Block on Transmit Error */ + address = HWPfHiBlockTransmitOnErrorEn; + value = 0; + acc100_reg_write(d, address, value); + /* Prevents to drop MSI */ + address = HWPfHiMsiDropEnableReg; + value = 0; + acc100_reg_write(d, address, value); + /* Set the PF Mode register */ + address = HWPfHiPfMode; + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0; + acc100_reg_write(d, address, value); + /* Explicitly releasing AXI after PF Mode and 2 ms */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* QoS overflow init */ + value = 1; + address = HWPfQosmonAEvalOverflow0; + acc100_reg_write(d, address, value); + address = HWPfQosmonBEvalOverflow0; + acc100_reg_write(d, address, value); + + /* HARQ DDR Configuration */ + unsigned int ddrSizeInMb = ACC101_HARQ_DDR; + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfDmaVfDdrBaseRw + vf_idx + * 0x10; + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) + + (ddrSizeInMb - 1); + acc100_reg_write(d, address, value); + } + usleep(ACC101_LONG_WAIT); + + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name); + return 0; +} + +int +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf) +{ + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + if (bbdev == NULL) { + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device); + printf("Configure dev id %x\n", pci_dev->id.device_id); + if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) + return acc100_configure(dev_name, conf); + else + return acc101_configure(dev_name, conf); +} diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map index 40604c7..13f0398 100644 --- a/drivers/baseband/acc100/version.map +++ b/drivers/baseband/acc100/version.map @@ -5,6 +5,5 @@ DPDK_22 { EXPERIMENTAL { global: - rte_acc100_configure; - + rte_acc10x_configure; };