From patchwork Thu Feb 17 15:17:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ma, WenwuX" X-Patchwork-Id: 107714 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD47AA0032; Thu, 17 Feb 2022 08:18:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C6C1C410FB; Thu, 17 Feb 2022 08:18:06 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 2F21940042 for ; Thu, 17 Feb 2022 08:18:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645082285; x=1676618285; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=9SPpEeli9WZoued4SH2peQOOXFHbqCUrO0LvzX7lzkI=; b=T4LHAr80qok7j99ci1d0uwsA+J7qobRaQB1x+Cqtb/oJ0sW7up1U/WFH J8SG0DrbP0amdOjX5ndP2HaBRN1HkxLX2CjyyFMQrJqR3IGSMJNokdAdS nb3zawsZUIt7pMBiB1ARBV4LoP/k7XyCX8k+ftpV89aal+UxGK75VSJDM 53Ke4VHMDGfUpvcuz3EydyhihNQ4kRbzQGVjfe/RX+4GxzBbAnix18gUd +ByB9/a+X7wOAD/Nko1IZdvjaezaCsrYVYK5gxJe+z7cS0dHKINokMe6q 8wrfiERIMHZakf3baaVJLzGtKr361etSz1+OGx5BnYP/F44Rn6c1blZjG Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10260"; a="275400446" X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="275400446" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 23:18:04 -0800 X-IronPort-AV: E=Sophos;i="5.88,375,1635231600"; d="scan'208";a="503382582" Received: from unknown (HELO localhost.localdomain) ([10.239.251.209]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 23:18:01 -0800 From: Wenwu Ma To: maxime.coquelin@redhat.com, chenbo.xia@intel.com Cc: dev@dpdk.org, jiayu.hu@intel.com, yinan.wang@intel.com, xingguang.he@intel.com, Wenwu Ma Subject: [PATCH] examples/vhost: add option to control mbuf pool size Date: Thu, 17 Feb 2022 15:17:05 +0000 Message-Id: <20220217151705.441734-1-wenwux.ma@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org dpdk-vhost will fail to launch with a 40G i40e port because there are not enough mbufs. This patch adds a new option --total-num-mbufs, through which the user can set larger mbuf pool to avoid this problem. Signed-off-by: Wenwu Ma --- examples/vhost/main.c | 83 +++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/examples/vhost/main.c b/examples/vhost/main.c index 3e784f5c6f..360f9f7f4d 100644 --- a/examples/vhost/main.c +++ b/examples/vhost/main.c @@ -33,6 +33,8 @@ #define MAX_QUEUES 128 #endif +#define NUM_MBUFS_DEFAULT 0x24000 + /* the maximum number of external ports supported */ #define MAX_SUP_PORTS 1 @@ -61,6 +63,9 @@ #define DMA_RING_SIZE 4096 +/* number of mbufs in all pools - if specified on command-line. */ +static int total_num_mbufs = NUM_MBUFS_DEFAULT; + struct dma_for_vhost dma_bind[RTE_MAX_VHOST_DEVICE]; int16_t dmas_id[RTE_DMADEV_DEFAULT_MAX]; static int dma_count; @@ -609,7 +614,8 @@ us_vhost_usage(const char *prgname) " --tso [0|1] disable/enable TCP segment offload.\n" " --client register a vhost-user socket as client mode.\n" " --dma-type register dma type for your vhost async driver. For example \"ioat\" for now.\n" - " --dmas register dma channel for specific vhost device.\n", + " --dmas register dma channel for specific vhost device.\n" + " --total-num-mbufs [0-N] set the number of mbufs to be allocated in mbuf pools.\n", prgname); } @@ -638,6 +644,8 @@ enum { OPT_BUILTIN_NET_DRIVER_NUM, #define OPT_DMAS "dmas" OPT_DMAS_NUM, +#define OPT_NUM_MBUFS "total-num-mbufs" + OPT_NUM_MBUFS_NUM, }; /* @@ -675,6 +683,8 @@ us_vhost_parse_args(int argc, char **argv) NULL, OPT_BUILTIN_NET_DRIVER_NUM}, {OPT_DMAS, required_argument, NULL, OPT_DMAS_NUM}, + {OPT_NUM_MBUFS, required_argument, + NULL, OPT_NUM_MBUFS_NUM}, {NULL, 0, 0, 0}, }; @@ -802,6 +812,19 @@ us_vhost_parse_args(int argc, char **argv) } break; + case OPT_NUM_MBUFS_NUM: + ret = parse_num_opt(optarg, INT32_MAX); + if (ret == -1) { + RTE_LOG(INFO, VHOST_CONFIG, + "Invalid argument for total-num-mbufs [0..N]\n"); + us_vhost_usage(prgname); + return -1; + } + + if (total_num_mbufs < ret) + total_num_mbufs = ret; + break; + case OPT_CLIENT_NUM: client_mode = 1; break; @@ -1731,57 +1754,6 @@ sigint_handler(__rte_unused int signum) exit(0); } -/* - * While creating an mbuf pool, one key thing is to figure out how - * many mbuf entries is enough for our use. FYI, here are some - * guidelines: - * - * - Each rx queue would reserve @nr_rx_desc mbufs at queue setup stage - * - * - For each switch core (A CPU core does the packet switch), we need - * also make some reservation for receiving the packets from virtio - * Tx queue. How many is enough depends on the usage. It's normally - * a simple calculation like following: - * - * MAX_PKT_BURST * max packet size / mbuf size - * - * So, we definitely need allocate more mbufs when TSO is enabled. - * - * - Similarly, for each switching core, we should serve @nr_rx_desc - * mbufs for receiving the packets from physical NIC device. - * - * - We also need make sure, for each switch core, we have allocated - * enough mbufs to fill up the mbuf cache. - */ -static void -create_mbuf_pool(uint16_t nr_port, uint32_t nr_switch_core, uint32_t mbuf_size, - uint32_t nr_queues, uint32_t nr_rx_desc, uint32_t nr_mbuf_cache) -{ - uint32_t nr_mbufs; - uint32_t nr_mbufs_per_core; - uint32_t mtu = 1500; - - if (mergeable) - mtu = 9000; - if (enable_tso) - mtu = 64 * 1024; - - nr_mbufs_per_core = (mtu + mbuf_size) * MAX_PKT_BURST / - (mbuf_size - RTE_PKTMBUF_HEADROOM); - nr_mbufs_per_core += nr_rx_desc; - nr_mbufs_per_core = RTE_MAX(nr_mbufs_per_core, nr_mbuf_cache); - - nr_mbufs = nr_queues * nr_rx_desc; - nr_mbufs += nr_mbufs_per_core * nr_switch_core; - nr_mbufs *= nr_port; - - mbuf_pool = rte_pktmbuf_pool_create("MBUF_POOL", nr_mbufs, - nr_mbuf_cache, 0, mbuf_size, - rte_socket_id()); - if (mbuf_pool == NULL) - rte_exit(EXIT_FAILURE, "Cannot create mbuf pool\n"); -} - static void reset_dma(void) { @@ -1861,8 +1833,11 @@ main(int argc, char *argv[]) * many queues here. We probably should only do allocation for * those queues we are going to use. */ - create_mbuf_pool(valid_num_ports, rte_lcore_count() - 1, MBUF_DATA_SIZE, - MAX_QUEUES, RTE_TEST_RX_DESC_DEFAULT, MBUF_CACHE_SIZE); + mbuf_pool = rte_pktmbuf_pool_create("MBUF_POOL", total_num_mbufs, + MBUF_CACHE_SIZE, 0, MBUF_DATA_SIZE, + rte_socket_id()); + if (mbuf_pool == NULL) + rte_exit(EXIT_FAILURE, "Cannot create mbuf pool\n"); if (vm2vm_mode == VM2VM_HARDWARE) { /* Enable VT loop back to let L2 switch to do it. */