From patchwork Tue Oct 19 12:37:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102221 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96C41A0C4D; Tue, 19 Oct 2021 14:37:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 769ED4119C; Tue, 19 Oct 2021 14:37:52 +0200 (CEST) Received: from AZHDRRW-EX02.NVIDIA.COM (azhdrrw-ex02.nvidia.com [20.64.145.131]) by mails.dpdk.org (Postfix) with ESMTP id EBD654119B for ; Tue, 19 Oct 2021 14:37:48 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.171) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:37:47 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FLja65HtoNKGPVmZyLPw4ZyEswvLToBGuol1mIIfPaEwUvbbEaYiVjaguyzlTgzunSmAYE+X1pPAmZt0FKugmsOFg+zZswcKqPf+NvY50grK42IHDJxJ7j5DBYOeYR+iQNVbF+pOmsF8+O2WZIAvzmfZSePE6FRLKUVyxiYSxZWkVPBkPkctc9aReMSEAB5QLltSyzuL16H7BiLrIRmeycXgT/m/X3ggX64x4fB8cqHrYiJMu5bsUTKRGYFOqd0sT/SbJj+Tax97zy7mFte5NAn8LlIhSJZMbrERNDkgl38Q0h5VdCCYV8d3BxwCoXDNIYVj1IxWGagixVJzb3wd9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k06OcFSgQ65q+HQN8mNMl4fCsb07qejD+ge0TvywRso=; b=NUirce4NxHiE77NXjLnkdoGYeMpifA3HIC0nc8qHZE0+gn7ZNxeKbgCtBjNpSi2R0WyUahDDukaz/8dlVGOCvw4N6fURUxHUccmIPfhoBm+sfywo51dR+Yc0Kh4EMv7bgt22j4JRxyHq5YNZQgLph0uNd646slOijhO4IfmSiUODB5b03iYeeISeS05jSsMXvMjS6Vc7F2W40o+rXcUnyQfDua7rAxpxainOlJy8aBq8LtKdUW7YAvXm3LMHgtKx8cXPoynCop+O99xUWXFmaqGNUbmTUsXUyBuwsmOw9wVPpNNtDOtnUhl2sD/gi4VZvVxR+9JbWRxwzhHt1yNDdg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k06OcFSgQ65q+HQN8mNMl4fCsb07qejD+ge0TvywRso=; b=m3KFqpJtBDfcYvXN+Vk5xGgigf1EP4pSOJgC3wqBmbVChz9BCZeB/O9O+P8IZLiVkEoGo/eEyCRINolXnaeaBlz6HtQ/GsQNS5kZ4vJrv20DzRMl2qpEcb6Vntdauig/ACzgkvOHWtoiZfHXBMIvXECg0FM0+tS3n5VPrdzP6IhA6SwesLgnvr+lpk6x7waG+ihvSN8mkCDHcGg0GghcD0N3yvZXBrAgihzzv3N7qo+AR9C0xKkHsnOI1EASyStZbK71utCMUNaFH0ZyJVfquZT0AN9+4X96amEczQmNAU71rYqyO3d2/L5vpM6II/688eU0uGkhsp13BJKQ+mIzEA== Received: from DM5PR1101CA0013.namprd11.prod.outlook.com (2603:10b6:4:4c::23) by BN8PR12MB3041.namprd12.prod.outlook.com (2603:10b6:408:46::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.18; Tue, 19 Oct 2021 12:37:46 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::1c) by DM5PR1101CA0013.outlook.office365.com (2603:10b6:4:4c::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:45 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:41 +0000 From: Dmitry Kozlyuk To: CC: Qi Zhang , Ori Kam , "Thomas Monjalon" , Ferruh Yigit , Andrew Rybchenko Date: Tue, 19 Oct 2021 15:37:17 +0300 Message-ID: <20211019123722.3414694-2-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40494a14-e0ec-4434-991f-08d992fd40e0 X-MS-TrafficTypeDiagnostic: BN8PR12MB3041: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iMG+KKoke/5XTrKKEcZu8YsDNxuA5zwbd3CV9N8boE6ayEkq8KA2w+FGiB1O2TkZAUpdUI2aoHZ/jdxMVkLzAYkyM9gP2/LbI9DKhucl7p8hgOxmwZ8dUm3unzIqUB1oBdCRtVHWUv/R+TL24kq7L/Nk5j4fZGCeFDtscV7F3lxc9agw4RIn0XpsftEmCcheyo40jzxbMxo75ImA2pVFUPICKlbN8E4HExtpPUDziZk6L/98crf99BD5AUPnGxwyWxDp8FDduFpTsa6V3PCEsq+yoJlCAorENlj40u9FCwcJ57T9OShJDHUrf7T1rGuEkrCDU6g+Zwj+s8AVpkEzQRByUng2jGCVxi4ISTs4eap8fu3gva2tHTNkVVehGBAlQXk+EAgW9es6HKcBLBFSoorOUhLoGy0miFtWKLBY2Na6Tn843CF0G204bxx5WGE1/xEBmDeERB6ODhHdlLmzHQkzcGNHWeWmmi3ptrZNJ0Ff0syMXeYeUkv6ZNZnhTI2stYJJEnQpELHxtu071m65r39wcN82IvHzLpD8ka6mMvLhwWxIjUZCGkl7kBcP5Ha3Ui6jU4QkQl+PkCqjlhXwG6XtlIhSTmrmnW7lEikQKnDDID1otAyGJU3agCXlpqojO0eqeOu3JAhFZOMRB3smIxTxsv0INdB+L+OlBs7vZQL9ic8HHA9KWZCxTdPjeIP5QW+7wFRr3I9ky7kejkOog== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(316002)(2616005)(7636003)(6666004)(1076003)(6916009)(5660300002)(107886003)(82310400003)(8676002)(70586007)(36756003)(54906003)(86362001)(336012)(70206006)(36906005)(426003)(356005)(4326008)(8936002)(186003)(508600001)(7696005)(47076005)(16526019)(83380400001)(6286002)(55016002)(36860700001)(2906002)(26005); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:37:45.7390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40494a14-e0ec-4434-991f-08d992fd40e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3041 Subject: [dpdk-dev] [PATCH v3 1/6] ethdev: add capability to keep flow rules on restart X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Previously, it was not specified what happens to the flow rules when the device is stopped, possibly reconfigured, then started. If flow rules were kept, it could be convenient for application developers, because they wouldn't need to save and restore them. However, due to the number of flows and possible creation rate it is impractical to save all flow rules in DPDK layer. This means that flow rules persistence really depends on whether PMD and HW can implement it efficiently. It can also be limited by the rule item and action types, and its attributes transfer bit (a combination of an item/action type and a value of the transfer bit is called a ruel feature). Add a device capability bit for PMDs that can keep at least some of the flow rules across restart. Without this capability behavior is still unspecified and it is declared that the application must flush the rules before stopping the device. Allow the application to test for persitence of rules using a particular feature by attempting to create a flow rule using that feature when the device is stopped and checking for the specific error. This is logical because if the PMD can to create the flow rule when the device is not started and use it after the start happens, it is natural that it can move its internal flow rule object to the same state when the device is stopped and restore the state when the device is started. Rule persistence across a reconfigurations is not required, because tracking all the rules and configuration-dependent resources they use may be infeasible. In case a PMD cannot keep the rules across reconfiguration, it is allowed just to report an error. Application must then flush the rules before attempting it. Signed-off-by: Dmitry Kozlyuk Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 25 +++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 7 +++++++ lib/ethdev/rte_flow.h | 1 + 3 files changed, 33 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 2b42d5ec8c..ff67b211e3 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -87,6 +87,31 @@ To avoid resource leaks on the PMD side, handles must be explicitly destroyed by the application before releasing associated resources such as queues and ports. +If ``RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP`` is not advertised, +rules cannot be created until the device is started for the first time +and cannot be kept when the device is stopped. +However, PMD also does not flush them automatically on stop, +so the application must call ``rte_flow_flush()`` or ``rte_flow_destroy()`` +before stopping the device to ensure no rules remain. + +If ``RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP`` is advertised, this means +the PMD can keep at least some rules across the device stop and start. +However, ``rte_eth_dev_configure()`` may fail if any rules remain, +so the application must flush them before attempting a reconfiguration. +Keeping may be unsupported for some types of rule items and actions, +as well as depending on the value of flow attributes transfer bit. +A combination of an item or action type and a value of the transfer bit +is called a rule feature. +To test if rules with a particular feature are kept, the application must try +to create a valid rule using this feature when the device is stopped +(after it has been configured or started previously). +If it fails with an error of type ``RTE_FLOW_ERROR_TYPE_STATE``, +rules using this feature are flushed when the device is stopped. +If it suceeds, such rules will be kept when the device is stopped, +provided they do not use other features that are not supported. +Rules that are created when the device is stopped, including the rules +created for the test, will be kept after the device is started. + The following sections cover: - **Attributes** (represented by ``struct rte_flow_attr``): properties of a diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 6d80514ba7..a0b388bb25 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -90,6 +90,11 @@ * - flow director filtering mode (but not filtering rules) * - NIC queue statistics mappings * + * The following configuration may be retained or not + * depending on the device capabilities: + * + * - flow rules + * * Any other configuration will not be stored and will need to be re-entered * before a call to rte_eth_dev_start(). * @@ -1445,6 +1450,8 @@ struct rte_eth_conf { #define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP 0x00000001 /** Device supports Tx queue setup after device started. */ #define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP 0x00000002 +/** Device supports keeping flow rules across restart. */ +#define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP 0x00000004 /**@}*/ /* diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index a89945061a..aa0182d021 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -3344,6 +3344,7 @@ enum rte_flow_error_type { RTE_FLOW_ERROR_TYPE_ACTION_NUM, /**< Number of actions. */ RTE_FLOW_ERROR_TYPE_ACTION_CONF, /**< Action configuration. */ RTE_FLOW_ERROR_TYPE_ACTION, /**< Specific action. */ + RTE_FLOW_ERROR_TYPE_STATE, /**< Current device state. */ }; /** From patchwork Tue Oct 19 12:37:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102222 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98F0DA0C4D; Tue, 19 Oct 2021 14:37:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 82E30411A5; Tue, 19 Oct 2021 14:37:53 +0200 (CEST) Received: from AZHDRRW-EX02.NVIDIA.COM (azhdrrw-ex02.nvidia.com [20.64.145.131]) by mails.dpdk.org (Postfix) with ESMTP id 4C4C84119C for ; Tue, 19 Oct 2021 14:37:49 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.103) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:37:48 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q4i9oV+qQHuIPx8BkfNA8jH0ChWRmTTZ6n+xw/V7Ramcu475Gbh3mPZAnYKIW9UmlX/FkC/PUXT0dPsANdhZx3wc4GWYB1bkzZTJH+lJhQK01Zk8W6uD3ExXbJk2Y6mVvwvSClrRLPrSrCzPtANPlJTxn7NbBxsKgLmwDUxxD++qQV/KYPhl4UsQ0Z9VDXEmTgfQZkIG2dq2XnI1epOnYahh/Rwzpq1/NbVEbdc9+pU4EkIfeZz1/mwno7MieShiLEvVt0u2LmDKmniL8UnrLVSFYhL+LCZgsyIr5V9wW3qHNH3RnyvX9ksKOChUqEjyS7hFek72h78B2YEraOLXmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BXYNqTNFd/zQX0bUnq5JzyjptPBLbo4ViEGGTPxvjdk=; b=AIDoznc0syiqJT2zAQhcIt+konAYzLkedUCcS9YyiAXVIFP0LUmz6vO6GIyTEAd6i/C9rKbL6oIr4oQZgcYy1XqhtQWHxesU99Wt8Vh56fRMvqMgweK+KVLaF9uN52KxYABs/htt0c/JWvOZYEknNiqupPFzEy60D84wLgwgrQhtxdIl+l3WFAH2zjhx9Nq2+jomFwjMIEj6GZSZyMaMfZ13Uhf0hLXopnnPdV/swoLYgawDj5vXattFKv8hUuD+h/SCnibS0Tkq+pKTD+NM1kniJfDgGuHoQKNxX/Nvnnoo2Pi62ABaK5u0Df4c3goufa8AG6PXnkagRgi5LdU5eQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BXYNqTNFd/zQX0bUnq5JzyjptPBLbo4ViEGGTPxvjdk=; b=Xjgs8JBh4K+kWyUIJ3XnGns21Y0XJpDy90PEA2qBHKv+J0DcxZC3zR8HLxOcqB50/bH79EJYRrX0otLE3J8kgYCogabL5CXoKRZvjfv1au4pnN3CWbS1YfwhQuJhDyEb2PXhwk45qpUFvWxenJNVonEf4Q9zhp9rl9DfCpz9DYpslK8EEBmQV1qcHNRHlJoZPsTpn9Z9tpg/KIBIcjC7skbizDqHd22MOsYa4QBixC7vTcmOV75c/qUipcZ2jrd00JBH6L3HAzD0drQrSl6wDyyMEvGkSP1SqCICtE9PS0FBFHJ1/p+KqeqPRi+fLCNpeLrmm37GY2RhhbyZZtfOmw== Received: from DM5PR1101CA0024.namprd11.prod.outlook.com (2603:10b6:4:4c::34) by CY4PR12MB1398.namprd12.prod.outlook.com (2603:10b6:903:40::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Tue, 19 Oct 2021 12:37:47 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::f3) by DM5PR1101CA0024.outlook.office365.com (2603:10b6:4:4c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:47 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:43 +0000 From: Dmitry Kozlyuk To: CC: Ori Kam , Thomas Monjalon , "Ferruh Yigit" , Andrew Rybchenko Date: Tue, 19 Oct 2021 15:37:18 +0300 Message-ID: <20211019123722.3414694-3-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: da91c0b3-b781-4e5d-d104-08d992fd41aa X-MS-TrafficTypeDiagnostic: CY4PR12MB1398: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9qKW6xrs3iW1JTerG4AHOgZ2jkc3MPvAqbU7XDipsUh02Y+8FYyNW7+W7gGkGdmVEJDq4xOV9rxI4gGMk/hh6QS7HEUchOimhsifvQ0Err3jYXT+1qeTf/OnQzSDbde6TmbahCo799OQI2USBClzHBURwZmlFZ69eGeoaxN7M8pusQ7dTmQz6WkPjm4jQ6lN0wsIPTT/YzBc56zB495vyVwjCrTaVIkOEwjuKG00m7Q6Q3iDxmZ+P5y3i/2vagMvKP46ZwLtTpaVGhk7p2NOrXfGSt0qCwd/L7T4zJg+d/6L/hpKg9W4p4XOhR3E7ik4ax1ECoEdcShM6GnPvOXIrHkAIGcr0gKYOGoMNBdh/+9th3MBvRxjkYqXQXiAwqHRY64G7s4Ykr/5g6niOK0NhbWGaz0cvvz74iOMC3oQEaFpqApsYvmMfNsvNtaw4YzUBbpsSKr/zVvS0sAV7UEXR9pKXNNtWKGrL771LKhZp2zQLAGxaH9wNUOBgZmZUVjthppKojmcLdYJ/DrotUml96GsshVLZoRczHtWa2qSHxNHe3P5aWRJ0dVYoXRU0Uaz5bdt1pU5c4ay53VVTatK4W+moEJ5JBtfBCdjv147Qm7RGkwCQe8ProQrLGOA5wEEZ5MCUK9BL9WiTLkXi1PjnGV7Iqur1E35MIxk15CExIRsxuuTG9ahudGREG4VXMjTTpOC8nvBh/BEZN7OYmwyDA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2906002)(6666004)(6916009)(426003)(4326008)(6286002)(86362001)(82310400003)(1076003)(55016002)(36756003)(7696005)(26005)(16526019)(36860700001)(316002)(70206006)(186003)(8936002)(356005)(107886003)(2616005)(8676002)(5660300002)(508600001)(83380400001)(54906003)(70586007)(336012)(36906005)(47076005)(7636003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:37:47.0513 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da91c0b3-b781-4e5d-d104-08d992fd41aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1398 Subject: [dpdk-dev] [PATCH v3 2/6] ethdev: add capability to keep shared objects on restart X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" rte_flow_action_handle_create() did not mention what happens with an indirect action when a device is stopped and started again. It is natural for some indirect actions, like counter, to be persistent. Keeping others at least saves application time and complexity. However, not all PMDs can support it, or the support may be limited by particular action kinds, that is, combinations of action type and the value of the transfer bit in its configuration. Add a device capability to indicate if at least some indirect actions are kept across the above sequence. Without this capability the behavior is still unspecified, and application is required to destroy the indirect actions before stopping the device. In the future, indirect actions may not be the only type of objects shared between flow rules. The capability bit intends to cover all possible types of such objects, hence its name. Declare that the application can test for the persistence of a particular indirect action kind by attempting to create an indirect action of that kind when the device is stopped and checking for the specific error type. This is logical because if the PMD can to create an indirect action when the device is not started and use it after the start happens, it is natural that it can move its internal flow shared object to the same state when the device is stopped and restore the state when the device is started. Indirect action persistence across a reconfigurations is not required. In case a PMD cannot keep the indirect actions across reconfiguration, it is allowed just to report an error. Application must then flush the indirect actions before attempting it. Signed-off-by: Dmitry Kozlyuk Acked-by: Ori Kam --- doc/guides/prog_guide/rte_flow.rst | 24 ++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index ff67b211e3..19e17f453d 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2810,6 +2810,30 @@ updated depend on the type of the ``action`` and different for every type. The indirect action specified data (e.g. counter) can be queried by ``rte_flow_action_handle_query()``. +If ``RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP`` is not advertised, +indirect actions cannot be created until the device is started for the first time +and cannot be kept when the device is stopped. +However, PMD also does not flush them automatically on stop, +so the application must call ``rte_flow_action_handle_destroy()`` +before stopping the device to ensure no indirect actions remain. + +If ``RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP`` is advertised, +this means that the PMD can keep at least some indirect actions +across device stop and start. +However, ``rte_eth_dev_configure()`` may fail if any indirect actions remain, +so the application must destroy them before attempting a reconfiguration. +Keeping may be only supported for certain kinds of indirect actions. +A kind is a combination of an action type and a value of its transfer bit. +To test if a particular kind of indirect actions is kept, +the application must try to create a valid indirect action of that kind +when the device is stopped (after it has been configured or started previously). +If it fails with an error of type ``RTE_FLOW_ERROR_TYPE_STATE``, +indirect actions of this kind are flushed when the device is stopped. +If it succeeds, all indirect actions of the same kind are kept +when the device is stopped. +Indirect actions of a kept kind that are created when the device is stopped, +including the ones created for the test, will be kept after the device start. + .. _table_rte_flow_action_handle: .. table:: INDIRECT diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index a0b388bb25..12fc7262eb 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -94,6 +94,7 @@ * depending on the device capabilities: * * - flow rules + * - flow-related shared objects, e.g. indirect actions * * Any other configuration will not be stored and will need to be re-entered * before a call to rte_eth_dev_start(). @@ -1452,6 +1453,8 @@ struct rte_eth_conf { #define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP 0x00000002 /** Device supports keeping flow rules across restart. */ #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP 0x00000004 +/** Device supports keeping shared flow objects across restart. */ +#define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP 0x00000008 /**@}*/ /* From patchwork Tue Oct 19 12:37:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102223 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5395AA0C4D; Tue, 19 Oct 2021 14:38:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF69C4119D; Tue, 19 Oct 2021 14:38:00 +0200 (CEST) Received: from AZHDRRW-EX01.nvidia.com (azhdrrw-ex01.nvidia.com [20.51.104.162]) by mails.dpdk.org (Postfix) with ESMTP id 03D294119B for ; Tue, 19 Oct 2021 14:37:57 +0200 (CEST) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (104.47.73.168) by mxs.oss.nvidia.com (10.13.234.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:37:56 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BgZroEwi/Fz/6ddTMUfuMXZSfuPfIT7u9/fhFC6AitXr59CdatK0TMnMGQBqcPTaq6yTc1Ko6X3dmY13TBKEr2k+l3SKcyM1O1J24u5p4Xc3oFhN9sXxeuRfl+7ZDInpo6kuB77O4MH5u01Mxf4abOLehjLk7YKNrZPnsvPGNgwNaG8QY79c3kkQP19YbOmfY54OSUaf/0UsbQSR1QlO4au0PD2wGfdZfX9FHIz6gaS5qzEdmoQXw/Xm8uItpGfudNxPpWTlOmp0Mq/+n0WqGq6s0O2LjQm6cwHoghs8iKnwHt7vWeb5eQL5b83qD/NhNPqL84SH4yWuT4T+tVnvsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JEZf1nHjkSUr8xaf46uRYW5TuFiTErZ4zlep9hAIKvo=; b=jJLQnJFgntAbw926iyo2GASDr9H7K2bI6x3zZB9rkwO2wR744Sib13K/c2yGtBIg2+lfbnFPzoj/oz3+duaTpvkFwewAl2EezLy39aiHgUfjLDPRPbFNu2F0ucXtpP8nfTBpzTSCqlzvE/+aUUa/8jrpnlFax6+fG51klkNopB7ZwEvRbCkNXOwZxSukpsrPk08LxGkRvfNNWaNs9pkfZnL6CnocjQwxEojH+XIMxqV0CYYr2TBLmAnS8wdumGSo6zsFl/d/sK+LE1rgEL8PoBeCBY0hJuOlc+y8PwC1xK/YIKyienENIPmlAbXmeRM3TYgyMj4dIlT96uvC1hyd6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JEZf1nHjkSUr8xaf46uRYW5TuFiTErZ4zlep9hAIKvo=; b=uXeobdZ9At4Sd6aZykbaP8S2aV8XG8lJ958RT2dr+2O8b5Ip9rlpCYYnidbjUYpdI4ZRBRVIDY3RmbmrsfOVsvQBCF4Rn8uVHb0O7lmeXK59nVZFHoTylBkKqgooRyTg9jXauIPEOCrGVTXtQ8L2n+amMhD2C24ifwXG15icIwoOs3LgOqBR4BFV3fviLSRJFyfXFqdJCP1Ix7ATzCD3wcZ2mw+D7yy+jVpUn+n0vqOQFRTwC1XZmgEUsGEo/JUgPhzMtQw432FykGtUWKwyX0bhL900GNwqor1dTNV2ESSpBWnZ6vq3Hsje3cJ0kw0q9Odn2w1SS2zpIDEz9P8qow== Received: from DM5PR1101CA0024.namprd11.prod.outlook.com (2603:10b6:4:4c::34) by BY5PR12MB4162.namprd12.prod.outlook.com (2603:10b6:a03:201::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15; Tue, 19 Oct 2021 12:37:55 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::78) by DM5PR1101CA0024.outlook.office365.com (2603:10b6:4:4c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:54 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:45 +0000 From: Dmitry Kozlyuk To: CC: Ferruh Yigit , Ajit Khaparde , Somnath Kotur , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Rahul Lakkireddy , Hemant Agrawal , Sachin Saxena , Haiyue Wang , John Daley , Hyong Youb Kim , Gaetan Rivet , Ziyang Xuan , Xiaoyun Wang , Guoyang Zhou , "Min Hu (Connor)" , Yisen Zhuang , Lijun Ou , Beilei Xing , "Jingjing Wu" , Qiming Yang , Qi Zhang , Rosen Xu , Liron Himi , Jerin Jacob , Rasesh Mody , Devendra Singh Rawat , "Andrew Rybchenko" , Jasvinder Singh , Cristian Dumitrescu , Keith Wiles , "Jiawen Wu" , Jian Wang Date: Tue, 19 Oct 2021 15:37:19 +0300 Message-ID: <20211019123722.3414694-4-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dd0c69bf-34d2-4a29-01ca-08d992fd45ea X-MS-TrafficTypeDiagnostic: BY5PR12MB4162: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YFLvz8GhIx2ULJnCb6Oz1PrQmaXglbz+vLRtVR3tIgqTCgMmsr50Vzn7/400Rfe99+oohicPbrS+L8QG+jxbQ9ma1+85C0LQ32JbnTDLn6ihoXiDPjjAZ5bmMy7CY8xrbZ/Qi9IwJqZZaUKsPwLTuvDOLbfAai79v65FgWJfxpcPHe62wgVOFakOUwc0Vjy72PuSKDR59BmltVBzu3bWWkW4BT86TJIUK5In34ifKGmLl0TdcJa9+AOYfxi5L62oFKByom8k/ZQo9Z6Ztlrm/d5Nums5bEeLkgNOWrb7NFWKHPa6lvATJ5qVexodE2+HkgTLAH7lt+hfWvls/H80pv5uw0BrXqyht3rGq96cfQ1DQO8uRPqo2K1H0FsKBkb4Gl6re2loaTxcccJr051MnmK6fgic96zDb+Ii5ru1ETFa+/ceR2Iei+ujLATT3RKPnPNCsnwVkjYh9u21Q4tYgzWeTsQknv5JPSuaHAO+lp586HpvRNXqkig5fFEDwSMrWbLIN4Rnq3D1cnq1uvxq/HRzT+012z2Bbc1TKImDqI2ne7KabG8mfXh4FxQkmA2THsIrXei4XogsGMAWxAAmAmy4i5454uVILaNyWp+CfesJ3y8+9kGd6x/91vMEr2jl2/QEtm5FcHFndvCuIggwhcj3LE1Ro7QDfSd5PA5mw2qYN1faIeOsnwmIGOhLgem+nro9sB5M1VGOtie3LeTwHBBr3tOcSGIW4urXHL1DXPU= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(356005)(186003)(16526019)(54906003)(26005)(70586007)(70206006)(83380400001)(336012)(2616005)(316002)(7636003)(7696005)(508600001)(47076005)(36860700001)(426003)(5660300002)(4326008)(107886003)(6286002)(2906002)(8936002)(55016002)(86362001)(8676002)(30864003)(36756003)(6666004)(1076003)(6916009)(82310400003)(21314003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:37:54.1503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd0c69bf-34d2-4a29-01ca-08d992fd45ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4162 Subject: [dpdk-dev] [PATCH v3 3/6] net: advertise no support for keeping flow rules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP capability bit is zero, the specified behavior is the same as it had been before this bit was introduced. Explicitly reset it in all PMDs supporting rte_flow API in order to attract the attention of maintainers, who should eventually choose to advertise the new capability or not. It is already known that mlx4 and mlx5 will not support this capability. For RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP similar action is not performed, because no PMD except mlx5 supports indirect actions. Any PMD that starts doing so will anyway have to consider all relevant API, including this capability. Suggested-by: Ferruh Yigit Signed-off-by: Dmitry Kozlyuk --- drivers/net/bnxt/bnxt_ethdev.c | 1 + drivers/net/bnxt/bnxt_reps.c | 1 + drivers/net/cnxk/cnxk_ethdev_ops.c | 1 + drivers/net/cxgbe/cxgbe_ethdev.c | 2 ++ drivers/net/dpaa2/dpaa2_ethdev.c | 1 + drivers/net/e1000/em_ethdev.c | 2 ++ drivers/net/e1000/igb_ethdev.c | 1 + drivers/net/enic/enic_ethdev.c | 1 + drivers/net/failsafe/failsafe_ops.c | 1 + drivers/net/hinic/hinic_pmd_ethdev.c | 2 ++ drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/i40e/i40e_ethdev.c | 1 + drivers/net/i40e/i40e_vf_representor.c | 2 ++ drivers/net/iavf/iavf_ethdev.c | 1 + drivers/net/ice/ice_dcf_ethdev.c | 1 + drivers/net/igc/igc_ethdev.c | 1 + drivers/net/ipn3ke/ipn3ke_representor.c | 1 + drivers/net/mvpp2/mrvl_ethdev.c | 2 ++ drivers/net/octeontx2/otx2_ethdev_ops.c | 1 + drivers/net/qede/qede_ethdev.c | 1 + drivers/net/sfc/sfc_ethdev.c | 1 + drivers/net/softnic/rte_eth_softnic.c | 1 + drivers/net/tap/rte_eth_tap.c | 1 + drivers/net/txgbe/txgbe_ethdev.c | 1 + drivers/net/txgbe/txgbe_ethdev_vf.c | 1 + 26 files changed, 31 insertions(+) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index aa7e7fdc85..1a6e0128ff 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1009,6 +1009,7 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, dev_info->speed_capa = bnxt_get_speed_capabilities(bp); dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_thresh = { diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c index df05619c3f..0697f820db 100644 --- a/drivers/net/bnxt/bnxt_reps.c +++ b/drivers/net/bnxt/bnxt_reps.c @@ -525,6 +525,7 @@ int bnxt_rep_dev_info_get_op(struct rte_eth_dev *eth_dev, dev_info->max_tx_queues = max_rx_rings; dev_info->reta_size = bnxt_rss_hash_tbl_size(parent_bp); dev_info->hash_key_size = 40; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; /* MTU specifics */ dev_info->min_mtu = RTE_ETHER_MIN_MTU; diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index b6cc5286c6..a2b85c9411 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -68,6 +68,7 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->speed_capa = dev->speed_capa; devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; return 0; } diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index cd9aa9f84b..a1207fcc17 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -131,6 +131,8 @@ int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, device_info->max_vfs = adapter->params.arch.vfcount; device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ + device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + device_info->rx_queue_offload_capa = 0UL; device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index ff8ae89922..6f8d4d3ad8 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -255,6 +255,7 @@ dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_10G; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->max_hash_mac_addrs = 0; dev_info->max_vfs = 0; diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c index a0ca371b02..897c15d6da 100644 --- a/drivers/net/e1000/em_ethdev.c +++ b/drivers/net/e1000/em_ethdev.c @@ -1108,6 +1108,8 @@ eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + /* Preferred queue parameters */ dev_info->default_rxportconf.nb_queues = 1; dev_info->default_txportconf.nb_queues = 1; diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 6510cd7ceb..49e354b388 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -2178,6 +2178,7 @@ eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev); dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) | dev_info->tx_queue_offload_capa; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; switch (hw->mac.type) { case e1000_82575: diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c index b03e56bc25..d445a11e4d 100644 --- a/drivers/net/enic/enic_ethdev.c +++ b/drivers/net/enic/enic_ethdev.c @@ -469,6 +469,7 @@ static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, device_info->rx_offload_capa = enic->rx_offload_capa; device_info->tx_offload_capa = enic->tx_offload_capa; device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; + device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; device_info->default_rxconf = (struct rte_eth_rxconf) { .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH }; diff --git a/drivers/net/failsafe/failsafe_ops.c b/drivers/net/failsafe/failsafe_ops.c index d0030af061..3040ce0de6 100644 --- a/drivers/net/failsafe/failsafe_ops.c +++ b/drivers/net/failsafe/failsafe_ops.c @@ -1222,6 +1222,7 @@ fs_dev_infos_get(struct rte_eth_dev *dev, infos->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + infos->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_PROBED) { struct rte_eth_dev_info sub_info; diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c index cd4dad8588..9567974cc9 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.c +++ b/drivers/net/hinic/hinic_pmd_ethdev.c @@ -752,6 +752,8 @@ hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_MULTI_SEGS; + info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + info->hash_key_size = HINIC_RSS_KEY_SIZE; info->reta_size = HINIC_RSS_INDIR_SIZE; info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL; diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index cabf73ffbc..6cfcbe1375 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2752,6 +2752,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; if (hns3_dev_ptp_supported(hw)) info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 8d9b7979c8..25f73e62c6 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -994,6 +994,7 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; info->rx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = HNS3_MAX_RING_DESC, diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 1fc3d897a8..13b0ccfbf7 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -3747,6 +3747,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); diff --git a/drivers/net/i40e/i40e_vf_representor.c b/drivers/net/i40e/i40e_vf_representor.c index 0481b55381..6c06c8992b 100644 --- a/drivers/net/i40e/i40e_vf_representor.c +++ b/drivers/net/i40e/i40e_vf_representor.c @@ -35,6 +35,8 @@ i40e_vf_representor_dev_infos_get(struct rte_eth_dev *ethdev, /* get dev info for the vdev */ dev_info->device = ethdev->device; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + dev_info->max_rx_queues = ethdev->data->nb_rx_queues; dev_info->max_tx_queues = ethdev->data->nb_tx_queues; diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index 5a5a7f59e1..83914b05cc 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -959,6 +959,7 @@ iavf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->reta_size = vf->vf_res->rss_lut_size; dev_info->flow_type_rss_offloads = IAVF_RSS_OFFLOAD_ALL; dev_info->max_mac_addrs = IAVF_NUM_MACADDR_MAX; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_QINQ_STRIP | diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 91f6558742..dab11b21ef 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -676,6 +676,7 @@ ice_dcf_dev_info_get(struct rte_eth_dev *dev, dev_info->hash_key_size = hw->vf_res->rss_key_size; dev_info->reta_size = hw->vf_res->rss_lut_size; dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c index 0e41c85d29..d55bc4babd 100644 --- a/drivers/net/igc/igc_ethdev.c +++ b/drivers/net/igc/igc_ethdev.c @@ -1488,6 +1488,7 @@ eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE; dev_info->max_mac_addrs = hw->mac.rar_entry_count; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL; dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL; dev_info->rx_queue_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP; diff --git a/drivers/net/ipn3ke/ipn3ke_representor.c b/drivers/net/ipn3ke/ipn3ke_representor.c index 694435a4ae..e7c1968ead 100644 --- a/drivers/net/ipn3ke/ipn3ke_representor.c +++ b/drivers/net/ipn3ke/ipn3ke_representor.c @@ -97,6 +97,7 @@ ipn3ke_rpst_dev_infos_get(struct rte_eth_dev *ethdev, dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->switch_info.name = ethdev->device->name; dev_info->switch_info.domain_id = rpst->switch_domain_id; diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 65d011300a..71ff094495 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1718,6 +1718,8 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev, { struct mrvl_priv *priv = dev->data->dev_private; + info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + info->speed_capa = ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c index 552e6bd43d..54cb1f4b44 100644 --- a/drivers/net/octeontx2/otx2_ethdev_ops.c +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c @@ -611,6 +611,7 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; return 0; } diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index fd8c62a182..403c63cc68 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -1373,6 +1373,7 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev, dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN; dev_info->rx_desc_lim = qede_rx_desc_lim; dev_info->tx_desc_lim = qede_tx_desc_lim; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; if (IS_PF(edev)) dev_info->max_rx_queues = (uint16_t)RTE_MIN( diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c index 9dc5e5b3a3..50908005e8 100644 --- a/drivers/net/sfc/sfc_ethdev.c +++ b/drivers/net/sfc/sfc_ethdev.c @@ -183,6 +183,7 @@ sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; if (mae->status == SFC_MAE_STATUS_SUPPORTED) { dev_info->switch_info.name = dev->device->driver->name; diff --git a/drivers/net/softnic/rte_eth_softnic.c b/drivers/net/softnic/rte_eth_softnic.c index b3b55b9035..3622049afa 100644 --- a/drivers/net/softnic/rte_eth_softnic.c +++ b/drivers/net/softnic/rte_eth_softnic.c @@ -93,6 +93,7 @@ pmd_dev_infos_get(struct rte_eth_dev *dev __rte_unused, dev_info->max_rx_pktlen = UINT32_MAX; dev_info->max_rx_queues = UINT16_MAX; dev_info->max_tx_queues = UINT16_MAX; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; return 0; } diff --git a/drivers/net/tap/rte_eth_tap.c b/drivers/net/tap/rte_eth_tap.c index 046f17669d..f8f1eb96f4 100644 --- a/drivers/net/tap/rte_eth_tap.c +++ b/drivers/net/tap/rte_eth_tap.c @@ -1006,6 +1006,7 @@ tap_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) * functions together and not in partial combinations */ dev_info->flow_type_rss_offloads = ~TAP_RSS_HF_MASK; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; return 0; } diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index b267da462b..21758851e5 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -2613,6 +2613,7 @@ txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->max_vfs = pci_dev->max_vfs; dev_info->max_vmdq_pools = ETH_64_POOLS; dev_info->vmdq_queue_num = dev_info->max_rx_queues; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | dev_info->rx_queue_offload_capa); diff --git a/drivers/net/txgbe/txgbe_ethdev_vf.c b/drivers/net/txgbe/txgbe_ethdev_vf.c index 896da8a887..bba234a5e9 100644 --- a/drivers/net/txgbe/txgbe_ethdev_vf.c +++ b/drivers/net/txgbe/txgbe_ethdev_vf.c @@ -487,6 +487,7 @@ txgbevf_dev_info_get(struct rte_eth_dev *dev, dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC; dev_info->max_vfs = pci_dev->max_vfs; dev_info->max_vmdq_pools = ETH_64_POOLS; + dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev); dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) | dev_info->rx_queue_offload_capa); From patchwork Tue Oct 19 12:37:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102224 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD4AEA0C4D; Tue, 19 Oct 2021 14:38:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0AD00411AE; Tue, 19 Oct 2021 14:38:06 +0200 (CEST) Received: from AZHDRRW-EX01.nvidia.com (azhdrrw-ex01.nvidia.com [20.51.104.162]) by mails.dpdk.org (Postfix) with ESMTP id B5C62410F4; Tue, 19 Oct 2021 14:38:00 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.174) by mxs.oss.nvidia.com (10.13.234.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:38:00 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X4dJg5ycRnD+Z63toWbBwBeGwT5JHQ7EUyJ7/7Qi8JPVTifdwDCmbGEn2CdVIPuNQgKisswAIsBiqPebpi2ovrXolbJWLWlB//rNp/rRe0g86pnHgz4n8quyGfFYdth0MWzPdbiT32JQszoXJVNHATZqE6pVhUsHgD7bJF0HlSgAZoh5pMZ7D/qxOOYtDqC/XzXuf4Ut4EvWWaXVwEmQzoLKuVET6evj/OPsW45FqasFCF/rZvxPuZgLCMfdDtIgR7jvIHDyhB1xDEF94RAIEY5nd7/T1a3UXxMMqqFMFYYOTcElhVgOKPo+GEjErRuHVYxjex3AK6cyEhudKWupbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BYmjf649AjxfufmyExX1H9A/RXBudrCIcO65K2pPD+E=; b=BJ0Tsyv1LnQYmObjRV7hXWhrt1E4vwV+ogoWPw8lrPThpAT62nCshthqI6VxuxUEW7Mwc0T8/YeCzWAtsYhpvRQ9SaOGyEFj5dvkgOAHoX3+7t3G4pqQrqYh56/KEmLqvz4f75JMEFekmJN7UBGrY+Naxohb331+WKbL702YHcDstwTUuBTjbMijPsJD3f6PA3pXhy7ATQ5mpfY5Pf2mHDGr61pM2qohQG0H05IW4TW0S8T/N5VciUSUEnGp7IhGCPTHVmxs+0L4zKOgz1eYrgvKKkwQ2QNG/wTL/m96dyiFHpfja7Stk9HVmDPlZcOPekiOhaWv2FErGRrvm0hnlg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BYmjf649AjxfufmyExX1H9A/RXBudrCIcO65K2pPD+E=; b=Hzdj7OqpTGX+AboUIlS583z/DzgN1A+ASlCH1CU85t7dbXqjrDAOTUuhKzbJcexj8+ntq7K61rCBalapqi+yvlmaZYh1u+k/aLzmaq6YUuSTH5dmktbp5W4X+o0xd2H7HqcLoqhGiW7Y+V4NgypybeKWoxyY73CSwnyG6GgeintyIEh3+G7tesyBeKp7lWqfuEmtlcgMZGbrcX84vxboV22ICq4BwDQO3PmyW6hhx32tatE8Kg9z9XsIOsKReUx3oxO+iXYsukIogl/ov+8BxUEfl8OSqNQdbU9GiraagMElpnAiFDN9Z713utv7D158xAqS4q78iUEzXrzW1K2bRg== Received: from DM5PR1101CA0003.namprd11.prod.outlook.com (2603:10b6:4:4c::13) by SA0PR12MB4367.namprd12.prod.outlook.com (2603:10b6:806:94::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Tue, 19 Oct 2021 12:37:58 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::c7) by DM5PR1101CA0003.outlook.office365.com (2603:10b6:4:4c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:37:56 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:53 +0000 From: Dmitry Kozlyuk To: CC: , Matan Azrad , Viacheslav Ovsiienko Date: Tue, 19 Oct 2021 15:37:20 +0300 Message-ID: <20211019123722.3414694-5-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d16ac6b9-2c05-475e-1b12-08d992fd47fc X-MS-TrafficTypeDiagnostic: SA0PR12MB4367: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vB4bxISn6v1MqNaNTO/Ogc71KhaGc4ty+92vljDYdFSK4ACa55c/N2hSyY1WZq3vFAnqi/qpqymg+ceXtiYf8fqn46HmA3jtluYyvlM/FBvsfT5MBkd4utKD9msxGmxS09wK4DRJ25LyRK7ISpfnkzNIoLNku9UpGFHpLvECOwaUggA9rhHd5b7Xi/dNw0GhLgYV0E0y2tnRbFnISnR/DYpkU1BxtxoS+vJDbYmHNwqB5wC7aGOXvkLbjB93UJZo3cGFrILxcFXflUPOTLdlxDe6nxmbxzDv+RlGEwKGbpu2XnlhhEqlyhYUVhdo0ji6DhYyBU8D4btR5QpRJxAk4mnrzjFTaKyXyyqdh5Z3zfuysHBEuPTFPfsVPLtaprU74ZxleB7OGxXUT5LESgZDcJhLu6geG9kb8EG8XEO668QaY5ndoyju9yRLicvBwhib2IcW78Yac+jZezmfq3Fr2FARi4WLgjS4pkPCUahnZP9DyhBr491Du4SJEGS8BAtqHHaqZxflW8bIT8SiSXU20q2DwhBhmAHKtW3wB3eIgk/FO2UJFtqRZq1XYUdsmg6WJrG9DGWAok1s2MacqqXd08n9orHVQ+WEVeA5bE+uoWlc4bfYl8FDot5e8HItH50gKS/ykDaEBVGuTlY/61YBs+I862stz5d/kWycco+cuvqGRANdE1ImdcDaMgNDjevypFO73l0jMywhSMzqgl16+Q== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(336012)(6666004)(5660300002)(2616005)(36860700001)(508600001)(6286002)(30864003)(54906003)(8676002)(426003)(7636003)(36756003)(82310400003)(8936002)(6916009)(70206006)(16526019)(55016002)(356005)(4326008)(450100002)(47076005)(316002)(70586007)(107886003)(2906002)(7696005)(26005)(83380400001)(1076003)(86362001)(186003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:37:56.2582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d16ac6b9-2c05-475e-1b12-08d992fd47fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4367 Subject: [dpdk-dev] [PATCH v3 4/6] net/mlx5: discover max flow priority using DevX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Maximum available flow priority was discovered using Verbs API regardless of the selected flow engine. This required some Verbs objects to be initialized in order to use DevX engine. Make priority discovery an engine method and implement it for DevX using its API. Cc: stable@dpdk.org Signed-off-by: Dmitry Kozlyuk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 1 - drivers/net/mlx5/mlx5_flow.c | 98 +++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 4 ++ drivers/net/mlx5/mlx5_flow_dv.c | 103 +++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_verbs.c | 77 +++------------------ 5 files changed, 215 insertions(+), 68 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 3746057673..8ee7ada51b 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1830,7 +1830,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev); if (!priv->drop_queue.hrxq) goto error; - /* Supported Verbs flow priority number detection. */ err = mlx5_flow_discover_priorities(eth_dev); if (err < 0) { err = -err; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index c914a7120c..bfc3e20c9a 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -9416,3 +9416,101 @@ mlx5_dbg__print_pattern(const struct rte_flow_item *item) } printf("END\n"); } + +/* Map of Verbs to Flow priority with 8 Verbs priorities. */ +static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { + { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, +}; + +/* Map of Verbs to Flow priority with 16 Verbs priorities. */ +static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { + { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, + { 9, 10, 11 }, { 12, 13, 14 }, +}; + +/** + * Discover the number of available flow priorities. + * + * @param dev + * Ethernet device. + * + * @return + * On success, number of available flow priorities. + * On failure, a negative errno-style code and rte_errno is set. + */ +int +mlx5_flow_discover_priorities(struct rte_eth_dev *dev) +{ + static const uint16_t vprio[] = {8, 16}; + const struct mlx5_priv *priv = dev->data->dev_private; + const struct mlx5_flow_driver_ops *fops; + enum mlx5_flow_drv_type type; + int ret; + + type = mlx5_flow_os_get_type(); + if (type == MLX5_FLOW_TYPE_MAX) { + type = MLX5_FLOW_TYPE_VERBS; + if (priv->config.devx && priv->config.dv_flow_en) + type = MLX5_FLOW_TYPE_DV; + } + fops = flow_get_drv_ops(type); + if (fops->discover_priorities == NULL) { + DRV_LOG(ERR, "Priority discovery not supported"); + rte_errno = ENOTSUP; + return -rte_errno; + } + ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); + if (ret < 0) + return ret; + switch (ret) { + case 8: + ret = RTE_DIM(priority_map_3); + break; + case 16: + ret = RTE_DIM(priority_map_5); + break; + default: + rte_errno = ENOTSUP; + DRV_LOG(ERR, + "port %u maximum priority: %d expected 8/16", + dev->data->port_id, ret); + return -rte_errno; + } + DRV_LOG(INFO, "port %u supported flow priorities:" + " 0-%d for ingress or egress root table," + " 0-%d for non-root table or transfer root table.", + dev->data->port_id, ret - 2, + MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); + return ret; +} + +/** + * Adjust flow priority based on the highest layer and the request priority. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] priority + * The rule base priority. + * @param[in] subpriority + * The priority based on the items. + * + * @return + * The new priority. + */ +uint32_t +mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, + uint32_t subpriority) +{ + uint32_t res = 0; + struct mlx5_priv *priv = dev->data->dev_private; + + switch (priv->config.flow_prio) { + case RTE_DIM(priority_map_3): + res = priority_map_3[priority][subpriority]; + break; + case RTE_DIM(priority_map_5): + res = priority_map_5[priority][subpriority]; + break; + } + return res; +} diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 5c68d4f7d7..8f94125f26 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1226,6 +1226,9 @@ typedef int (*mlx5_flow_create_def_policy_t) (struct rte_eth_dev *dev); typedef void (*mlx5_flow_destroy_def_policy_t) (struct rte_eth_dev *dev); +typedef int (*mlx5_flow_discover_priorities_t) + (struct rte_eth_dev *dev, + const uint16_t *vprio, int vprio_n); struct mlx5_flow_driver_ops { mlx5_flow_validate_t validate; @@ -1260,6 +1263,7 @@ struct mlx5_flow_driver_ops { mlx5_flow_action_update_t action_update; mlx5_flow_action_query_t action_query; mlx5_flow_sync_domain_t sync_domain; + mlx5_flow_discover_priorities_t discover_priorities; }; /* mlx5_flow.c */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index c6370cd1d6..155745748f 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -17978,6 +17978,108 @@ flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags) return 0; } +/** + * Discover the number of available flow priorities + * by trying to create a flow with the highest priority value + * for each possible number. + * + * @param[in] dev + * Ethernet device. + * @param[in] vprio + * List of possible number of available priorities. + * @param[in] vprio_n + * Size of @p vprio array. + * @return + * On success, number of available flow priorities. + * On failure, a negative errno-style code and rte_errno is set. + */ +static int +flow_dv_discover_priorities(struct rte_eth_dev *dev, + const uint16_t *vprio, int vprio_n) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW]; + struct rte_flow_item_eth eth; + struct rte_flow_item item = { + .type = RTE_FLOW_ITEM_TYPE_ETH, + .spec = ð, + .mask = ð, + }; + struct mlx5_flow_dv_matcher matcher = { + .mask = { + .size = sizeof(matcher.mask.buf), + }, + }; + union mlx5_flow_tbl_key tbl_key; + struct mlx5_flow flow; + void *action; + struct rte_flow_error error; + uint8_t misc_mask; + int i, err, ret = -ENOTSUP; + + /* + * Prepare a flow with a catch-all pattern and a drop action. + * Use drop queue, because shared drop action may be unavailable. + */ + action = priv->drop_queue.hrxq->action; + if (action == NULL) { + DRV_LOG(ERR, "Priority discovery requires a drop action"); + rte_errno = ENOTSUP; + return -rte_errno; + } + memset(&flow, 0, sizeof(flow)); + flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx); + if (flow.handle == NULL) { + DRV_LOG(ERR, "Cannot create flow handle"); + rte_errno = ENOMEM; + return -rte_errno; + } + flow.ingress = true; + flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param); + flow.dv.actions[0] = action; + flow.dv.actions_n = 1; + memset(ð, 0, sizeof(eth)); + flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf, + &item, /* inner */ false, /* group */ 0); + matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size); + for (i = 0; i < vprio_n; i++) { + /* Configure the next proposed maximum priority. */ + matcher.priority = vprio[i] - 1; + memset(&tbl_key, 0, sizeof(tbl_key)); + err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow, + /* tunnel */ NULL, + /* group */ 0, + &error); + if (err != 0) { + /* This action is pure SW and must always succeed. */ + DRV_LOG(ERR, "Cannot register matcher"); + ret = -rte_errno; + break; + } + /* Try to apply the flow to HW. */ + misc_mask = flow_dv_matcher_enable(flow.dv.value.buf); + __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask); + err = mlx5_flow_os_create_flow + (flow.handle->dvh.matcher->matcher_object, + (void *)&flow.dv.value, flow.dv.actions_n, + flow.dv.actions, &flow.handle->drv_flow); + if (err == 0) { + claim_zero(mlx5_flow_os_destroy_flow + (flow.handle->drv_flow)); + flow.handle->drv_flow = NULL; + } + claim_zero(flow_dv_matcher_release(dev, flow.handle)); + if (err != 0) + break; + ret = vprio[i]; + } + mlx5_ipool_free(pool, flow.handle_idx); + /* Set rte_errno if no expected priority value matched. */ + if (ret < 0) + rte_errno = -ret; + return ret; +} + const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = { .validate = flow_dv_validate, .prepare = flow_dv_prepare, @@ -18011,6 +18113,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = { .action_update = flow_dv_action_update, .action_query = flow_dv_action_query, .sync_domain = flow_dv_sync_domain, + .discover_priorities = flow_dv_discover_priorities, }; #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index b93fd4d2c9..72b9db6c7f 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -28,17 +28,6 @@ #define VERBS_SPEC_INNER(item_flags) \ (!!((item_flags) & MLX5_FLOW_LAYER_TUNNEL) ? IBV_FLOW_SPEC_INNER : 0) -/* Map of Verbs to Flow priority with 8 Verbs priorities. */ -static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { - { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, -}; - -/* Map of Verbs to Flow priority with 16 Verbs priorities. */ -static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { - { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, - { 9, 10, 11 }, { 12, 13, 14 }, -}; - /* Verbs specification header. */ struct ibv_spec_header { enum ibv_flow_spec_type type; @@ -50,13 +39,17 @@ struct ibv_spec_header { * * @param[in] dev * Pointer to the Ethernet device structure. - * + * @param[in] vprio + * Expected result variants. + * @param[in] vprio_n + * Number of entries in @p vprio array. * @return - * number of supported flow priority on success, a negative errno + * Number of supported flow priority on success, a negative errno * value otherwise and rte_errno is set. */ -int -mlx5_flow_discover_priorities(struct rte_eth_dev *dev) +static int +flow_verbs_discover_priorities(struct rte_eth_dev *dev, + const uint16_t *vprio, int vprio_n) { struct mlx5_priv *priv = dev->data->dev_private; struct { @@ -79,7 +72,6 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) }; struct ibv_flow *flow; struct mlx5_hrxq *drop = priv->drop_queue.hrxq; - uint16_t vprio[] = { 8, 16 }; int i; int priority = 0; @@ -87,7 +79,7 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) rte_errno = ENOTSUP; return -rte_errno; } - for (i = 0; i != RTE_DIM(vprio); i++) { + for (i = 0; i != vprio_n; i++) { flow_attr.attr.priority = vprio[i] - 1; flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr); if (!flow) @@ -95,59 +87,9 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev) claim_zero(mlx5_glue->destroy_flow(flow)); priority = vprio[i]; } - switch (priority) { - case 8: - priority = RTE_DIM(priority_map_3); - break; - case 16: - priority = RTE_DIM(priority_map_5); - break; - default: - rte_errno = ENOTSUP; - DRV_LOG(ERR, - "port %u verbs maximum priority: %d expected 8/16", - dev->data->port_id, priority); - return -rte_errno; - } - DRV_LOG(INFO, "port %u supported flow priorities:" - " 0-%d for ingress or egress root table," - " 0-%d for non-root table or transfer root table.", - dev->data->port_id, priority - 2, - MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); return priority; } -/** - * Adjust flow priority based on the highest layer and the request priority. - * - * @param[in] dev - * Pointer to the Ethernet device structure. - * @param[in] priority - * The rule base priority. - * @param[in] subpriority - * The priority based on the items. - * - * @return - * The new priority. - */ -uint32_t -mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, - uint32_t subpriority) -{ - uint32_t res = 0; - struct mlx5_priv *priv = dev->data->dev_private; - - switch (priv->config.flow_prio) { - case RTE_DIM(priority_map_3): - res = priority_map_3[priority][subpriority]; - break; - case RTE_DIM(priority_map_5): - res = priority_map_5[priority][subpriority]; - break; - } - return res; -} - /** * Get Verbs flow counter by index. * @@ -2105,4 +2047,5 @@ const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = { .destroy = flow_verbs_destroy, .query = flow_verbs_query, .sync_domain = flow_verbs_sync_domain, + .discover_priorities = flow_verbs_discover_priorities, }; From patchwork Tue Oct 19 12:37:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102225 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63021A0C4D; Tue, 19 Oct 2021 14:38:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E548411B8; Tue, 19 Oct 2021 14:38:11 +0200 (CEST) Received: from AZHDRRW-EX01.nvidia.com (azhdrrw-ex01.nvidia.com [20.51.104.162]) by mails.dpdk.org (Postfix) with ESMTP id B82BB411BC; Tue, 19 Oct 2021 14:38:07 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.170) by mxs.oss.nvidia.com (10.13.234.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:38:06 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eu03SezVHtDN03OUFOShUeSKiOPEf+/m7UAg737Ri+gzW75pJ99soGEGq68gFaTtGIzhQB/bnpUsjVmefTulnKuacUko2JfPxXIPulsLrzgdz/e03XNV6bviJPTs/yeLwXxP98lOqAlRN7VNNNKKGeIoszA4DqN0dmVyOsfNGG5keuuBTREtb/dkT4wSIJqtNhpBHA60trCVZrto2hgHKhG8OeOoQzAV0rVLUvKMsKFFuG3xbR0LwghWnScy6B4D2FuRTNKp6W1CHpoAIR+dodAmivy1gt/wTBwGNuE18iRqVRzwkaqGDSv8VUew4xyDTfyD1cmWt6u0gIiSXlh8nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rF6PCjc6Foa8qHZ8zEJfNghrMALKfxb+VpRT8ojcUIE=; b=COC8ocTnWOgR6x0SA+kVVMEfVHnVwvpJmgxgel1scx1hzGMPodNmRX0LDfryeVM/rRVCYlm8+O6y8Uxfe5pIDDlw3Rxc9oHImosL7spQ8PYS8DVrekmbt3p/YXtdZdcNRjrxb2OFtFBcVPh9L9yo8aqiVz1BMZwpQbTJk+HxSw2I2q1G112yIcyZrgRci9eUln3TrQAQkhNOqrlLuW5gx4QNqwut1F2UIoK44aVZMkVu8vYOaLxN1/uptJ/tcTkAWFvBsey9hFRDxcWnFeqPDo5kLKAqVXY0M9zF8AKszIyrlIS5rW66tzld4vUOY3mqnXARTehviH2uFQmB+pvP4A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rF6PCjc6Foa8qHZ8zEJfNghrMALKfxb+VpRT8ojcUIE=; b=B3tw+agJ4Of+cHC4i3Xl7fkdvTe/LjfoTJvfGH+8Suv3A0Q1+xCDfn2PvPO9BrEtYKDPmlC80hUuBk0DiS9c5an1TK/8eobrySY8By0ekF4O7mGQV/MtfLp7Gdma+Ux3o5Kbf9Fo1rht9ybokEx2bYDI6SVEFM70hmQSRiZMpoph16UqaRHEfHnZNeJKMlIeoIbkmVrpLZMlIT3YBqnZybKHROk5CZ8K1nr05B/b7ndO9PWCHMQedlkKoIWUie86fe69K4xmIeAQTRO6r/Hh2A/E25UcDZ/9KJYjTLAaUvCEk20i2V+DfoJUwG14LMo0uiiFrZzYYiUT0qtqmMqiQA== Received: from DM5PR1101CA0005.namprd11.prod.outlook.com (2603:10b6:4:4c::15) by MN2PR12MB3789.namprd12.prod.outlook.com (2603:10b6:208:16a::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Tue, 19 Oct 2021 12:38:05 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::12) by DM5PR1101CA0005.outlook.office365.com (2603:10b6:4:4c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:38:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:38:02 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:55 +0000 From: Dmitry Kozlyuk To: CC: , Matan Azrad , Viacheslav Ovsiienko Date: Tue, 19 Oct 2021 15:37:21 +0300 Message-ID: <20211019123722.3414694-6-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2ff6d89c-1ec8-4f7e-7dda-08d992fd4a93 X-MS-TrafficTypeDiagnostic: MN2PR12MB3789: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3276; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: psfIpaz/6lK3z3GmGj6tC2K8twbIHKgux7g5odHN4rRMXfRh6SCDwFVvKVpCO5vzKufB1FyeEuZG8SwtPVjH1Q0Q6acY+J5Sk33XvZZ3x/VbD/V6kmvctUkSmRJiuBcfQ3Dt+Z9sc1brXYDqEP6CBI70IBM8EcvA5uCFmbbPjcCfZEah9U5Y3BhrAN6Wwmoi7OhK5Z9SPjnjPJW1lC7c4f3WKxUD/KjZoHWFZK1nngAk0FDi1qhjJsobNRH62FN7LaCcO42IRhviqMWzuab4vlMvxcOfde+PWAODKwytCCxr8ReZ0Kk8XG/qZQuULcL4eXZI3zDPtYfeBJbpKjqKYFjHjsr+xVCOxsPDtEEdZNop8txQpeTRGlVjXHWxiVXNOIizb7RG24JHl+ZxV+U0YiEHFaFxGO6M0J+HHupQfcqAS1BYDvlGlFQlzjf83Jv7bJe0y4ChdzC9rF0aqgge4n28j6b2E4dz2Z9o1ShYGn/9dxz7Oo5Z8KeDVwn/1GiYKHF2UWAKBD9Mk2IbYjTDH39RKWPEpWrOoLvPp9EUqlP31ThPZ6SEmsItgGRs/PLODOLl7gV8mABCvwhyZ3tY73ZIjE/NlkYbZb9NsxjjZ7uqgp5j873YpRiqNhmaJ5FYk2y+MU+PKPmg6Q51LxVzoQrlC4VFieZY7zc4JHCJf9Y8rpNu/Ln4j60hTp+pYdaTZjlJN51Or5GoDLbSVFshdQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(26005)(426003)(55016002)(54906003)(83380400001)(2616005)(86362001)(6916009)(8936002)(36756003)(1076003)(6286002)(6666004)(70586007)(70206006)(336012)(508600001)(47076005)(36860700001)(7696005)(16526019)(5660300002)(2906002)(30864003)(7636003)(316002)(107886003)(4326008)(8676002)(356005)(82310400003)(450100002)(186003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:38:02.0569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ff6d89c-1ec8-4f7e-7dda-08d992fd4a93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3789 Subject: [dpdk-dev] [PATCH v3 5/6] net/mlx5: create drop queue using DevX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Drop queue creation and destruction were not implemented for DevX flow engine and Verbs engine methods were used as a workaround. Implement these methods for DevX so that there is a valid queue ID that can be used regardless of queue configuration via API. Cc: stable@dpdk.org Signed-off-by: Dmitry Kozlyuk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 4 - drivers/net/mlx5/mlx5_devx.c | 211 ++++++++++++++++++++++++++----- 2 files changed, 180 insertions(+), 35 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 8ee7ada51b..985f0bd489 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1790,10 +1790,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } if (config->devx && config->dv_flow_en && config->dest_tir) { priv->obj_ops = devx_obj_ops; - priv->obj_ops.drop_action_create = - ibv_obj_ops.drop_action_create; - priv->obj_ops.drop_action_destroy = - ibv_obj_ops.drop_action_destroy; #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify; #else diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index a1db53577a..1e62108c94 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -226,17 +226,17 @@ mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj) * * @param dev * Pointer to Ethernet device. - * @param idx - * Queue index in DPDK Rx queue array. + * @param rxq_data + * RX queue data. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx) +mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, + struct mlx5_rxq_data *rxq_data) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx]; struct mlx5_rxq_ctrl *rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); struct mlx5_devx_create_rq_attr rq_attr = { 0 }; @@ -289,20 +289,20 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, uint16_t idx) * * @param dev * Pointer to Ethernet device. - * @param idx - * Queue index in DPDK Rx queue array. + * @param rxq_data + * RX queue data. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx) +mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, + struct mlx5_rxq_data *rxq_data) { struct mlx5_devx_cq *cq_obj = 0; struct mlx5_devx_cq_attr cq_attr = { 0 }; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_dev_ctx_shared *sh = priv->sh; - struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx]; struct mlx5_rxq_ctrl *rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data); @@ -497,13 +497,13 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel); } /* Create CQ using DevX API. */ - ret = mlx5_rxq_create_devx_cq_resources(dev, idx); + ret = mlx5_rxq_create_devx_cq_resources(dev, rxq_data); if (ret) { DRV_LOG(ERR, "Failed to create CQ."); goto error; } /* Create RQ using DevX API. */ - ret = mlx5_rxq_create_devx_rq_resources(dev, idx); + ret = mlx5_rxq_create_devx_rq_resources(dev, rxq_data); if (ret) { DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.", dev->data->port_id, idx); @@ -536,6 +536,11 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) * Pointer to Ethernet device. * @param log_n * Log of number of queues in the array. + * @param queues + * List of RX queue indices or NULL, in which case + * the attribute will be filled by drop queue ID. + * @param queues_n + * Size of @p queues array or 0 if it is NULL. * @param ind_tbl * DevX indirection table object. * @@ -563,6 +568,11 @@ mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev, } rqt_attr->rqt_max_size = priv->config.ind_table_max_size; rqt_attr->rqt_actual_size = rqt_n; + if (queues == NULL) { + for (i = 0; i < rqt_n; i++) + rqt_attr->rq_list[i] = priv->drop_queue.rxq->rq->id; + return rqt_attr; + } for (i = 0; i != queues_n; ++i) { struct mlx5_rxq_data *rxq = (*priv->rxqs)[queues[i]]; struct mlx5_rxq_ctrl *rxq_ctrl = @@ -595,11 +605,12 @@ mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n, { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_devx_rqt_attr *rqt_attr = NULL; + const uint16_t *queues = dev->data->dev_started ? ind_tbl->queues : + NULL; MLX5_ASSERT(ind_tbl); - rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, - ind_tbl->queues, - ind_tbl->queues_n); + rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, queues, + ind_tbl->queues_n); if (!rqt_attr) return -rte_errno; ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx, rqt_attr); @@ -670,7 +681,8 @@ mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl) * @param[in] hash_fields * Verbs protocol hash field to make the RSS on. * @param[in] ind_tbl - * Indirection table for TIR. + * Indirection table for TIR. If table queues array is NULL, + * a TIR for drop queue is assumed. * @param[in] tunnel * Tunnel type. * @param[out] tir_attr @@ -686,19 +698,27 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, int tunnel, struct mlx5_devx_tir_attr *tir_attr) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[ind_tbl->queues[0]]; - struct mlx5_rxq_ctrl *rxq_ctrl = - container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); - enum mlx5_rxq_type rxq_obj_type = rxq_ctrl->type; + enum mlx5_rxq_type rxq_obj_type; bool lro = true; uint32_t i; - /* Enable TIR LRO only if all the queues were configured for. */ - for (i = 0; i < ind_tbl->queues_n; ++i) { - if (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) { - lro = false; - break; + /* NULL queues designate drop queue. */ + if (ind_tbl->queues != NULL) { + struct mlx5_rxq_data *rxq_data = + (*priv->rxqs)[ind_tbl->queues[0]]; + struct mlx5_rxq_ctrl *rxq_ctrl = + container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); + rxq_obj_type = rxq_ctrl->type; + + /* Enable TIR LRO only if all the queues were configured for. */ + for (i = 0; i < ind_tbl->queues_n; ++i) { + if (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) { + lro = false; + break; + } } + } else { + rxq_obj_type = priv->drop_queue.rxq->rxq_ctrl->type; } memset(tir_attr, 0, sizeof(*tir_attr)); tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT; @@ -857,7 +877,7 @@ mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, } /** - * Create a DevX drop action for Rx Hash queue. + * Create a DevX drop Rx queue. * * @param dev * Pointer to Ethernet device. @@ -866,14 +886,99 @@ mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_devx_drop_action_create(struct rte_eth_dev *dev) +mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev) { - (void)dev; - DRV_LOG(ERR, "DevX drop action is not supported yet."); - rte_errno = ENOTSUP; + struct mlx5_priv *priv = dev->data->dev_private; + int socket_id = dev->device->numa_node; + struct mlx5_rxq_ctrl *rxq_ctrl; + struct mlx5_rxq_data *rxq_data; + struct mlx5_rxq_obj *rxq = NULL; + int ret; + + /* + * Initialize dummy control structures. + * They are required to hold pointers for cleanup + * and are only accessible via drop queue DevX objects. + */ + rxq_ctrl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_ctrl), + 0, socket_id); + if (rxq_ctrl == NULL) { + DRV_LOG(ERR, "Port %u could not allocate drop queue control", + dev->data->port_id); + rte_errno = ENOMEM; + goto error; + } + rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, socket_id); + if (rxq == NULL) { + DRV_LOG(ERR, "Port %u could not allocate drop queue object", + dev->data->port_id); + rte_errno = ENOMEM; + goto error; + } + rxq->rxq_ctrl = rxq_ctrl; + rxq_ctrl->type = MLX5_RXQ_TYPE_STANDARD; + rxq_ctrl->priv = priv; + rxq_ctrl->obj = rxq; + rxq_data = &rxq_ctrl->rxq; + /* Create CQ using DevX API. */ + ret = mlx5_rxq_create_devx_cq_resources(dev, rxq_data); + if (ret != 0) { + DRV_LOG(ERR, "Port %u drop queue CQ creation failed.", + dev->data->port_id); + goto error; + } + /* Create RQ using DevX API. */ + ret = mlx5_rxq_create_devx_rq_resources(dev, rxq_data); + if (ret != 0) { + DRV_LOG(ERR, "Port %u drop queue RQ creation failed.", + dev->data->port_id); + rte_errno = ENOMEM; + goto error; + } + /* Change queue state to ready. */ + ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RST2RDY); + if (ret != 0) + goto error; + /* Initialize drop queue. */ + priv->drop_queue.rxq = rxq; + return 0; +error: + ret = rte_errno; /* Save rte_errno before cleanup. */ + if (rxq != NULL) { + if (rxq->rq_obj.rq != NULL) + mlx5_devx_rq_destroy(&rxq->rq_obj); + if (rxq->cq_obj.cq != NULL) + mlx5_devx_cq_destroy(&rxq->cq_obj); + if (rxq->devx_channel) + mlx5_os_devx_destroy_event_channel + (rxq->devx_channel); + mlx5_free(rxq); + } + if (rxq_ctrl != NULL) + mlx5_free(rxq_ctrl); + rte_errno = ret; /* Restore rte_errno. */ return -rte_errno; } +/** + * Release drop Rx queue resources. + * + * @param dev + * Pointer to Ethernet device. + */ +static void +mlx5_rxq_devx_obj_drop_release(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq; + struct mlx5_rxq_ctrl *rxq_ctrl = rxq->rxq_ctrl; + + mlx5_rxq_devx_obj_release(rxq); + mlx5_free(rxq); + mlx5_free(rxq_ctrl); + priv->drop_queue.rxq = NULL; +} + /** * Release a drop hash Rx queue. * @@ -883,9 +988,53 @@ mlx5_devx_drop_action_create(struct rte_eth_dev *dev) static void mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev) { - (void)dev; - DRV_LOG(ERR, "DevX drop action is not supported yet."); - rte_errno = ENOTSUP; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq; + + if (hrxq->tir != NULL) + mlx5_devx_tir_destroy(hrxq); + if (hrxq->ind_table->ind_table != NULL) + mlx5_devx_ind_table_destroy(hrxq->ind_table); + if (priv->drop_queue.rxq->rq != NULL) + mlx5_rxq_devx_obj_drop_release(dev); +} + +/** + * Create a DevX drop action for Rx Hash queue. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_devx_drop_action_create(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq; + int ret; + + ret = mlx5_rxq_devx_obj_drop_create(dev); + if (ret != 0) { + DRV_LOG(ERR, "Cannot create drop RX queue"); + return ret; + } + /* hrxq->ind_table queues are NULL, drop RX queue ID will be used */ + ret = mlx5_devx_ind_table_new(dev, 0, hrxq->ind_table); + if (ret != 0) { + DRV_LOG(ERR, "Cannot create drop hash RX queue indirection table"); + goto error; + } + ret = mlx5_devx_hrxq_new(dev, hrxq, /* tunnel */ false); + if (ret != 0) { + DRV_LOG(ERR, "Cannot create drop hash RX queue"); + goto error; + } + return 0; +error: + mlx5_devx_drop_action_destroy(dev); + return ret; } /** From patchwork Tue Oct 19 12:37:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Kozlyuk X-Patchwork-Id: 102226 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3686A0C4D; Tue, 19 Oct 2021 14:38:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE05E411CA; Tue, 19 Oct 2021 14:38:13 +0200 (CEST) Received: from AZHDRRW-EX02.NVIDIA.COM (azhdrrw-ex02.nvidia.com [20.64.145.131]) by mails.dpdk.org (Postfix) with ESMTP id 2FB2E4119B; Tue, 19 Oct 2021 14:38:10 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.169) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.15; Tue, 19 Oct 2021 05:38:09 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iOiD5wM983/SuVNxItVrDyPqPNptnx8r1t2KgzE4r1TN5/Y7TjLbtxsad3OomNl1GoNvzEOSsZlN8unEZp5PjYiA8w8TeoC/niYUj34hT4jfXvMF910nCLoWoZY4q9VUb6Zcoiv3AL6G0LxlEN6H80PzepalnFRIejzv6s7qVq9Rt6fXbQuL+dUtwELkldjaIyFa6RqGR0Wb6/NCnqggQoYnmvLA2ofK0ILDb0Nwt2J7ooBAz9ZUYSyYBnKXIoFsh3Cgyuy196JMg5nFdqHY4UOxuF1/wBuZLhRuzmy7sYvnZINQc6nWVxf0vvikNLW9ZuGWtDUcaHNFUw0RrrH6hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JYkVMJ8vaoSQDwl1W6yxyP3Fv43hkDLUBJvhvAbizK4=; b=fLlwh87ZoNXuNfGKYsKanIjor1c29fVlrqhR7lZEvgxGHc7z1eXu3IULJcsgPdTF4sRdM/lMpaQer0OJPw6xCWDXfkktCiecVPXoP2rY15TrI7sN/wu0398YxDWIHOkl9XWfg9mh2HCjILwttQg9fyV7r6UCuDWjtEgiNUi9AvX1XIC/p1jYOI8o3bh1fJQEqFmvpVi4W4Lks61M8MAHdikonWIRlfhOvB9v8sIhrK0kINHcPYENXshY6tMSxExhIs6OFC8F60N4uCyCV4iVo8/ey/fBhYfMPwQPbaiZYEXZNi9RNipAE4h7po6FpeS9FlTeoaMsppn/5/P9dxUUxA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JYkVMJ8vaoSQDwl1W6yxyP3Fv43hkDLUBJvhvAbizK4=; b=egheKosXs1Zj/xV4LYA4EthP1CWdRUcsP38m+hQGSfEd+xN+pPkpWqRuTUabcBadZqbZzipLIXlWni1zJ4sjUFOa3A1xJs4qX85Wwc2uArPynRqZD5NhPyHfj/MSgUKkphuJEIM3Zakc+2rPYVBYmwQZtIVZhA5R2ZDonbJvJpFQwSSQLMOY4oRFLy/2/q7IKg6dw5hZnQvI3um3QMlPxUhDgv626G1k+zpCw2BhWIfo8ZmgklEzYzot1YjKnRCbt1ZEJ7kLpN43QLuFhLNk1LW+WT9FYiXNqf91fGffu0N1dZE8XsEOjksGM2saYRZ/E40BHkSzuNB3KYjWrxveXw== Received: from DM5PR1101CA0002.namprd11.prod.outlook.com (2603:10b6:4:4c::12) by DM6PR12MB2969.namprd12.prod.outlook.com (2603:10b6:5:115::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; Tue, 19 Oct 2021 12:38:07 +0000 Received: from DM6NAM11FT013.eop-nam11.prod.protection.outlook.com (2603:10b6:4:4c:cafe::f7) by DM5PR1101CA0002.outlook.office365.com (2603:10b6:4:4c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16 via Frontend Transport; Tue, 19 Oct 2021 12:38:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT013.mail.protection.outlook.com (10.13.173.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Tue, 19 Oct 2021 12:38:06 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 19 Oct 2021 12:37:57 +0000 From: Dmitry Kozlyuk To: CC: , , Matan Azrad , Viacheslav Ovsiienko Date: Tue, 19 Oct 2021 15:37:22 +0300 Message-ID: <20211019123722.3414694-7-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211019123722.3414694-1-dkozlyuk@nvidia.com> References: <20211015161822.3099818-1-dkozlyuk@nvidia.com> <20211019123722.3414694-1-dkozlyuk@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e7e9710e-7a70-44b9-c367-08d992fd4d5a X-MS-TrafficTypeDiagnostic: DM6PR12MB2969: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:291; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LAs/9nhMfrM594Od/mDBwTAGdTSqTfH6XpLCA3yIUg7uhNAZsLhd+DxY8SahVq07AQNhiefBZycpIbuSakIpnQH0yEx5zPIqQSlZzFXvDTuKs7vRLq4haQ6ewLjTJagrAKFYniu9JYdZ6XahOl1sCKyrch8XqRmoJPajIA6I5MCe/fYOnRwgsxq5dtWsOk6M9I1+T+KV6C1X2vFtJch3NmJmBCkUI3RAqW7MW5ZNFpJZyJTPVL576PxNk0CGcc1oSOJo+Ny6lq4TP312u8Vqu7pUpqGZxxCldEt4DnRUrIIOanOmrLOlPBTgjRPHPSO7eu3F6QDPi8z9KcbphvHQVzdLI61NWOeIabp5aUSr58lKsgDNtLvy7E5tmV81tzhdbpeuSdZZox7M/oowQWAAgfuPgjJeJqMPA3y7pqM02rEHdZI3QS03sJtaQpzHD71rmljRnI1MwxuVAvLve2P1M4LHtE5ZUeyQ7ZFJWlg5N2BN7RFbqx7jSvs/SK8RzdgBaSY2FMnhxIb6HKjqsZn18yjBmSTM5M5S4zHurtJuFw4vQHpb0MQGS5r/J9Ro/6xhutWug9XFXUDJBfjtznMtR6KSLKdttsmnncnFCAk+pA/i8eLrevkjeaCkSFkDZUrHuvEcjq5I42joCKH1L4j4xCwuJJ7EcDutbQ6PSkZuhkJC4FYHofzl5C4hwdUncgcwAzTMFqS85FiR6Vz01PzmyA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(7696005)(70206006)(70586007)(107886003)(54906003)(316002)(6916009)(86362001)(6666004)(36860700001)(6286002)(26005)(426003)(83380400001)(1076003)(30864003)(8936002)(186003)(356005)(508600001)(2616005)(82310400003)(7636003)(336012)(4326008)(450100002)(47076005)(8676002)(36756003)(55016002)(16526019)(2906002)(5660300002); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2021 12:38:06.6983 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7e9710e-7a70-44b9-c367-08d992fd4d5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2969 Subject: [dpdk-dev] [PATCH v3 6/6] net/mlx5: preserve indirect actions on restart X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" MLX5 PMD uses reference counting to manage RX queue resources. After port stop shared RSS actions kept references to RX queues, preventing resource release. As a result, internal PMD mempool for such queues had been exhausted after a number of port restarts. Diagnostic message from rte_eth_dev_start(): Rx queue allocation failed: Cannot allocate memory Dereference RX queues used by indirect actions on port stop (detach) and restore references on port start (attach) in order to allow RX queue resource release, but keep indirect RSS across the port restart. Replace queue IDs in HW by drop queue ID on detach and restore actual queue IDs on attach. When the port is stopped, create indirect RSS in the detached state. As a result, MLX5 PMD is able to keep all its indirect actions across port restart. Advertise this capability. Fixes: 4b61b8774be9 ("ethdev: introduce indirect flow action") Cc: bingz@nvidia.com Cc: stable@dpdk.org Signed-off-by: Dmitry Kozlyuk Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_ethdev.c | 1 + drivers/net/mlx5/mlx5_flow.c | 194 ++++++++++++++++++++++++++++---- drivers/net/mlx5/mlx5_flow.h | 2 + drivers/net/mlx5/mlx5_rx.h | 4 + drivers/net/mlx5/mlx5_rxq.c | 99 ++++++++++++++-- drivers/net/mlx5/mlx5_trigger.c | 10 ++ 6 files changed, 276 insertions(+), 34 deletions(-) diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 82e2284d98..419fec3e4e 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -321,6 +321,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->rx_offload_capa = (mlx5_get_rx_port_offloads() | info->rx_queue_offload_capa); info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); + info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; info->if_index = mlx5_ifindex(dev); info->reta_size = priv->reta_idx_n ? priv->reta_idx_n : config->ind_table_max_size; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index bfc3e20c9a..c10b911259 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1560,6 +1560,58 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action, return 0; } +/** + * Validate queue numbers for device RSS. + * + * @param[in] dev + * Configured device. + * @param[in] queues + * Array of queue numbers. + * @param[in] queues_n + * Size of the @p queues array. + * @param[out] error + * On error, filled with a textual error description. + * @param[out] queue + * On error, filled with an offending queue index in @p queues array. + * + * @return + * 0 on success, a negative errno code on error. + */ +static int +mlx5_validate_rss_queues(const struct rte_eth_dev *dev, + const uint16_t *queues, uint32_t queues_n, + const char **error, uint32_t *queue_idx) +{ + const struct mlx5_priv *priv = dev->data->dev_private; + enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; + uint32_t i; + + for (i = 0; i != queues_n; ++i) { + struct mlx5_rxq_ctrl *rxq_ctrl; + + if (queues[i] >= priv->rxqs_n) { + *error = "queue index out of range"; + *queue_idx = i; + return -EINVAL; + } + if (!(*priv->rxqs)[queues[i]]) { + *error = "queue is not configured"; + *queue_idx = i; + return -EINVAL; + } + rxq_ctrl = container_of((*priv->rxqs)[queues[i]], + struct mlx5_rxq_ctrl, rxq); + if (i == 0) + rxq_type = rxq_ctrl->type; + if (rxq_type != rxq_ctrl->type) { + *error = "combining hairpin and regular RSS queues is not supported"; + *queue_idx = i; + return -ENOTSUP; + } + } + return 0; +} + /* * Validate the rss action. * @@ -1580,8 +1632,9 @@ mlx5_validate_action_rss(struct rte_eth_dev *dev, { struct mlx5_priv *priv = dev->data->dev_private; const struct rte_flow_action_rss *rss = action->conf; - enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; - unsigned int i; + int ret; + const char *message; + uint32_t queue_idx; if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) @@ -1645,27 +1698,12 @@ mlx5_validate_action_rss(struct rte_eth_dev *dev, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, "No queues configured"); - for (i = 0; i != rss->queue_num; ++i) { - struct mlx5_rxq_ctrl *rxq_ctrl; - - if (rss->queue[i] >= priv->rxqs_n) - return rte_flow_error_set - (error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION_CONF, - &rss->queue[i], "queue index out of range"); - if (!(*priv->rxqs)[rss->queue[i]]) - return rte_flow_error_set - (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, - &rss->queue[i], "queue is not configured"); - rxq_ctrl = container_of((*priv->rxqs)[rss->queue[i]], - struct mlx5_rxq_ctrl, rxq); - if (i == 0) - rxq_type = rxq_ctrl->type; - if (rxq_type != rxq_ctrl->type) - return rte_flow_error_set - (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION_CONF, - &rss->queue[i], - "combining hairpin and regular RSS queues is not supported"); + ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, + &message, &queue_idx); + if (ret != 0) { + return rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + &rss->queue[queue_idx], message); } return 0; } @@ -8547,6 +8585,116 @@ mlx5_action_handle_flush(struct rte_eth_dev *dev) return ret; } +/** + * Validate existing indirect actions against current device configuration + * and attach them to device resources. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_action_handle_attach(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_indexed_pool *ipool = + priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS]; + struct mlx5_shared_action_rss *shared_rss, *shared_rss_last; + int ret = 0; + uint32_t idx; + + ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { + struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; + const char *message; + uint32_t queue_idx; + + ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, + ind_tbl->queues_n, + &message, &queue_idx); + if (ret != 0) { + DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", + dev->data->port_id, ind_tbl->queues[queue_idx], + message); + break; + } + } + if (ret != 0) + return ret; + ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { + struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; + + ret = mlx5_ind_table_obj_attach(dev, ind_tbl); + if (ret != 0) { + DRV_LOG(ERR, "Port %u could not attach " + "indirection table obj %p", + dev->data->port_id, (void *)ind_tbl); + goto error; + } + } + return 0; +error: + shared_rss_last = shared_rss; + ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { + struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; + + if (shared_rss == shared_rss_last) + break; + if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) + DRV_LOG(CRIT, "Port %u could not detach " + "indirection table obj %p on rollback", + dev->data->port_id, (void *)ind_tbl); + } + return ret; +} + +/** + * Detach indirect actions of the device from its resources. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_action_handle_detach(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_indexed_pool *ipool = + priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS]; + struct mlx5_shared_action_rss *shared_rss, *shared_rss_last; + int ret = 0; + uint32_t idx; + + ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { + struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; + + ret = mlx5_ind_table_obj_detach(dev, ind_tbl); + if (ret != 0) { + DRV_LOG(ERR, "Port %u could not detach " + "indirection table obj %p", + dev->data->port_id, (void *)ind_tbl); + goto error; + } + } + return 0; +error: + shared_rss_last = shared_rss; + ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { + struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; + + if (shared_rss == shared_rss_last) + break; + if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) + DRV_LOG(CRIT, "Port %u could not attach " + "indirection table obj %p on rollback", + dev->data->port_id, (void *)ind_tbl); + } + return ret; +} + #ifndef HAVE_MLX5DV_DR #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) #else diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 8f94125f26..6bc7946cc3 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1574,6 +1574,8 @@ void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, struct mlx5_flow_meter_policy *mtr_policy); int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev); +int mlx5_action_handle_attach(struct rte_eth_dev *dev); +int mlx5_action_handle_detach(struct rte_eth_dev *dev); int mlx5_action_handle_flush(struct rte_eth_dev *dev); void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 2b7ad3e48b..d44c8078de 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -222,6 +222,10 @@ int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, struct mlx5_ind_table_obj *ind_tbl, uint16_t *queues, const uint32_t queues_n, bool standalone); +int mlx5_ind_table_obj_attach(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl); +int mlx5_ind_table_obj_detach(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl); struct mlx5_list_entry *mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx); int mlx5_hrxq_match_cb(void *tool_ctx, struct mlx5_list_entry *entry, void *cb_ctx); diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index b68443bed5..fd2b5779ff 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2015,6 +2015,26 @@ mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues, return ind_tbl; } +static int +mlx5_ind_table_obj_check_standalone(struct rte_eth_dev *dev __rte_unused, + struct mlx5_ind_table_obj *ind_tbl) +{ + uint32_t refcnt; + + refcnt = __atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED); + if (refcnt <= 1) + return 0; + /* + * Modification of indirection tables having more than 1 + * reference is unsupported. + */ + DRV_LOG(DEBUG, + "Port %u cannot modify indirection table %p (refcnt %u > 1).", + dev->data->port_id, (void *)ind_tbl, refcnt); + rte_errno = EINVAL; + return -rte_errno; +} + /** * Modify an indirection table. * @@ -2047,18 +2067,8 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, MLX5_ASSERT(standalone); RTE_SET_USED(standalone); - if (__atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED) > 1) { - /* - * Modification of indirection ntables having more than 1 - * reference unsupported. Intended for standalone indirection - * tables only. - */ - DRV_LOG(DEBUG, - "Port %u cannot modify indirection table (refcnt> 1).", - dev->data->port_id); - rte_errno = EINVAL; + if (mlx5_ind_table_obj_check_standalone(dev, ind_tbl) < 0) return -rte_errno; - } for (i = 0; i != queues_n; ++i) { if (!mlx5_rxq_get(dev, queues[i])) { ret = -rte_errno; @@ -2084,6 +2094,73 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev, return ret; } +/** + * Attach an indirection table to its queues. + * + * @param dev + * Pointer to Ethernet device. + * @param ind_table + * Indirection table to attach. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_ind_table_obj_attach(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl) +{ + unsigned int i; + int ret; + + ret = mlx5_ind_table_obj_modify(dev, ind_tbl, ind_tbl->queues, + ind_tbl->queues_n, true); + if (ret != 0) { + DRV_LOG(ERR, "Port %u could not modify indirect table obj %p", + dev->data->port_id, (void *)ind_tbl); + return ret; + } + for (i = 0; i < ind_tbl->queues_n; i++) + mlx5_rxq_get(dev, ind_tbl->queues[i]); + return 0; +} + +/** + * Detach an indirection table from its queues. + * + * @param dev + * Pointer to Ethernet device. + * @param ind_table + * Indirection table to detach. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_ind_table_obj_detach(struct rte_eth_dev *dev, + struct mlx5_ind_table_obj *ind_tbl) +{ + struct mlx5_priv *priv = dev->data->dev_private; + const unsigned int n = rte_is_power_of_2(ind_tbl->queues_n) ? + log2above(ind_tbl->queues_n) : + log2above(priv->config.ind_table_max_size); + unsigned int i; + int ret; + + ret = mlx5_ind_table_obj_check_standalone(dev, ind_tbl); + if (ret != 0) + return ret; + MLX5_ASSERT(priv->obj_ops.ind_table_modify); + ret = priv->obj_ops.ind_table_modify(dev, n, NULL, 0, ind_tbl); + if (ret != 0) { + DRV_LOG(ERR, "Port %u could not modify indirect table obj %p", + dev->data->port_id, (void *)ind_tbl); + return ret; + } + for (i = 0; i < ind_tbl->queues_n; i++) + mlx5_rxq_release(dev, ind_tbl->queues[i]); + return ret; +} + int mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry, void *cb_ctx) diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 54173bfacb..c3adf5082e 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -14,6 +14,7 @@ #include #include "mlx5.h" +#include "mlx5_flow.h" #include "mlx5_mr.h" #include "mlx5_rx.h" #include "mlx5_tx.h" @@ -1113,6 +1114,14 @@ mlx5_dev_start(struct rte_eth_dev *dev) mlx5_rxq_timestamp_set(dev); /* Set a mask and offset of scheduling on timestamp into Tx queues. */ mlx5_txq_dynf_timestamp_set(dev); + /* Attach indirection table objects detached on port stop. */ + ret = mlx5_action_handle_attach(dev); + if (ret) { + DRV_LOG(ERR, + "port %u failed to attach indirect actions: %s", + dev->data->port_id, rte_strerror(rte_errno)); + goto error; + } /* * In non-cached mode, it only needs to start the default mreg copy * action and no flow created by application exists anymore. @@ -1185,6 +1194,7 @@ mlx5_dev_stop(struct rte_eth_dev *dev) /* All RX queue flags will be cleared in the flush interface. */ mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); mlx5_flow_meter_rxq_flush(dev); + mlx5_action_handle_detach(dev); mlx5_rx_intr_vec_disable(dev); priv->sh->port[priv->dev_port - 1].ih_port_id = RTE_MAX_ETHPORTS; priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;