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Signed-off-by: Hemant Agrawal Signed-off-by: Nipun Gupta --- doc/guides/bbdevs/features/default.ini | 1 + doc/guides/prog_guide/bbdev.rst | 6 ++++++ lib/bbdev/rte_bbdev_op.h | 14 ++++++++++++-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/doc/guides/bbdevs/features/default.ini b/doc/guides/bbdevs/features/default.ini index 5fe267a625..ae5aacf8f7 100644 --- a/doc/guides/bbdevs/features/default.ini +++ b/doc/guides/bbdevs/features/default.ini @@ -14,3 +14,4 @@ LLR/HARQ Compression = External DDR Access = HW Accelerated = BBDEV API = +Big Endian Processing = diff --git a/doc/guides/prog_guide/bbdev.rst b/doc/guides/prog_guide/bbdev.rst index 9619280ffc..6540b514bb 100644 --- a/doc/guides/prog_guide/bbdev.rst +++ b/doc/guides/prog_guide/bbdev.rst @@ -747,6 +747,9 @@ given below. |RTE_BBDEV_LDPC_ENC_CONCATENATION | | Set if a device supports concatenation of non byte aligned output | +--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_ENC_BIG_ENDIAN | +| Set if a device supports Big Endian data processing | ++--------------------------------------------------------------------+ The structure passed for each LDPC encode operation is given below, with the operation flags forming a bitmask in the ``op_flags`` field. @@ -942,6 +945,9 @@ given below. |RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | | Set if a device supports loopback access to HARQ internal memory | +--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_DEC_BIG_ENDIAN | +| Set if a device supports Big Endian data processing | ++--------------------------------------------------------------------+ The structure passed for each LDPC decode operation is given below, with the operation flags forming a bitmask in the ``op_flags`` field. diff --git a/lib/bbdev/rte_bbdev_op.h b/lib/bbdev/rte_bbdev_op.h index f946842727..9e9b5be81f 100644 --- a/lib/bbdev/rte_bbdev_op.h +++ b/lib/bbdev/rte_bbdev_op.h @@ -186,7 +186,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks { * for HARQ memory. If not set, it is assumed the filler bits are not * in HARQ memory and handled directly by the LDPC decoder. */ - RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18) + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18), + /** Set if a device supports Big Endian data processing. + * If not set Little Endian data processing is supported by + * default. + */ + RTE_BBDEV_LDPC_DEC_BIG_ENDIAN = (1ULL << 8) }; /** Flags for LDPC encoder operation and capability structure */ @@ -206,7 +211,12 @@ enum rte_bbdev_op_ldpcenc_flag_bitmasks { /** Set if a device supports scatter-gather functionality. */ RTE_BBDEV_LDPC_ENC_SCATTER_GATHER = (1ULL << 6), /** Set if a device supports concatenation of non byte aligned output */ - RTE_BBDEV_LDPC_ENC_CONCATENATION = (1ULL << 7) + RTE_BBDEV_LDPC_ENC_CONCATENATION = (1ULL << 7), + /** Set if a device supports Big Endian data processing + * If not set Little Endian data processing is supported by + * default. + */ + RTE_BBDEV_LDPC_ENC_BIG_ENDIAN = (1ULL << 8) }; /** Flags for the Code Block/Transport block mode */ From patchwork Sun Sep 12 12:15:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98711 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6440A0C4B; Sun, 12 Sep 2021 14:15:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 79498410F6; Sun, 12 Sep 2021 14:15:42 +0200 (CEST) Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2084.outbound.protection.outlook.com [40.107.21.84]) by mails.dpdk.org (Postfix) with ESMTP id 266F9410E7 for ; Sun, 12 Sep 2021 14:15:41 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gm6n6HPfkbGcQOvMkAyrEtARWH0e6eZjJ/EIn3nx1BaXjKd8HeGfVFrP/qFnLkRtuvC6YGkzFY/QkjOOoChfRbNkJ48EnQznotlCWkpA3vDGkAi7Ck6QISuGllaxJ0VBUOyNQrTXPLTy8Cb2NjpZ25YMfkJVgg2USvt69D/zOR3Qz4KvufGoaK5X8JHtoMruAsVuHxv/AePWBjK1pfyXERMFF4FURxms07U2OM5s3HdbBW5zqvG2WQH7puBG9D8pu+mqChSdzqsnYy3ZZs5s/h7MCCnNh6TomdDABlqNLijbKFICObzivrF24C3M8sx1H6bVy39kDwYieXPzSGHm+Q== ARC-Message-Signature: i=1; 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Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- MAINTAINERS | 9 ++ drivers/baseband/la12xx/bbdev_la12xx.c | 109 ++++++++++++++++++ .../baseband/la12xx/bbdev_la12xx_pmd_logs.h | 26 +++++ drivers/baseband/la12xx/meson.build | 6 + drivers/baseband/la12xx/version.map | 3 + drivers/baseband/meson.build | 1 + 6 files changed, 154 insertions(+) create mode 100644 drivers/baseband/la12xx/bbdev_la12xx.c create mode 100644 drivers/baseband/la12xx/bbdev_la12xx_pmd_logs.h create mode 100644 drivers/baseband/la12xx/meson.build create mode 100644 drivers/baseband/la12xx/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 266f5ac1da..a63e672c9e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1288,6 +1288,15 @@ F: drivers/event/opdl/ F: doc/guides/eventdevs/opdl.rst +Baseband Drivers +---------------- + +NXP LA12xx driver +M: Hemant Agrawal +M: Nipun Gupta +F: drivers/baseband/la12xx/ + + Rawdev Drivers -------------- diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c new file mode 100644 index 0000000000..7050b17728 --- /dev/null +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020-2021 NXP + */ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define DRIVER_NAME baseband_la12xx + +RTE_LOG_REGISTER(bbdev_la12xx_logtype, pmd.bb.la12xx, NOTICE); + +/* private data structure */ +struct bbdev_la12xx_private { + unsigned int max_nb_queues; /**< Max number of queues */ +}; +/* Create device */ +static int +la12xx_bbdev_create(struct rte_vdev_device *vdev) +{ + struct rte_bbdev *bbdev; + const char *name = rte_vdev_device_name(vdev); + + PMD_INIT_FUNC_TRACE(); + + bbdev = rte_bbdev_allocate(name); + if (bbdev == NULL) + return -ENODEV; + + bbdev->data->dev_private = rte_zmalloc(name, + sizeof(struct bbdev_la12xx_private), + RTE_CACHE_LINE_SIZE); + if (bbdev->data->dev_private == NULL) { + rte_bbdev_release(bbdev); + return -ENOMEM; + } + + bbdev->dev_ops = NULL; + bbdev->device = &vdev->device; + bbdev->data->socket_id = 0; + bbdev->intr_handle = NULL; + + /* register rx/tx burst functions for data path */ + bbdev->dequeue_enc_ops = NULL; + bbdev->dequeue_dec_ops = NULL; + bbdev->enqueue_enc_ops = NULL; + bbdev->enqueue_dec_ops = NULL; + + return 0; +} + +/* Initialise device */ +static int +la12xx_bbdev_probe(struct rte_vdev_device *vdev) +{ + const char *name; + + PMD_INIT_FUNC_TRACE(); + + if (vdev == NULL) + return -EINVAL; + + name = rte_vdev_device_name(vdev); + if (name == NULL) + return -EINVAL; + + return la12xx_bbdev_create(vdev); +} + +/* Uninitialise device */ +static int +la12xx_bbdev_remove(struct rte_vdev_device *vdev) +{ + struct rte_bbdev *bbdev; + const char *name; + + PMD_INIT_FUNC_TRACE(); + + if (vdev == NULL) + return -EINVAL; + + name = rte_vdev_device_name(vdev); + if (name == NULL) + return -EINVAL; + + bbdev = rte_bbdev_get_named_dev(name); + if (bbdev == NULL) + return -EINVAL; + + rte_free(bbdev->data->dev_private); + + return rte_bbdev_release(bbdev); +} + +static struct rte_vdev_driver bbdev_la12xx_pmd_drv = { + .probe = la12xx_bbdev_probe, + .remove = la12xx_bbdev_remove +}; + +RTE_PMD_REGISTER_VDEV(DRIVER_NAME, bbdev_la12xx_pmd_drv); diff --git a/drivers/baseband/la12xx/bbdev_la12xx_pmd_logs.h b/drivers/baseband/la12xx/bbdev_la12xx_pmd_logs.h new file mode 100644 index 0000000000..9dfa1cc458 --- /dev/null +++ b/drivers/baseband/la12xx/bbdev_la12xx_pmd_logs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 NXP + */ + +#ifndef _BBDEV_LA12XX_PMD_LOGS_H_ +#define _BBDEV_LA12XX_PMD_LOGS_H_ + +#define rte_bbdev_log(level, fmt, ...) \ + rte_log(RTE_LOG_ ## level, bbdev_la12xx_logtype, fmt "\n", \ + ##__VA_ARGS__) + +#ifdef RTE_LIBRTE_BBDEV_DEBUG +#define rte_bbdev_log_debug(fmt, ...) \ + rte_bbdev_log(DEBUG, "la12xx_pmd: " fmt, \ + ##__VA_ARGS__) +#else +#define rte_bbdev_log_debug(fmt, ...) +#endif + +#define PMD_INIT_FUNC_TRACE() rte_bbdev_log_debug(">>") + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define rte_bbdev_dp_log(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt, ## args) + +#endif /* _BBDEV_LA12XX_PMD_LOGS_H_ */ diff --git a/drivers/baseband/la12xx/meson.build b/drivers/baseband/la12xx/meson.build new file mode 100644 index 0000000000..7a017dcffa --- /dev/null +++ b/drivers/baseband/la12xx/meson.build @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2020-2021 NXP + +deps += ['bbdev', 'bus_vdev', 'ring'] + +sources = files('bbdev_la12xx.c') diff --git a/drivers/baseband/la12xx/version.map b/drivers/baseband/la12xx/version.map new file mode 100644 index 0000000000..4a76d1d52d --- /dev/null +++ b/drivers/baseband/la12xx/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; diff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build index 5ee61d5323..ccd1eebc3b 100644 --- a/drivers/baseband/meson.build +++ b/drivers/baseband/meson.build @@ -11,6 +11,7 @@ drivers = [ 'fpga_lte_fec', 'null', 'turbo_sw', + 'la12xx', ] log_prefix = 'pmd.bb' From patchwork Sun Sep 12 12:15:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98712 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAD2FA0C4B; Sun, 12 Sep 2021 14:16:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B3733410FC; Sun, 12 Sep 2021 14:15:45 +0200 (CEST) Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-eopbgr60064.outbound.protection.outlook.com [40.107.6.64]) by mails.dpdk.org (Postfix) with ESMTP id 972E3410FA for ; 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Sun, 12 Sep 2021 12:15:42 +0000 From: Nipun Gupta To: dev@dpdk.org, gakhil@marvell.com, nicolas.chautru@intel.com Cc: david.marchand@redhat.com, hemant.agrawal@nxp.com, Nipun Gupta Date: Sun, 12 Sep 2021 17:45:04 +0530 Message-Id: <20210912121510.22699-4-nipun.gupta@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210912121510.22699-1-nipun.gupta@nxp.com> References: <20210318063421.14895-1-hemant.agrawal@nxp.com> <20210912121510.22699-1-nipun.gupta@nxp.com> X-ClientProxiedBy: SG2PR0601CA0003.apcprd06.prod.outlook.com (2603:1096:3::13) To DB9PR04MB8429.eurprd04.prod.outlook.com (2603:10a6:10:24e::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv03274.swis.in-blr01.nxp.com (14.142.151.118) by SG2PR0601CA0003.apcprd06.prod.outlook.com (2603:1096:3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Sun, 12 Sep 2021 12:15:40 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3d9f952a-3776-4f40-2233-08d975e70a77 X-MS-TrafficTypeDiagnostic: DB7PR04MB4778: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; 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PTR:; CAT:NONE; SFS:(4636009)(346002)(396003)(366004)(136003)(39860400002)(376002)(66946007)(36756003)(1076003)(66556008)(38350700002)(38100700002)(8676002)(8936002)(186003)(4326008)(956004)(2616005)(52116002)(6486002)(316002)(55236004)(86362001)(5660300002)(44832011)(478600001)(1006002)(6666004)(83380400001)(7696005)(2906002)(26005)(66476007)(110426009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /4CqrRbFbliP2DdR13fC/dmNCq4Rk+Gtx+6SOb10IziMsikTULUXq8lSU468swr+KlnP7iAvIRNbZ1z8V1UdQ7lZgfyFhSa47lJGaaQ8mjPMPIoLhrcBX6/JOIMSl29mfwTwW0hcqg4mAjJpwlvEP75ufB9cnl4tpozJrRImGUpQWbwJFgV6aaf5dyi3LACjElQoIkZYSYJJP+M6i0GG6ospLJ6sUrdp7Jxn1CQvYBlYtzMfa8ELeJLcMEtfkVLaUy5iLNqZNVkijkZbWSSQWclQvyjO/W6FQiTHnCeehsOpMnw1G4kKJM+3I6RcYoTVbOOH2y8UJDa4d83blm+2Pi1iwvQQB4piDHFVw16mezVgt0wKLp7aInr42+5tubJ5zHkTgaYNged64Y/nAr0cnn584NWoDhw0Zch9hvUEN9gup37rgPus4UUdH5KD6hYFlhxD9eMt9LnB5UnA6S7W7dU3M91WBZgTUHKtfMeZvxy1jWIxaS9/GPIeodffcYZQftJDrZVgSH+kRulW+g/+PSjfXVj0GHXqvsnJd9iefFmqJKM3W3+D7LKPSkkaQhbr+fNYcsKaD7+wqTAsidnQii4E1yYA86b+t4ZWFhXj+ukq4wx8uC9TyOqkky5NLRnRxHokp/7kIJD0BzQi0OAo1octtauUZ6s2hozt3KHGUkQw1UdUZXXhreqEYEY9CNFVyR8Ebg6dq/Cl5/kxcyYc2/u6zWzPa3IZMF1o/QFB7VOlGsT4SJ3/bhW3dr7XGpYeEg8pOksVATgrcFsJTiF6J5p3Bpfpx+5hNHY7PzUMstKcNXbiY2U9iUWbIo2YteFEnB823ax08eh5lOcMZMy4tOoyXQmH4fP23dO0v960RHJa0ObVX/sgCm0qo2jExoHMfvuWccHWP2FddurGQR9lew67cR8eO8gsgxJaQA/LWm3t+LosfXfRTGzXkxDSPeyg0C2SCLzuuqRpe4mgo0A2aY+pVYbmyk/3MgxLCVt6GiAMkQ+hi7ziRrkm2ApSVERdkZV17kkbetN27VgZgKXwYzPXmLyzEUdLuR49V78nAN6sOxSiTGCVmQbpP2RR/k9YSKLWGGoQvUBNiVgLFlbH5CbuMiJjWW8pjO7x7zdN4cV+Nl0k13lvCGevAZTTWluQeFQf7LLy9cu76oghEQJfmv+uEv8fSrDVk9ZVP9VVJdWqy6BUlc745b2+QRtHCRHgHUH/Q1uTW0Sg9GIPJUM2YDAeKWjFPi8+hnin5TqUN9HbNVjOogB3vnTB+L7PLiZ3kJrLW9+0dBYBCxPKT4krpBLXuYFg0fwNiXfkwIaLIQ382mhG8y6qBchPX1o13MhU X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3d9f952a-3776-4f40-2233-08d975e70a77 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8429.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2021 12:15:42.4479 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7O0polKa8XacGEpMDYB6nZt6pli3NPgdj/08LX5NlXzLd9xGiYGrmLlCPU1HuGFMW5WNIj8APJKAEvM7xUJHPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4778 Subject: [dpdk-dev] [PATCH v5 3/9] baseband/la12xx: add devargs for max queues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal This patch adds dev args to take max queues as input Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- drivers/baseband/la12xx/bbdev_la12xx.c | 72 +++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index 7050b17728..8886b35429 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -19,13 +19,72 @@ RTE_LOG_REGISTER(bbdev_la12xx_logtype, pmd.bb.la12xx, NOTICE); +/* Initialisation params structure that can be used by LA12xx BBDEV driver */ +struct bbdev_la12xx_params { + uint8_t queues_num; /*< LA12xx BBDEV queues number */ +}; + +#define LA12XX_MAX_NB_QUEUES_ARG "max_nb_queues" + +static const char * const bbdev_la12xx_valid_params[] = { + LA12XX_MAX_NB_QUEUES_ARG, +}; + /* private data structure */ struct bbdev_la12xx_private { unsigned int max_nb_queues; /**< Max number of queues */ }; +static inline int +parse_u16_arg(const char *key, const char *value, void *extra_args) +{ + uint16_t *u16 = extra_args; + + unsigned int long result; + if ((value == NULL) || (extra_args == NULL)) + return -EINVAL; + errno = 0; + result = strtoul(value, NULL, 0); + if ((result >= (1 << 16)) || (errno != 0)) { + rte_bbdev_log(ERR, "Invalid value %lu for %s", result, key); + return -ERANGE; + } + *u16 = (uint16_t)result; + return 0; +} + +/* Parse parameters used to create device */ +static int +parse_bbdev_la12xx_params(struct bbdev_la12xx_params *params, + const char *input_args) +{ + struct rte_kvargs *kvlist = NULL; + int ret = 0; + + if (params == NULL) + return -EINVAL; + if (input_args) { + kvlist = rte_kvargs_parse(input_args, + bbdev_la12xx_valid_params); + if (kvlist == NULL) + return -EFAULT; + + ret = rte_kvargs_process(kvlist, bbdev_la12xx_valid_params[0], + &parse_u16_arg, ¶ms->queues_num); + if (ret < 0) + goto exit; + + } + +exit: + if (kvlist) + rte_kvargs_free(kvlist); + return ret; +} + /* Create device */ static int -la12xx_bbdev_create(struct rte_vdev_device *vdev) +la12xx_bbdev_create(struct rte_vdev_device *vdev, + struct bbdev_la12xx_params *init_params __rte_unused) { struct rte_bbdev *bbdev; const char *name = rte_vdev_device_name(vdev); @@ -62,7 +121,11 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev) static int la12xx_bbdev_probe(struct rte_vdev_device *vdev) { + struct bbdev_la12xx_params init_params = { + 8 + }; const char *name; + const char *input_args; PMD_INIT_FUNC_TRACE(); @@ -73,7 +136,10 @@ la12xx_bbdev_probe(struct rte_vdev_device *vdev) if (name == NULL) return -EINVAL; - return la12xx_bbdev_create(vdev); + input_args = rte_vdev_device_args(vdev); + parse_bbdev_la12xx_params(&init_params, input_args); + + return la12xx_bbdev_create(vdev, &init_params); } /* Uninitialise device */ @@ -107,3 +173,5 @@ static struct rte_vdev_driver bbdev_la12xx_pmd_drv = { }; RTE_PMD_REGISTER_VDEV(DRIVER_NAME, bbdev_la12xx_pmd_drv); +RTE_PMD_REGISTER_PARAM_STRING(DRIVER_NAME, + LA12XX_MAX_NB_QUEUES_ARG"="); From patchwork Sun Sep 12 12:15:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98713 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 179F8A0C4B; Sun, 12 Sep 2021 14:16:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D1B64111B; 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Signed-off-by: Hemant Agrawal --- drivers/baseband/la12xx/bbdev_la12xx.c | 64 +++++++++++++++++++--- drivers/baseband/la12xx/bbdev_la12xx.h | 56 +++++++++++++++++++ drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 20 +++++++ 3 files changed, 133 insertions(+), 7 deletions(-) create mode 100644 drivers/baseband/la12xx/bbdev_la12xx.h create mode 100644 drivers/baseband/la12xx/bbdev_la12xx_ipc.h diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index 8886b35429..f26f3f2a08 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -14,6 +14,8 @@ #include #include +#include +#include #define DRIVER_NAME baseband_la12xx @@ -22,18 +24,18 @@ RTE_LOG_REGISTER(bbdev_la12xx_logtype, pmd.bb.la12xx, NOTICE); /* Initialisation params structure that can be used by LA12xx BBDEV driver */ struct bbdev_la12xx_params { uint8_t queues_num; /*< LA12xx BBDEV queues number */ + int8_t modem_id; /*< LA12xx modem instance id */ }; #define LA12XX_MAX_NB_QUEUES_ARG "max_nb_queues" +#define LA12XX_VDEV_MODEM_ID_ARG "modem" +#define LA12XX_MAX_MODEM 4 static const char * const bbdev_la12xx_valid_params[] = { LA12XX_MAX_NB_QUEUES_ARG, + LA12XX_VDEV_MODEM_ID_ARG, }; -/* private data structure */ -struct bbdev_la12xx_private { - unsigned int max_nb_queues; /**< Max number of queues */ -}; static inline int parse_u16_arg(const char *key, const char *value, void *extra_args) { @@ -52,6 +54,28 @@ parse_u16_arg(const char *key, const char *value, void *extra_args) return 0; } +/* Parse integer from integer argument */ +static int +parse_integer_arg(const char *key __rte_unused, + const char *value, void *extra_args) +{ + int i; + char *end; + + errno = 0; + + i = strtol(value, &end, 10); + if (*end != 0 || errno != 0 || i < 0 || i > LA12XX_MAX_MODEM) { + rte_bbdev_log(ERR, "Supported Port IDS are 0 to %d", + LA12XX_MAX_MODEM - 1); + return -EINVAL; + } + + *((uint32_t *)extra_args) = i; + + return 0; +} + /* Parse parameters used to create device */ static int parse_bbdev_la12xx_params(struct bbdev_la12xx_params *params, @@ -73,6 +97,16 @@ parse_bbdev_la12xx_params(struct bbdev_la12xx_params *params, if (ret < 0) goto exit; + ret = rte_kvargs_process(kvlist, + bbdev_la12xx_valid_params[1], + &parse_integer_arg, + ¶ms->modem_id); + + if (params->modem_id >= LA12XX_MAX_MODEM) { + rte_bbdev_log(ERR, "Invalid modem id, must be < %u", + LA12XX_MAX_MODEM); + goto exit; + } } exit: @@ -84,10 +118,11 @@ parse_bbdev_la12xx_params(struct bbdev_la12xx_params *params, /* Create device */ static int la12xx_bbdev_create(struct rte_vdev_device *vdev, - struct bbdev_la12xx_params *init_params __rte_unused) + struct bbdev_la12xx_params *init_params) { struct rte_bbdev *bbdev; const char *name = rte_vdev_device_name(vdev); + struct bbdev_la12xx_private *priv; PMD_INIT_FUNC_TRACE(); @@ -103,6 +138,20 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev, return -ENOMEM; } + priv = bbdev->data->dev_private; + priv->modem_id = init_params->modem_id; + /* if modem id is not configured */ + if (priv->modem_id == -1) + priv->modem_id = bbdev->data->dev_id; + + /* Reset Global variables */ + priv->num_ldpc_enc_queues = 0; + priv->num_ldpc_dec_queues = 0; + priv->num_valid_queues = 0; + priv->max_nb_queues = init_params->queues_num; + + rte_bbdev_log(INFO, "Setting Up %s: DevId=%d, ModemId=%d", + name, bbdev->data->dev_id, priv->modem_id); bbdev->dev_ops = NULL; bbdev->device = &vdev->device; bbdev->data->socket_id = 0; @@ -122,7 +171,7 @@ static int la12xx_bbdev_probe(struct rte_vdev_device *vdev) { struct bbdev_la12xx_params init_params = { - 8 + 8, -1, }; const char *name; const char *input_args; @@ -174,4 +223,5 @@ static struct rte_vdev_driver bbdev_la12xx_pmd_drv = { RTE_PMD_REGISTER_VDEV(DRIVER_NAME, bbdev_la12xx_pmd_drv); RTE_PMD_REGISTER_PARAM_STRING(DRIVER_NAME, - LA12XX_MAX_NB_QUEUES_ARG"="); + LA12XX_MAX_NB_QUEUES_ARG"=" + LA12XX_VDEV_MODEM_ID_ARG "= "); diff --git a/drivers/baseband/la12xx/bbdev_la12xx.h b/drivers/baseband/la12xx/bbdev_la12xx.h new file mode 100644 index 0000000000..5228502331 --- /dev/null +++ b/drivers/baseband/la12xx/bbdev_la12xx.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020-2021 NXP + */ + +#ifndef __BBDEV_LA12XX_H__ +#define __BBDEV_LA12XX_H__ + +#define BBDEV_IPC_ENC_OP_TYPE 1 +#define BBDEV_IPC_DEC_OP_TYPE 2 + +#define MAX_LDPC_ENC_FECA_QUEUES 4 +#define MAX_LDPC_DEC_FECA_QUEUES 4 + +#define MAX_CHANNEL_DEPTH 16 +/* private data structure */ +struct bbdev_la12xx_private { + void *ipc_priv; + uint8_t num_valid_queues; + uint8_t max_nb_queues; + uint8_t num_ldpc_enc_queues; + uint8_t num_ldpc_dec_queues; + int8_t modem_id; + struct bbdev_la12xx_q_priv *queues_priv[32]; +}; + +struct hugepage_info { + void *vaddr; + phys_addr_t paddr; + size_t len; +}; + +struct bbdev_la12xx_q_priv { + struct bbdev_la12xx_private *bbdev_priv; + uint32_t q_id; /**< Channel ID */ + uint32_t feca_blk_id; /** FECA block ID for processing */ + uint32_t feca_blk_id_be32; /**< FECA Block ID for this queue */ + uint8_t en_napi; /* 0: napi disabled, 1: napi enabled */ + uint16_t queue_size; /**< Queue depth */ + int32_t eventfd; /**< Event FD value */ + enum rte_bbdev_op_type op_type; /**< Operation type */ + uint32_t la12xx_core_id; + /* LA12xx core ID on which this will be scheduled */ + struct rte_mempool *mp; /**< Pool from where buffers would be cut */ + void *bbdev_op[MAX_CHANNEL_DEPTH]; + /**< Stores bbdev op for each index */ + void *msg_ch_vaddr[MAX_CHANNEL_DEPTH]; + /**< Stores msg channel addr for modem->host */ + uint32_t host_pi; /**< Producer_Index for HOST->MODEM */ + uint32_t host_ci; /**< Consumer Index for MODEM->HOST */ + host_ipc_params_t *host_params; /**< Host parameters */ +}; + +#define lower_32_bits(x) ((uint32_t)((uint64_t)x)) +#define upper_32_bits(x) ((uint32_t)(((uint64_t)(x) >> 16) >> 16)) + +#endif diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h new file mode 100644 index 0000000000..9aa5562981 --- /dev/null +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020-2021 NXP + */ +#ifndef __BBDEV_LA12XX_IPC_H__ +#define __BBDEV_LA12XX_IPC_H__ + +/** No. of max channel per instance */ +#define IPC_MAX_DEPTH (16) + +/* This shared memory would be on the host side which have copy of some + * of the parameters which are also part of Shared BD ring. Read access + * of these parameters from the host side would not be over PCI. + */ +typedef struct host_ipc_params { + volatile uint32_t pi; + volatile uint32_t ci; + volatile uint32_t modem_ptr[IPC_MAX_DEPTH]; +} __rte_packed host_ipc_params_t; + +#endif From patchwork Sun Sep 12 12:15:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98714 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E88D7A0C4B; Sun, 12 Sep 2021 14:16:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 443FD410E9; Sun, 12 Sep 2021 14:15:51 +0200 (CEST) Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2083.outbound.protection.outlook.com [40.107.21.83]) by mails.dpdk.org (Postfix) with ESMTP id F173D410F5 for ; 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Sun, 12 Sep 2021 12:15:46 +0000 From: Nipun Gupta To: dev@dpdk.org, gakhil@marvell.com, nicolas.chautru@intel.com Cc: david.marchand@redhat.com, hemant.agrawal@nxp.com, Nipun Gupta Date: Sun, 12 Sep 2021 17:45:06 +0530 Message-Id: <20210912121510.22699-6-nipun.gupta@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210912121510.22699-1-nipun.gupta@nxp.com> References: <20210318063421.14895-1-hemant.agrawal@nxp.com> <20210912121510.22699-1-nipun.gupta@nxp.com> X-ClientProxiedBy: SG2PR0601CA0003.apcprd06.prod.outlook.com (2603:1096:3::13) To DB9PR04MB8429.eurprd04.prod.outlook.com (2603:10a6:10:24e::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv03274.swis.in-blr01.nxp.com (14.142.151.118) by SG2PR0601CA0003.apcprd06.prod.outlook.com (2603:1096:3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Sun, 12 Sep 2021 12:15:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c79998b2-0052-4f46-8290-08d975e70cd0 X-MS-TrafficTypeDiagnostic: DB7PR04MB4778: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:431; 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Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- MAINTAINERS | 1 + doc/guides/bbdevs/index.rst | 1 + doc/guides/bbdevs/la12xx.rst | 81 +++ doc/guides/rel_notes/release_21_11.rst | 5 + drivers/baseband/la12xx/bbdev_la12xx.c | 553 ++++++++++++++++++++- drivers/baseband/la12xx/bbdev_la12xx.h | 11 +- drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 189 ++++++- 7 files changed, 831 insertions(+), 10 deletions(-) create mode 100644 doc/guides/bbdevs/la12xx.rst diff --git a/MAINTAINERS b/MAINTAINERS index a63e672c9e..2c243c10fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1295,6 +1295,7 @@ NXP LA12xx driver M: Hemant Agrawal M: Nipun Gupta F: drivers/baseband/la12xx/ +F: doc/guides/bbdevs/la12xx.rst Rawdev Drivers diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst index 4445cbd1b0..cedd706fa6 100644 --- a/doc/guides/bbdevs/index.rst +++ b/doc/guides/bbdevs/index.rst @@ -14,3 +14,4 @@ Baseband Device Drivers fpga_lte_fec fpga_5gnr_fec acc100 + la12xx diff --git a/doc/guides/bbdevs/la12xx.rst b/doc/guides/bbdevs/la12xx.rst new file mode 100644 index 0000000000..3c9ac5c047 --- /dev/null +++ b/doc/guides/bbdevs/la12xx.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright 2021 NXP + +NXP LA12xx Poll Mode Driver +======================================= + +The BBDEV LA12xx poll mode driver (PMD) supports an implementation for +offloading High Phy processing functions like LDPC Encode / Decode 5GNR wireless +acceleration function, using PCI based LA12xx Software defined radio. + +More information can be found at `NXP Official Website +`_. + +Features +-------- + +LA12xx PMD supports the following features: + +- Maximum of 8 UL queues +- Maximum of 8 DL queues +- PCIe Gen-3 x8 Interface +- MSI-X + +Installation +------------ + +Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. + +DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual. + +Initialization +-------------- + +The device can be listed on the host console with: + + +Use the following lspci command to get the multiple LA12xx processor ids. The +device ID of the LA12xx baseband processor is "1c30". + +.. code-block:: console + + sudo lspci -nn + +... +0001:01:00.0 Power PC [0b20]: Freescale Semiconductor Inc Device [1957:1c30] ( +rev 10) +... +0002:01:00.0 Power PC [0b20]: Freescale Semiconductor Inc Device [1957:1c30] ( +rev 10) + + +Prerequisites +------------- + +Currently supported by DPDK: + +- NXP LA1224 BSP **1.0+**. +- NXP LA1224 PCIe Modem card connected to ARM host. + +- Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup the basic DPDK environment. + +* Use dev arg option ``modem=0`` to identify the modem instance for a given + device. This is required only if more than 1 modem cards are attached to host. + this is optional and the default value is 0. + e.g. ``--vdev=baseband_la12xx,modem=0`` + +* Use dev arg option ``max_nb_queues=x`` to specify the maximum number of queues + to be used for communication with offload device i.e. modem. default is 16. + e.g. ``--vdev=baseband_la12xx,max_nb_queues=4`` + +Enabling logs +------------- + +For enabling logs, use the following EAL parameter: + +.. code-block:: console + + ./your_bbdev_application --log-level=la12xx: + +Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be +enabled which are lower than logging ``level``. diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 675b573834..a0e0ebbeb8 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -62,6 +62,11 @@ New Features * Added bus-level parsing of the devargs syntax. * Kept compatibility with the legacy syntax as parsing fallback. +* **Added NXP LA12xx baseband PMD.** + + * Added a new baseband PMD driver for NXP LA12xx Software defined radio. + * See the :doc:`../bbdevs/la12xx` for more details. + Removed Items ------------- diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index f26f3f2a08..57e957a93a 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -3,6 +3,11 @@ */ #include +#include +#include +#include +#include +#include #include #include @@ -31,11 +36,550 @@ struct bbdev_la12xx_params { #define LA12XX_VDEV_MODEM_ID_ARG "modem" #define LA12XX_MAX_MODEM 4 +#define LA12XX_MAX_CORES 4 +#define LA12XX_LDPC_ENC_CORE 0 +#define LA12XX_LDPC_DEC_CORE 1 + +#define LA12XX_MAX_LDPC_ENC_QUEUES 4 +#define LA12XX_MAX_LDPC_DEC_QUEUES 4 + static const char * const bbdev_la12xx_valid_params[] = { LA12XX_MAX_NB_QUEUES_ARG, LA12XX_VDEV_MODEM_ID_ARG, }; +static const struct rte_bbdev_op_cap bbdev_capabilities[] = { + { + .type = RTE_BBDEV_OP_LDPC_ENC, + .cap.ldpc_enc = { + .capability_flags = + RTE_BBDEV_LDPC_CRC_24A_ATTACH | + RTE_BBDEV_LDPC_CRC_24B_ATTACH, + .num_buffers_src = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_dst = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + } + }, + { + .type = RTE_BBDEV_OP_LDPC_DEC, + .cap.ldpc_dec = { + .capability_flags = + RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | + RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP, + .num_buffers_src = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .num_buffers_hard_out = + RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, + .llr_size = 8, + .llr_decimals = 1, + } + }, + RTE_BBDEV_END_OF_CAPABILITIES_LIST() +}; + +static struct rte_bbdev_queue_conf default_queue_conf = { + .queue_size = MAX_CHANNEL_DEPTH, +}; + +/* Get device info */ +static void +la12xx_info_get(struct rte_bbdev *dev __rte_unused, + struct rte_bbdev_driver_info *dev_info) +{ + PMD_INIT_FUNC_TRACE(); + + dev_info->driver_name = RTE_STR(DRIVER_NAME); + dev_info->max_num_queues = LA12XX_MAX_QUEUES; + dev_info->queue_size_lim = MAX_CHANNEL_DEPTH; + dev_info->hardware_accelerated = true; + dev_info->max_dl_queue_priority = 0; + dev_info->max_ul_queue_priority = 0; + dev_info->default_queue_conf = default_queue_conf; + dev_info->capabilities = bbdev_capabilities; + dev_info->cpu_flag_reqs = NULL; + dev_info->min_alignment = 64; + + rte_bbdev_log_debug("got device info from %u", dev->data->dev_id); +} + +/* Release queue */ +static int +la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id) +{ + RTE_SET_USED(dev); + RTE_SET_USED(q_id); + + PMD_INIT_FUNC_TRACE(); + + /* TODO: Implement */ + + return 0; +} + +#define HUGEPG_OFFSET(A) \ + ((uint64_t) ((unsigned long) (A) \ + - ((uint64_t)ipc_priv->hugepg_start.host_vaddr))) + +static int ipc_queue_configure(uint32_t channel_id, + ipc_t instance, struct bbdev_la12xx_q_priv *q_priv) +{ + ipc_userspace_t *ipc_priv = (ipc_userspace_t *)instance; + ipc_instance_t *ipc_instance = ipc_priv->instance; + ipc_ch_t *ch; + void *vaddr; + uint32_t i = 0; + uint32_t msg_size = sizeof(struct bbdev_ipc_enqueue_op); + + PMD_INIT_FUNC_TRACE(); + + rte_bbdev_log_debug("%x %p", ipc_instance->initialized, + ipc_priv->instance); + ch = &(ipc_instance->ch_list[channel_id]); + + rte_bbdev_log_debug("channel: %u, depth: %u, msg size: %u", + channel_id, q_priv->queue_size, msg_size); + + /* Start init of channel */ + ch->md.ring_size = rte_cpu_to_be_32(q_priv->queue_size); + ch->md.pi = 0; + ch->md.ci = 0; + ch->md.msg_size = msg_size; + for (i = 0; i < q_priv->queue_size; i++) { + vaddr = rte_malloc(NULL, msg_size, RTE_CACHE_LINE_SIZE); + if (!vaddr) + return IPC_HOST_BUF_ALLOC_FAIL; + /* Only offset now */ + ch->bd_h[i].modem_ptr = + rte_cpu_to_be_32(HUGEPG_OFFSET(vaddr)); + ch->bd_h[i].host_virt_l = lower_32_bits(vaddr); + ch->bd_h[i].host_virt_h = upper_32_bits(vaddr); + q_priv->msg_ch_vaddr[i] = vaddr; + /* Not sure use of this len may be for CRC*/ + ch->bd_h[i].len = 0; + } + ch->host_ipc_params = + rte_cpu_to_be_32(HUGEPG_OFFSET(q_priv->host_params)); + + rte_bbdev_log_debug("Channel configured"); + return IPC_SUCCESS; +} + +static int +la12xx_e200_queue_setup(struct rte_bbdev *dev, + struct bbdev_la12xx_q_priv *q_priv) +{ + struct bbdev_la12xx_private *priv = dev->data->dev_private; + ipc_userspace_t *ipc_priv = priv->ipc_priv; + struct gul_hif *mhif; + ipc_metadata_t *ipc_md; + ipc_ch_t *ch; + int instance_id = 0, i; + int ret; + + PMD_INIT_FUNC_TRACE(); + + switch (q_priv->op_type) { + case RTE_BBDEV_OP_LDPC_ENC: + q_priv->la12xx_core_id = LA12XX_LDPC_ENC_CORE; + break; + case RTE_BBDEV_OP_LDPC_DEC: + q_priv->la12xx_core_id = LA12XX_LDPC_DEC_CORE; + break; + default: + rte_bbdev_log(ERR, "Unsupported op type\n"); + return -1; + } + + mhif = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr; + /* offset is from start of PEB */ + ipc_md = (ipc_metadata_t *)((uint64_t)ipc_priv->peb_start.host_vaddr + + mhif->ipc_regs.ipc_mdata_offset); + ch = &ipc_md->instance_list[instance_id].ch_list[q_priv->q_id]; + + if (q_priv->q_id < priv->num_valid_queues) { + ipc_br_md_t *md = &(ch->md); + + q_priv->feca_blk_id = rte_cpu_to_be_32(ch->feca_blk_id); + q_priv->feca_blk_id_be32 = ch->feca_blk_id; + q_priv->host_pi = rte_be_to_cpu_32(md->pi); + q_priv->host_ci = rte_be_to_cpu_32(md->ci); + q_priv->host_params = (host_ipc_params_t *) + (rte_be_to_cpu_32(ch->host_ipc_params) + + ((uint64_t)ipc_priv->hugepg_start.host_vaddr)); + + for (i = 0; i < q_priv->queue_size; i++) { + uint32_t h, l; + + h = ch->bd_h[i].host_virt_h; + l = ch->bd_h[i].host_virt_l; + q_priv->msg_ch_vaddr[i] = (void *)join_32_bits(h, l); + } + + rte_bbdev_log(WARNING, + "Queue [%d] already configured, not configuring again", + q_priv->q_id); + return 0; + } + + rte_bbdev_log_debug("setting up queue %d", q_priv->q_id); + + /* Call ipc_configure_channel */ + ret = ipc_queue_configure(q_priv->q_id, ipc_priv, q_priv); + if (ret) { + rte_bbdev_log(ERR, "Unable to setup queue (%d) (err=%d)", + q_priv->q_id, ret); + return ret; + } + + /* Set queue properties for LA12xx device */ + switch (q_priv->op_type) { + case RTE_BBDEV_OP_LDPC_ENC: + if (priv->num_ldpc_enc_queues >= LA12XX_MAX_LDPC_ENC_QUEUES) { + rte_bbdev_log(ERR, + "num_ldpc_enc_queues reached max value"); + return -1; + } + ch->la12xx_core_id = + rte_cpu_to_be_32(LA12XX_LDPC_ENC_CORE); + ch->feca_blk_id = rte_cpu_to_be_32(priv->num_ldpc_enc_queues++); + break; + case RTE_BBDEV_OP_LDPC_DEC: + if (priv->num_ldpc_dec_queues >= LA12XX_MAX_LDPC_DEC_QUEUES) { + rte_bbdev_log(ERR, + "num_ldpc_dec_queues reached max value"); + return -1; + } + ch->la12xx_core_id = + rte_cpu_to_be_32(LA12XX_LDPC_DEC_CORE); + ch->feca_blk_id = rte_cpu_to_be_32(priv->num_ldpc_dec_queues++); + break; + default: + rte_bbdev_log(ERR, "Not supported op type\n"); + return -1; + } + ch->op_type = rte_cpu_to_be_32(q_priv->op_type); + ch->depth = rte_cpu_to_be_32(q_priv->queue_size); + + /* Store queue config here */ + q_priv->feca_blk_id = rte_cpu_to_be_32(ch->feca_blk_id); + q_priv->feca_blk_id_be32 = ch->feca_blk_id; + + return 0; +} + +/* Setup a queue */ +static int +la12xx_queue_setup(struct rte_bbdev *dev, uint16_t q_id, + const struct rte_bbdev_queue_conf *queue_conf) +{ + struct bbdev_la12xx_private *priv = dev->data->dev_private; + struct rte_bbdev_queue_data *q_data; + struct bbdev_la12xx_q_priv *q_priv; + int ret; + + PMD_INIT_FUNC_TRACE(); + + /* Move to setup_queues callback */ + q_data = &dev->data->queues[q_id]; + q_data->queue_private = rte_zmalloc(NULL, + sizeof(struct bbdev_la12xx_q_priv), 0); + if (!q_data->queue_private) { + rte_bbdev_log(ERR, "Memory allocation failed for qpriv"); + return -ENOMEM; + } + q_priv = q_data->queue_private; + q_priv->q_id = q_id; + q_priv->bbdev_priv = dev->data->dev_private; + q_priv->queue_size = queue_conf->queue_size; + q_priv->op_type = queue_conf->op_type; + + ret = la12xx_e200_queue_setup(dev, q_priv); + if (ret) { + rte_bbdev_log(ERR, "e200_queue_setup failed for qid: %d", + q_id); + return ret; + } + + /* Store queue config here */ + priv->num_valid_queues++; + + return 0; +} + +static int +la12xx_start(struct rte_bbdev *dev) +{ + struct bbdev_la12xx_private *priv = dev->data->dev_private; + ipc_userspace_t *ipc_priv = priv->ipc_priv; + int ready = 0; + struct gul_hif *hif_start; + + PMD_INIT_FUNC_TRACE(); + + hif_start = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr; + + /* Set Host Read bit */ + SET_HIF_HOST_RDY(hif_start, HIF_HOST_READY_IPC_APP); + + /* Now wait for modem ready bit */ + while (!ready) + ready = CHK_HIF_MOD_RDY(hif_start, HIF_MOD_READY_IPC_APP); + + return 0; +} + +static const struct rte_bbdev_ops pmd_ops = { + .info_get = la12xx_info_get, + .queue_setup = la12xx_queue_setup, + .queue_release = la12xx_queue_release, + .start = la12xx_start +}; +static struct hugepage_info * +get_hugepage_info(void) +{ + struct hugepage_info *hp_info; + struct rte_memseg *mseg; + + PMD_INIT_FUNC_TRACE(); + + /* TODO - find a better way */ + hp_info = rte_malloc(NULL, sizeof(struct hugepage_info), 0); + if (!hp_info) { + rte_bbdev_log(ERR, "Unable to allocate on local heap"); + return NULL; + } + + mseg = rte_mem_virt2memseg(hp_info, NULL); + hp_info->vaddr = mseg->addr; + hp_info->paddr = rte_mem_virt2phy(mseg->addr); + hp_info->len = mseg->len; + + return hp_info; +} + +static int open_ipc_dev(int modem_id) +{ + char dev_initials[16], dev_path[PATH_MAX]; + struct dirent *entry; + int dev_ipc = 0; + DIR *dir; + + dir = opendir("/dev/"); + if (!dir) { + rte_bbdev_log(ERR, "Unable to open /dev/"); + return -1; + } + + sprintf(dev_initials, "gulipcgul%d", modem_id); + + while ((entry = readdir(dir)) != NULL) { + if (!strncmp(dev_initials, entry->d_name, + sizeof(dev_initials) - 1)) + break; + } + + if (!entry) { + rte_bbdev_log(ERR, "Error: No gulipcgul%d device", modem_id); + return -1; + } + + sprintf(dev_path, "/dev/%s", entry->d_name); + dev_ipc = open(dev_path, O_RDWR); + if (dev_ipc < 0) { + rte_bbdev_log(ERR, "Error: Cannot open %s", dev_path); + return -errno; + } + + return dev_ipc; +} + +static int +setup_la12xx_dev(struct rte_bbdev *dev) +{ + struct bbdev_la12xx_private *priv = dev->data->dev_private; + ipc_userspace_t *ipc_priv = priv->ipc_priv; + struct hugepage_info *hp = NULL; + ipc_channel_us_t *ipc_priv_ch = NULL; + int dev_ipc = 0, dev_mem = 0, i; + ipc_metadata_t *ipc_md; + struct gul_hif *mhif; + uint32_t phy_align = 0; + int ret; + + PMD_INIT_FUNC_TRACE(); + + if (!ipc_priv) { + /* TODO - get a better way */ + /* Get the hugepage info against it */ + hp = get_hugepage_info(); + if (!hp) { + rte_bbdev_log(ERR, "Unable to get hugepage info"); + ret = -ENOMEM; + goto err; + } + + rte_bbdev_log_debug("%lx %p %lx", + hp->paddr, hp->vaddr, hp->len); + + ipc_priv = rte_zmalloc(0, sizeof(ipc_userspace_t), 0); + if (ipc_priv == NULL) { + rte_bbdev_log(ERR, + "Unable to allocate memory for ipc priv"); + ret = -ENOMEM; + goto err; + } + + for (i = 0; i < IPC_MAX_CHANNEL_COUNT; i++) { + ipc_priv_ch = rte_zmalloc(0, + sizeof(ipc_channel_us_t), 0); + if (ipc_priv_ch == NULL) { + rte_bbdev_log(ERR, + "Unable to allocate memory for channels"); + ret = -ENOMEM; + } + ipc_priv->channels[i] = ipc_priv_ch; + } + + dev_mem = open("/dev/mem", O_RDWR); + if (dev_mem < 0) { + rte_bbdev_log(ERR, "Error: Cannot open /dev/mem"); + ret = -errno; + goto err; + } + + ipc_priv->instance_id = 0; + ipc_priv->dev_mem = dev_mem; + + rte_bbdev_log_debug("hugepg input %lx %p %lx", + hp->paddr, hp->vaddr, hp->len); + + ipc_priv->sys_map.hugepg_start.host_phys = hp->paddr; + ipc_priv->sys_map.hugepg_start.size = hp->len; + + ipc_priv->hugepg_start.host_phys = hp->paddr; + ipc_priv->hugepg_start.host_vaddr = hp->vaddr; + ipc_priv->hugepg_start.size = hp->len; + + rte_free(hp); + } + + dev_ipc = open_ipc_dev(priv->modem_id); + if (dev_ipc < 0) { + rte_bbdev_log(ERR, "Error: open_ipc_dev failed"); + goto err; + } + ipc_priv->dev_ipc = dev_ipc; + + ret = ioctl(ipc_priv->dev_ipc, IOCTL_GUL_IPC_GET_SYS_MAP, + &ipc_priv->sys_map); + if (ret) { + rte_bbdev_log(ERR, + "IOCTL_GUL_IPC_GET_SYS_MAP ioctl failed"); + goto err; + } + + phy_align = (ipc_priv->sys_map.mhif_start.host_phys % 0x1000); + ipc_priv->mhif_start.host_vaddr = + mmap(0, ipc_priv->sys_map.mhif_start.size + phy_align, + (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem, + (ipc_priv->sys_map.mhif_start.host_phys - phy_align)); + if (ipc_priv->mhif_start.host_vaddr == MAP_FAILED) { + rte_bbdev_log(ERR, "MAP failed:"); + ret = -errno; + goto err; + } + + ipc_priv->mhif_start.host_vaddr = (void *) ((uint64_t) + (ipc_priv->mhif_start.host_vaddr) + phy_align); + + phy_align = (ipc_priv->sys_map.peb_start.host_phys % 0x1000); + ipc_priv->peb_start.host_vaddr = + mmap(0, ipc_priv->sys_map.peb_start.size + phy_align, + (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem, + (ipc_priv->sys_map.peb_start.host_phys - phy_align)); + if (ipc_priv->peb_start.host_vaddr == MAP_FAILED) { + rte_bbdev_log(ERR, "MAP failed:"); + ret = -errno; + goto err; + } + + ipc_priv->peb_start.host_vaddr = (void *)((uint64_t) + (ipc_priv->peb_start.host_vaddr) + phy_align); + + phy_align = (ipc_priv->sys_map.modem_ccsrbar.host_phys % 0x1000); + ipc_priv->modem_ccsrbar.host_vaddr = + mmap(0, ipc_priv->sys_map.modem_ccsrbar.size + phy_align, + (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem, + (ipc_priv->sys_map.modem_ccsrbar.host_phys - phy_align)); + if (ipc_priv->modem_ccsrbar.host_vaddr == MAP_FAILED) { + rte_bbdev_log(ERR, "MAP failed:"); + ret = -errno; + goto err; + } + + ipc_priv->modem_ccsrbar.host_vaddr = (void *)((uint64_t) + (ipc_priv->modem_ccsrbar.host_vaddr) + phy_align); + + ipc_priv->hugepg_start.modem_phys = + ipc_priv->sys_map.hugepg_start.modem_phys; + + ipc_priv->mhif_start.host_phys = + ipc_priv->sys_map.mhif_start.host_phys; + ipc_priv->mhif_start.size = ipc_priv->sys_map.mhif_start.size; + ipc_priv->peb_start.host_phys = ipc_priv->sys_map.peb_start.host_phys; + ipc_priv->peb_start.size = ipc_priv->sys_map.peb_start.size; + + rte_bbdev_log(INFO, "peb %lx %p %x", + ipc_priv->peb_start.host_phys, + ipc_priv->peb_start.host_vaddr, + ipc_priv->peb_start.size); + rte_bbdev_log(INFO, "hugepg %lx %p %x", + ipc_priv->hugepg_start.host_phys, + ipc_priv->hugepg_start.host_vaddr, + ipc_priv->hugepg_start.size); + rte_bbdev_log(INFO, "mhif %lx %p %x", + ipc_priv->mhif_start.host_phys, + ipc_priv->mhif_start.host_vaddr, + ipc_priv->mhif_start.size); + mhif = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr; + + /* offset is from start of PEB */ + ipc_md = (ipc_metadata_t *)((uint64_t)ipc_priv->peb_start.host_vaddr + + mhif->ipc_regs.ipc_mdata_offset); + + if (sizeof(ipc_metadata_t) != mhif->ipc_regs.ipc_mdata_size) { + rte_bbdev_log(ERR, + "ipc_metadata_t =%lx, mhif->ipc_regs.ipc_mdata_size=%x", + sizeof(ipc_metadata_t), mhif->ipc_regs.ipc_mdata_size); + rte_bbdev_log(ERR, "--> mhif->ipc_regs.ipc_mdata_offset= %x", + mhif->ipc_regs.ipc_mdata_offset); + rte_bbdev_log(ERR, "gul_hif size=%lx", sizeof(struct gul_hif)); + return IPC_MD_SZ_MISS_MATCH; + } + + ipc_priv->instance = (ipc_instance_t *) + (&ipc_md->instance_list[ipc_priv->instance_id]); + + rte_bbdev_log_debug("finish host init"); + + priv->ipc_priv = ipc_priv; + + return 0; + +err: + rte_free(hp); + rte_free(ipc_priv); + rte_free(ipc_priv_ch); + if (dev_mem) + close(dev_mem); + if (dev_ipc) + close(dev_ipc); + + return ret; +} + static inline int parse_u16_arg(const char *key, const char *value, void *extra_args) { @@ -123,6 +667,7 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev, struct rte_bbdev *bbdev; const char *name = rte_vdev_device_name(vdev); struct bbdev_la12xx_private *priv; + int ret; PMD_INIT_FUNC_TRACE(); @@ -152,7 +697,13 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev, rte_bbdev_log(INFO, "Setting Up %s: DevId=%d, ModemId=%d", name, bbdev->data->dev_id, priv->modem_id); - bbdev->dev_ops = NULL; + ret = setup_la12xx_dev(bbdev); + if (ret) { + rte_bbdev_log(ERR, "IPC Setup failed for %s", name); + rte_free(bbdev->data->dev_private); + return ret; + } + bbdev->dev_ops = &pmd_ops; bbdev->device = &vdev->device; bbdev->data->socket_id = 0; bbdev->intr_handle = NULL; diff --git a/drivers/baseband/la12xx/bbdev_la12xx.h b/drivers/baseband/la12xx/bbdev_la12xx.h index 5228502331..49c37fe2fe 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.h +++ b/drivers/baseband/la12xx/bbdev_la12xx.h @@ -5,16 +5,10 @@ #ifndef __BBDEV_LA12XX_H__ #define __BBDEV_LA12XX_H__ -#define BBDEV_IPC_ENC_OP_TYPE 1 -#define BBDEV_IPC_DEC_OP_TYPE 2 - -#define MAX_LDPC_ENC_FECA_QUEUES 4 -#define MAX_LDPC_DEC_FECA_QUEUES 4 - #define MAX_CHANNEL_DEPTH 16 /* private data structure */ struct bbdev_la12xx_private { - void *ipc_priv; + ipc_userspace_t *ipc_priv; uint8_t num_valid_queues; uint8_t max_nb_queues; uint8_t num_ldpc_enc_queues; @@ -52,5 +46,6 @@ struct bbdev_la12xx_q_priv { #define lower_32_bits(x) ((uint32_t)((uint64_t)x)) #define upper_32_bits(x) ((uint32_t)(((uint64_t)(x) >> 16) >> 16)) - +#define join_32_bits(upper, lower) \ + ((size_t)(((uint64_t)(upper) << 32) | (uint32_t)(lower))) #endif diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h index 9aa5562981..5f613fb087 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h @@ -4,9 +4,182 @@ #ifndef __BBDEV_LA12XX_IPC_H__ #define __BBDEV_LA12XX_IPC_H__ +#define LA12XX_MAX_QUEUES 20 +#define HOST_RX_QUEUEID_OFFSET LA12XX_MAX_QUEUES + +/** No. of max channel per instance */ +#define IPC_MAX_CHANNEL_COUNT (64) + /** No. of max channel per instance */ #define IPC_MAX_DEPTH (16) +/** No. of max IPC instance per modem */ +#define IPC_MAX_INSTANCE_COUNT (1) + +/** Error codes */ +#define IPC_SUCCESS (0) /** IPC operation success */ +#define IPC_INPUT_INVALID (-1) /** Invalid input to API */ +#define IPC_CH_INVALID (-2) /** Channel no is invalid */ +#define IPC_INSTANCE_INVALID (-3) /** Instance no is invalid */ +#define IPC_MEM_INVALID (-4) /** Insufficient memory */ +#define IPC_CH_FULL (-5) /** Channel is full */ +#define IPC_CH_EMPTY (-6) /** Channel is empty */ +#define IPC_BL_EMPTY (-7) /** Free buffer list is empty */ +#define IPC_BL_FULL (-8) /** Free buffer list is full */ +#define IPC_HOST_BUF_ALLOC_FAIL (-9) /** DPDK malloc fail */ +#define IPC_MD_SZ_MISS_MATCH (-10) /** META DATA size in mhif miss matched*/ +#define IPC_MALLOC_FAIL (-11) /** system malloc fail */ +#define IPC_IOCTL_FAIL (-12) /** IOCTL call failed */ +#define IPC_MMAP_FAIL (-14) /** MMAP fail */ +#define IPC_OPEN_FAIL (-15) /** OPEN fail */ +#define IPC_EVENTFD_FAIL (-16) /** eventfd initialization failed */ +#define IPC_NOT_IMPLEMENTED (-17) /** IPC feature is not implemented yet*/ + +#define SET_HIF_HOST_RDY(hif, RDY_MASK) (hif->host_ready |= RDY_MASK) +#define CHK_HIF_MOD_RDY(hif, RDY_MASK) (hif->mod_ready & RDY_MASK) + +/* Host Ready bits */ +#define HIF_HOST_READY_HOST_REGIONS (1 << 0) +#define HIF_HOST_READY_IPC_LIB (1 << 12) +#define HIF_HOST_READY_IPC_APP (1 << 13) +#define HIF_HOST_READY_FECA (1 << 14) + +/* Modem Ready bits */ +#define HIF_MOD_READY_IPC_LIB (1 << 5) +#define HIF_MOD_READY_IPC_APP (1 << 6) +#define HIF_MOD_READY_FECA (1 << 7) + +typedef void *ipc_t; + +struct ipc_msg { + int chid; + void *addr; + uint32_t len; + uint8_t flags; +}; + +typedef struct { + uint64_t host_phys; + uint32_t modem_phys; + void *host_vaddr; + uint32_t size; +} mem_range_t; + +#define GUL_IPC_MAGIC 'R' + +#define IOCTL_GUL_IPC_GET_SYS_MAP _IOW(GUL_IPC_MAGIC, 1, struct ipc_msg *) +#define IOCTL_GUL_IPC_CHANNEL_REGISTER _IOWR(GUL_IPC_MAGIC, 4, struct ipc_msg *) +#define IOCTL_GUL_IPC_CHANNEL_DEREGISTER \ + _IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *) +#define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *) + +/** buffer ring common metadata */ +typedef struct ipc_bd_ring_md { + volatile uint32_t pi; /**< Producer index and flag (MSB) + * which flip for each Ring wrapping + */ + volatile uint32_t ci; /**< Consumer index and flag (MSB) + * which flip for each Ring wrapping + */ + uint32_t ring_size; /**< depth (Used to roll-over pi/ci) */ + uint32_t msg_size; /**< Size of the each buffer */ +} __rte_packed ipc_br_md_t; + +/** IPC buffer descriptor */ +typedef struct ipc_buffer_desc { + union { + uint64_t host_virt; /**< msg's host virtual address */ + struct { + uint32_t host_virt_l; + uint32_t host_virt_h; + }; + }; + uint32_t modem_ptr; /**< msg's modem physical address */ + uint32_t len; /**< msg len */ +} __rte_packed ipc_bd_t; + +typedef struct ipc_channel { + uint32_t ch_id; /**< Channel id */ + ipc_br_md_t md; /**< Metadata for BD ring */ + ipc_bd_t bd_h[IPC_MAX_DEPTH]; /**< Buffer Descriptor on Host */ + ipc_bd_t bd_m[IPC_MAX_DEPTH]; /**< Buffer Descriptor on Modem */ + uint32_t op_type; /**< Type of the BBDEV operation + * supported on this channel + */ + uint32_t depth; /**< Channel depth */ + uint32_t feca_blk_id; /**< FECA Transport Block ID for processing */ + uint32_t la12xx_core_id;/**< LA12xx core ID on which this will be + * scheduled + */ + uint32_t feca_input_circ_size; /**< FECA transport block input + * circular buffer size + */ + uint32_t host_ipc_params; /**< Address for host IPC parameters */ +} __rte_packed ipc_ch_t; + +typedef struct ipc_instance { + uint32_t instance_id; /**< instance id, use to init this + * instance by ipc_init API + */ + uint32_t initialized; /**< Set in ipc_init */ + ipc_ch_t ch_list[IPC_MAX_CHANNEL_COUNT]; + /**< Channel descriptors in this instance */ +} __rte_packed ipc_instance_t; + +typedef struct ipc_metadata { + uint32_t ipc_host_signature; /**< IPC host signature, Set by host/L2 */ + uint32_t ipc_geul_signature; /**< IPC geul signature, Set by modem */ + ipc_instance_t instance_list[IPC_MAX_INSTANCE_COUNT]; +} __rte_packed ipc_metadata_t; + +typedef struct ipc_channel_us_priv { + int32_t eventfd; + uint32_t channel_id; + /* In flight packets status for buffer list. */ + uint8_t bufs_inflight[IPC_MAX_DEPTH]; +} ipc_channel_us_t; + +typedef struct { + uint64_t host_phys; + uint32_t modem_phys; + uint32_t size; +} mem_strt_addr_t; + +typedef struct { + mem_strt_addr_t modem_ccsrbar; + mem_strt_addr_t peb_start; /* PEB meta data */ + mem_strt_addr_t mhif_start; /* MHIF meta daat */ + mem_strt_addr_t hugepg_start; /* Modem to access hugepage */ +} sys_map_t; + +typedef struct ipc_priv_t { + int instance_id; + int dev_ipc; + int dev_mem; + sys_map_t sys_map; + mem_range_t modem_ccsrbar; + mem_range_t peb_start; + mem_range_t mhif_start; + mem_range_t hugepg_start; + ipc_channel_us_t *channels[IPC_MAX_CHANNEL_COUNT]; + ipc_instance_t *instance; + ipc_instance_t *instance_bk; +} ipc_userspace_t; + +/** Structure specifying enqueue operation (enqueue at LA1224) */ +struct bbdev_ipc_enqueue_op { + /** Status of operation that was performed */ + int32_t status; + /** CRC Status of SD operation that was performed */ + int32_t crc_stat_addr; + /** HARQ Output buffer memory length for Shared Decode. + * Filled by LA12xx. + */ + uint32_t out_len; + /** Reserved (for 8 byte alignment) */ + uint32_t rsvd; +}; + /* This shared memory would be on the host side which have copy of some * of the parameters which are also part of Shared BD ring. Read access * of these parameters from the host side would not be over PCI. @@ -14,7 +187,21 @@ typedef struct host_ipc_params { volatile uint32_t pi; volatile uint32_t ci; - volatile uint32_t modem_ptr[IPC_MAX_DEPTH]; + volatile uint32_t bd_m_modem_ptr[IPC_MAX_DEPTH]; } __rte_packed host_ipc_params_t; +struct hif_ipc_regs { + uint32_t ipc_mdata_offset; + uint32_t ipc_mdata_size; +} __rte_packed; + +struct gul_hif { + uint32_t ver; + uint32_t hif_ver; + uint32_t status; + volatile uint32_t host_ready; + volatile uint32_t mod_ready; + struct hif_ipc_regs ipc_regs; +} __rte_packed; + #endif From patchwork Sun Sep 12 12:15:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98715 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4FB51A0C4B; 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Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- doc/guides/bbdevs/features/la12xx.ini | 14 + doc/guides/bbdevs/la12xx.rst | 46 +++ drivers/baseband/la12xx/bbdev_la12xx.c | 334 ++++++++++++++++++++- drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 37 +++ 4 files changed, 425 insertions(+), 6 deletions(-) create mode 100644 doc/guides/bbdevs/features/la12xx.ini diff --git a/doc/guides/bbdevs/features/la12xx.ini b/doc/guides/bbdevs/features/la12xx.ini new file mode 100644 index 0000000000..412af99bad --- /dev/null +++ b/doc/guides/bbdevs/features/la12xx.ini @@ -0,0 +1,14 @@ +; +; Supported features of the 'la12xx' bbdev driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Turbo Decoder (4G) = N +Turbo Encoder (4G) = N +LDPC Decoder (5G) = Y +LDPC Encoder (5G) = Y +LLR/HARQ Compression = N +HW Accelerated = Y +BBDEV API = Y +Big Endian Processing = Y diff --git a/doc/guides/bbdevs/la12xx.rst b/doc/guides/bbdevs/la12xx.rst index 3c9ac5c047..c39be0e51f 100644 --- a/doc/guides/bbdevs/la12xx.rst +++ b/doc/guides/bbdevs/la12xx.rst @@ -16,6 +16,8 @@ Features LA12xx PMD supports the following features: +- LDPC Encode in the DL +- LDPC Decode in the UL - Maximum of 8 UL queues - Maximum of 8 DL queues - PCIe Gen-3 x8 Interface @@ -79,3 +81,47 @@ For enabling logs, use the following EAL parameter: Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be enabled which are lower than logging ``level``. + +Test Application +---------------- + +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing +the functionality of LA12xx for FEC encode and decode, depending on the device +capabilities. The test application is located under app->test-bbdev folder and has the +following options: + +.. code-block:: console + + "-p", "--testapp-path": specifies path to the bbdev test app. + "-e", "--eal-params" : EAL arguments which are passed to the test app. + "-t", "--timeout" : Timeout in seconds (default=300). + "-c", "--test-cases" : Defines test cases to run. Run all if not specified. + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data). + "-n", "--num-ops" : Number of operations to process on device (default=32). + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32). + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests. + "-s", "--iter_max" : Number of iterations for LDPC decoder. + "-l", "--num-lcores" : Number of lcores to run (default=16). + "-i", "--init-device" : Initialise PF device with default values. + + +To execute the test application tool using simple decode or encode data, +type one of the following: + +.. code-block:: console + + ./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_dec_default.data + ./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_enc_default.data + +The test application ``test-bbdev.py``, supports the ability to configure the PF device with +a default set of values, if the "-i" or "- -init-device" option is included. The default values +are defined in test_bbdev_perf.c. + + +Test Vectors +~~~~~~~~~~~~ + +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides +a range of additional tests under the test_vectors folder, which may be useful. The results +of these tests will depend on the LA12xx FEC capabilities which may cause some +testcases to be skipped, but no failure should be reported. diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index 57e957a93a..1f64ee9b1e 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -54,7 +54,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = { .cap.ldpc_enc = { .capability_flags = RTE_BBDEV_LDPC_CRC_24A_ATTACH | - RTE_BBDEV_LDPC_CRC_24B_ATTACH, + RTE_BBDEV_LDPC_CRC_24B_ATTACH | + RTE_BBDEV_LDPC_ENC_BIG_ENDIAN, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_dst = @@ -67,7 +68,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = { .capability_flags = RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | - RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP, + RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP | + RTE_BBDEV_LDPC_DEC_BIG_ENDIAN, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_hard_out = @@ -122,6 +124,10 @@ la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id) ((uint64_t) ((unsigned long) (A) \ - ((uint64_t)ipc_priv->hugepg_start.host_vaddr))) +#define MODEM_P2V(A) \ + ((uint64_t) ((unsigned long) (A) \ + + (unsigned long)(ipc_priv->peb_start.host_vaddr))) + static int ipc_queue_configure(uint32_t channel_id, ipc_t instance, struct bbdev_la12xx_q_priv *q_priv) { @@ -336,6 +342,318 @@ static const struct rte_bbdev_ops pmd_ops = { .queue_release = la12xx_queue_release, .start = la12xx_start }; + +static inline int +is_bd_ring_full(uint32_t ci, uint32_t ci_flag, + uint32_t pi, uint32_t pi_flag) +{ + if (pi == ci) { + if (pi_flag != ci_flag) + return 1; /* Ring is Full */ + } + return 0; +} + +static inline int +prepare_ldpc_enc_op(struct rte_bbdev_enc_op *bbdev_enc_op, + struct bbdev_la12xx_q_priv *q_priv __rte_unused, + struct rte_bbdev_op_data *in_op_data __rte_unused, + struct rte_bbdev_op_data *out_op_data) +{ + struct rte_bbdev_op_ldpc_enc *ldpc_enc = &bbdev_enc_op->ldpc_enc; + uint32_t total_out_bits; + + total_out_bits = (ldpc_enc->tb_params.cab * + ldpc_enc->tb_params.ea) + (ldpc_enc->tb_params.c - + ldpc_enc->tb_params.cab) * ldpc_enc->tb_params.eb; + + ldpc_enc->output.length = (total_out_bits + 7)/8; + + rte_pktmbuf_append(out_op_data->data, ldpc_enc->output.length); + + return 0; +} + +static inline int +prepare_ldpc_dec_op(struct rte_bbdev_dec_op *bbdev_dec_op, + struct bbdev_ipc_dequeue_op *bbdev_ipc_op, + struct bbdev_la12xx_q_priv *q_priv __rte_unused, + struct rte_bbdev_op_data *out_op_data __rte_unused) +{ + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &bbdev_dec_op->ldpc_dec; + uint32_t total_out_bits; + uint32_t num_code_blocks = 0; + uint16_t sys_cols; + + sys_cols = (ldpc_dec->basegraph == 1) ? 22 : 10; + if (ldpc_dec->tb_params.c == 1) { + total_out_bits = ((sys_cols * ldpc_dec->z_c) - + ldpc_dec->n_filler); + /* 5G-NR protocol uses 16 bit CRC when output packet + * size <= 3824 (bits). Otherwise 24 bit CRC is used. + * Adjust the output bits accordingly + */ + if (total_out_bits - 16 <= 3824) + total_out_bits -= 16; + else + total_out_bits -= 24; + ldpc_dec->hard_output.length = (total_out_bits / 8); + } else { + total_out_bits = (((sys_cols * ldpc_dec->z_c) - + ldpc_dec->n_filler - 24) * + ldpc_dec->tb_params.c); + ldpc_dec->hard_output.length = (total_out_bits / 8) - 3; + } + + num_code_blocks = ldpc_dec->tb_params.c; + + bbdev_ipc_op->num_code_blocks = rte_cpu_to_be_32(num_code_blocks); + + return 0; +} + +static int +enqueue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *bbdev_op) +{ + struct bbdev_la12xx_private *priv = q_priv->bbdev_priv; + ipc_userspace_t *ipc_priv = priv->ipc_priv; + ipc_instance_t *ipc_instance = ipc_priv->instance; + struct bbdev_ipc_dequeue_op *bbdev_ipc_op; + struct rte_bbdev_op_ldpc_enc *ldpc_enc; + struct rte_bbdev_op_ldpc_dec *ldpc_dec; + uint32_t q_id = q_priv->q_id; + uint32_t ci, ci_flag, pi, pi_flag; + ipc_ch_t *ch = &(ipc_instance->ch_list[q_id]); + ipc_br_md_t *md = &(ch->md); + size_t virt; + char *huge_start_addr = + (char *)q_priv->bbdev_priv->ipc_priv->hugepg_start.host_vaddr; + struct rte_bbdev_op_data *in_op_data, *out_op_data; + char *data_ptr; + uint32_t l1_pcie_addr; + int ret; + + ci = IPC_GET_CI_INDEX(q_priv->host_ci); + ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci); + + pi = IPC_GET_PI_INDEX(q_priv->host_pi); + pi_flag = IPC_GET_PI_FLAG(q_priv->host_pi); + + rte_bbdev_dp_log(DEBUG, "before bd_ring_full: pi: %u, ci: %u," + "pi_flag: %u, ci_flag: %u, ring size: %u", + pi, ci, pi_flag, ci_flag, q_priv->queue_size); + + if (is_bd_ring_full(ci, ci_flag, pi, pi_flag)) { + rte_bbdev_dp_log(DEBUG, "bd ring full for queue id: %d", q_id); + return IPC_CH_FULL; + } + + virt = MODEM_P2V(q_priv->host_params->bd_m_modem_ptr[pi]); + bbdev_ipc_op = (struct bbdev_ipc_dequeue_op *)virt; + q_priv->bbdev_op[pi] = bbdev_op; + + switch (q_priv->op_type) { + case RTE_BBDEV_OP_LDPC_ENC: + ldpc_enc = &(((struct rte_bbdev_enc_op *)bbdev_op)->ldpc_enc); + in_op_data = &ldpc_enc->input; + out_op_data = &ldpc_enc->output; + + ret = prepare_ldpc_enc_op(bbdev_op, q_priv, + in_op_data, out_op_data); + if (ret) { + rte_bbdev_log(ERR, "process_ldpc_enc_op fail, ret: %d", + ret); + return ret; + } + break; + + case RTE_BBDEV_OP_LDPC_DEC: + ldpc_dec = &(((struct rte_bbdev_dec_op *)bbdev_op)->ldpc_dec); + in_op_data = &ldpc_dec->input; + + out_op_data = &ldpc_dec->hard_output; + + ret = prepare_ldpc_dec_op(bbdev_op, bbdev_ipc_op, + q_priv, out_op_data); + if (ret) { + rte_bbdev_log(ERR, "process_ldpc_dec_op fail, ret: %d", + ret); + return ret; + } + break; + + default: + rte_bbdev_log(ERR, "unsupported bbdev_ipc op type"); + return -1; + } + + if (in_op_data->data) { + data_ptr = rte_pktmbuf_mtod(in_op_data->data, char *); + l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR + + data_ptr - huge_start_addr; + bbdev_ipc_op->in_addr = l1_pcie_addr; + bbdev_ipc_op->in_len = in_op_data->length; + } + + if (out_op_data->data) { + data_ptr = rte_pktmbuf_mtod(out_op_data->data, char *); + l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR + + data_ptr - huge_start_addr; + bbdev_ipc_op->out_addr = rte_cpu_to_be_32(l1_pcie_addr); + bbdev_ipc_op->out_len = rte_cpu_to_be_32(out_op_data->length); + } + + /* Move Producer Index forward */ + pi++; + /* Flip the PI flag, if wrapping */ + if (unlikely(q_priv->queue_size == pi)) { + pi = 0; + pi_flag = pi_flag ? 0 : 1; + } + + if (pi_flag) + IPC_SET_PI_FLAG(pi); + else + IPC_RESET_PI_FLAG(pi); + q_priv->host_pi = pi; + + /* Wait for Data Copy & pi_flag update to complete before updating pi */ + rte_mb(); + /* now update pi */ + md->pi = rte_cpu_to_be_32(pi); + + rte_bbdev_dp_log(DEBUG, "enter: pi: %u, ci: %u," + "pi_flag: %u, ci_flag: %u, ring size: %u", + pi, ci, pi_flag, ci_flag, q_priv->queue_size); + + return 0; +} + +/* Enqueue decode burst */ +static uint16_t +enqueue_dec_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + int nb_enqueued, ret; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ret = enqueue_single_op(q_priv, ops[nb_enqueued]); + if (ret) + break; + } + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + +/* Enqueue encode burst */ +static uint16_t +enqueue_enc_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + int nb_enqueued, ret; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ret = enqueue_single_op(q_priv, ops[nb_enqueued]); + if (ret) + break; + } + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + +/* Dequeue encode burst */ +static void * +dequeue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *dst) +{ + void *op; + uint32_t ci, ci_flag; + uint32_t temp_ci; + + temp_ci = q_priv->host_params->ci; + if (temp_ci == q_priv->host_ci) + return NULL; + + ci = IPC_GET_CI_INDEX(q_priv->host_ci); + ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci); + + rte_bbdev_dp_log(DEBUG, + "ci: %u, ci_flag: %u, ring size: %u", + ci, ci_flag, q_priv->queue_size); + + op = q_priv->bbdev_op[ci]; + + rte_memcpy(dst, q_priv->msg_ch_vaddr[ci], + sizeof(struct bbdev_ipc_enqueue_op)); + + /* Move Consumer Index forward */ + ci++; + /* Flip the CI flag, if wrapping */ + if (q_priv->queue_size == ci) { + ci = 0; + ci_flag = ci_flag ? 0 : 1; + } + if (ci_flag) + IPC_SET_CI_FLAG(ci); + else + IPC_RESET_CI_FLAG(ci); + + q_priv->host_ci = ci; + + rte_bbdev_dp_log(DEBUG, + "exit: ci: %u, ci_flag: %u, ring size: %u", + ci, ci_flag, q_priv->queue_size); + + return op; +} + +/* Dequeue decode burst */ +static uint16_t +dequeue_dec_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + struct bbdev_ipc_enqueue_op bbdev_ipc_op; + int nb_dequeued; + + for (nb_dequeued = 0; nb_dequeued < nb_ops; nb_dequeued++) { + ops[nb_dequeued] = dequeue_single_op(q_priv, &bbdev_ipc_op); + if (!ops[nb_dequeued]) + break; + ops[nb_dequeued]->status = bbdev_ipc_op.status; + } + q_data->queue_stats.dequeued_count += nb_dequeued; + + return nb_dequeued; +} + +/* Dequeue encode burst */ +static uint16_t +dequeue_enc_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + struct bbdev_ipc_enqueue_op bbdev_ipc_op; + int nb_enqueued; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ops[nb_enqueued] = dequeue_single_op(q_priv, &bbdev_ipc_op); + if (!ops[nb_enqueued]) + break; + ops[nb_enqueued]->status = bbdev_ipc_op.status; + } + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + static struct hugepage_info * get_hugepage_info(void) { @@ -709,10 +1027,14 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev, bbdev->intr_handle = NULL; /* register rx/tx burst functions for data path */ - bbdev->dequeue_enc_ops = NULL; - bbdev->dequeue_dec_ops = NULL; - bbdev->enqueue_enc_ops = NULL; - bbdev->enqueue_dec_ops = NULL; + bbdev->dequeue_enc_ops = dequeue_enc_ops; + bbdev->dequeue_dec_ops = dequeue_dec_ops; + bbdev->enqueue_enc_ops = enqueue_enc_ops; + bbdev->enqueue_dec_ops = enqueue_dec_ops; + bbdev->dequeue_ldpc_enc_ops = dequeue_enc_ops; + bbdev->dequeue_ldpc_dec_ops = dequeue_dec_ops; + bbdev->enqueue_ldpc_enc_ops = enqueue_enc_ops; + bbdev->enqueue_ldpc_dec_ops = enqueue_dec_ops; return 0; } diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h index 5f613fb087..b6a7f677d0 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h @@ -73,6 +73,25 @@ typedef struct { _IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *) #define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *) +#define GUL_USER_HUGE_PAGE_OFFSET (0) +#define GUL_PCI1_ADDR_BASE (0x00000000ULL) + +#define GUL_USER_HUGE_PAGE_ADDR (GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET) + +/* IPC PI/CI index & flag manipulation helpers */ +#define IPC_PI_CI_FLAG_MASK 0x80000000 /* (1<<31) */ +#define IPC_PI_CI_INDEX_MASK 0x7FFFFFFF /* ~(1<<31) */ + +#define IPC_SET_PI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK) +#define IPC_RESET_PI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK) +#define IPC_GET_PI_FLAG(x) (x >> 31) +#define IPC_GET_PI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) + +#define IPC_SET_CI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK) +#define IPC_RESET_CI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK) +#define IPC_GET_CI_FLAG(x) (x >> 31) +#define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) + /** buffer ring common metadata */ typedef struct ipc_bd_ring_md { volatile uint32_t pi; /**< Producer index and flag (MSB) @@ -180,6 +199,24 @@ struct bbdev_ipc_enqueue_op { uint32_t rsvd; }; +/** Structure specifying dequeue operation (dequeue at LA1224) */ +struct bbdev_ipc_dequeue_op { + /** Input buffer memory address */ + uint32_t in_addr; + /** Input buffer memory length */ + uint32_t in_len; + /** Output buffer memory address */ + uint32_t out_addr; + /** Output buffer memory length */ + uint32_t out_len; + /* Number of code blocks. Only set when HARQ is used */ + uint32_t num_code_blocks; + /** Dequeue Operation flags */ + uint32_t op_flags; + /** Shared metadata between L1 and L2 */ + uint32_t shared_metadata; +}; + /* This shared memory would be on the host side which have copy of some * of the parameters which are also part of Shared BD ring. Read access * of these parameters from the host side would not be over PCI. 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For instance, if the driver supports big endian data processing, but the test vector does not mention the data as a big endian format, conversion from little endian to big will be handled by the testbbdev application. Signed-off-by: Nipun Gupta --- app/test-bbdev/test_bbdev_perf.c | 84 ++++++++++++++++++++++++++++++ app/test-bbdev/test_bbdev_vector.c | 4 ++ 2 files changed, 88 insertions(+) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 469597b8b3..836e07d747 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -227,6 +227,71 @@ clear_soft_out_cap(uint32_t *op_flags) *op_flags &= ~RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT; } +static void +clear_ldpc_endianness_flag(uint32_t *op_flags) +{ + *op_flags &= ~RTE_BBDEV_LDPC_ENC_BIG_ENDIAN; + *op_flags &= ~RTE_BBDEV_LDPC_DEC_BIG_ENDIAN; +} + +static inline void +reverse_op(struct op_data_entries *op) +{ + uint8_t nb_segs = op->nb_segments; + uint32_t *data, len; + int complete, rem, i, j; + uint8_t *rem_data, temp; + + /* Validate each mbuf segment length */ + for (i = 0; i < nb_segs; ++i) { + len = op->segments[i].length; + data = op->segments[i].addr; + + /* Swap complete u32 bytes */ + complete = len / 4; + for (j = 0; j < complete; j++) + data[j] = rte_bswap32(data[j]); + + /* Swap any remaining data for last seg */ + if (i == (nb_segs - 1)) { + rem = len % 4; + rem_data = (uint8_t *)&data[j]; + for (j = 0; j < rem/2; j++) { + temp = rem_data[j]; + rem_data[j] = rem_data[rem - j - 1]; + rem_data[rem - j - 1] = temp; + } + } + } +} + +static inline void +reverse_all_ops(void) +{ + unsigned int nb_inputs, nb_soft_outputs, nb_hard_outputs, + nb_harq_inputs, nb_harq_outputs; + + nb_inputs = test_vector.entries[DATA_INPUT].nb_segments; + if (nb_inputs) + reverse_op(&test_vector.entries[DATA_INPUT]); + + nb_soft_outputs = test_vector.entries[DATA_SOFT_OUTPUT].nb_segments; + if (nb_soft_outputs) + reverse_op(&test_vector.entries[DATA_SOFT_OUTPUT]); + + nb_hard_outputs = test_vector.entries[DATA_HARD_OUTPUT].nb_segments; + if (nb_hard_outputs) + reverse_op(&test_vector.entries[DATA_HARD_OUTPUT]); + + nb_harq_inputs = test_vector.entries[DATA_HARQ_INPUT].nb_segments; + if (nb_harq_inputs) + reverse_op(&test_vector.entries[DATA_HARQ_INPUT]); + + nb_harq_outputs = test_vector.entries[DATA_HARQ_OUTPUT].nb_segments; + if (nb_harq_outputs) + reverse_op(&test_vector.entries[DATA_HARQ_OUTPUT]); +} + static int check_dev_cap(const struct rte_bbdev_info *dev_info) { @@ -324,6 +389,16 @@ check_dev_cap(const struct rte_bbdev_info *dev_info) const struct rte_bbdev_op_cap_ldpc_enc *cap = &op_cap->cap.ldpc_enc; + if ((test_vector.ldpc_enc.op_flags & + RTE_BBDEV_LDPC_ENC_BIG_ENDIAN) != + (cap->capability_flags & + RTE_BBDEV_LDPC_ENC_BIG_ENDIAN)) { + reverse_all_ops(); + clear_ldpc_endianness_flag( + &test_vector.ldpc_enc.op_flags); + + } + if (!flags_match(test_vector.ldpc_enc.op_flags, cap->capability_flags)){ printf("Flag Mismatch\n"); @@ -352,6 +427,15 @@ check_dev_cap(const struct rte_bbdev_info *dev_info) const struct rte_bbdev_op_cap_ldpc_dec *cap = &op_cap->cap.ldpc_dec; + if ((test_vector.ldpc_dec.op_flags & + RTE_BBDEV_LDPC_DEC_BIG_ENDIAN) != + (cap->capability_flags & + RTE_BBDEV_LDPC_DEC_BIG_ENDIAN)) { + reverse_all_ops(); + clear_ldpc_endianness_flag( + &test_vector.ldpc_dec.op_flags); + } + if (!flags_match(test_vector.ldpc_dec.op_flags, cap->capability_flags)){ printf("Flag Mismatch\n"); diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c index 614dbd1a6d..b2e7a9008d 100644 --- a/app/test-bbdev/test_bbdev_vector.c +++ b/app/test-bbdev/test_bbdev_vector.c @@ -191,6 +191,8 @@ op_ldpc_decoder_flag_strtoul(char *token, uint32_t *op_flag_value) *op_flag_value = RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; else if (!strcmp(token, "RTE_BBDEV_LDPC_LLR_COMPRESSION")) *op_flag_value = RTE_BBDEV_LDPC_LLR_COMPRESSION; + else if (!strcmp(token, "RTE_BBDEV_LDPC_DEC_BIG_ENDIAN")) + *op_flag_value = RTE_BBDEV_LDPC_DEC_BIG_ENDIAN; else if (!strcmp(token, "RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE")) *op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE; @@ -248,6 +250,8 @@ op_ldpc_encoder_flag_strtoul(char *token, uint32_t *op_flag_value) *op_flag_value = RTE_BBDEV_LDPC_ENC_INTERRUPTS; else if (!strcmp(token, "RTE_BBDEV_LDPC_ENC_SCATTER_GATHER")) *op_flag_value = RTE_BBDEV_LDPC_ENC_SCATTER_GATHER; + else if (!strcmp(token, "RTE_BBDEV_LDPC_ENC_BIG_ENDIAN")) + *op_flag_value = RTE_BBDEV_LDPC_ENC_BIG_ENDIAN; else { printf("The given value is not a turbo encoder flag\n"); return -1; From patchwork Sun Sep 12 12:15:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 98718 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 314B6A0C4B; Sun, 12 Sep 2021 14:16:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 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ztv3lI9ldf6QPHICjheU8BWIeeEIiOyoHrQGBNGXzpUtYvL2sS9jKHz9Dzwwv7xfCSoXcHjSagNU6iT/rnGpCHRyWwdQNiB/Ec2dRYs3kY2Z/XknE45JOJen8KI/8P5jkPZW7tZuvsXMh9CsQ7mE3iiOu8c+Z3myvKrAISwnG0S+rOI6o61SE0FhT0KCLErGXxRPoVPTVdRUwW2SxQD5wthLXKkD2NehTk+97zbvXlAZTl+hDZ2mL+pN1ZXz8mDZBXJT8Ow99uuNwiDNGjG+cmEL8DhdMOdKGhr1Mt/M7RVj1UQbq4Jc6Q9NbBvfpo0nEbD2qdjC8sSAPMLXAR55ekoJwXDBw8+ptyIIzz/WQyajDybZP7lpM1nl0tmO9KTdPb16clH5Gwwk9eOwhyZ549OiHbytnmyreskU6KuuIzN52Z4uWaCJrCOxZwy6l+M2RnMV2LRJxY9hxJCTCuk/KQpwBWSk6CyrWxvorqYcSGd4OKSFsPOQEtLVq3MbIHby0dH0KWwdIk6+T1LYCmktXLt7D51C2qA4hVUhCR7vnnsVx2qqyeZ8Mc0Gbs01yzerMIgZWQbgYDPwP3RYhFZcolrC1ALolSTfHwl5Lw/wjSiwItTTsRHa/icBCNf8ZqvENEOSfHt6nh76SveLYLbIUyJyVpZgiY77kEApQgi5bIFhtQVYdVv5yj59H/NmVtVvHz9jaeyGcLwpgg7V+QO98MVic/nZiOGFvOodtGp75Js2fT8mfQsfcEqSxz/heA+ae/rG0K4SaaAVLkMvrPf2C3pjLp/YyJpMh4tPP56lL0OeVXrMrUQVYOqaBAe7ZPoHQtK/CVdrMgF4mlAl8L3ilizQ0e8A8WyaakArNvN3n3k0nnnjJ1NhAOMwhjhaeQ4pDrK/XDEnBwbwv7Cvn3BJloHTKEtaIEo/aa2gHGMjyTO+GgK4fM4G0i+N5+KHbL7lyv8M5fuaVLygxYSJy0MuIZM19DXSIAskI8s2MCdbJtmfP4YaW1UmUxsOnnnXmeBiTPYSYfx0IwbH2uVlLM+XrN+XMXnWxkzyq41NHwjA2ZK4VLsNVMjnq1+9F+bz3rMEned5z3fnV9HSgZz64PpYiuzidRDXIPnX7hq1K1lBH4s1FXWyC4I6r+np5W54VhPATY55rikIBgEzNp+yCHuZKQxFVp87hagZ6UAPNQaX6gpliJgJGyl4euzYNs3w+x28UEo3w0kCizOphhWhuhCcST7rc/xv+HV3AHe6SyoHfIDZBX2DhLYvuxj5ETU9WSjOnPjltPEELw0JlS+2hmFG2tF/l/Kv3SwFBaOyVOeDYZxb4jqCPz2GCR/1+KPe4CA4 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 82f299eb-208f-469d-31cb-08d975e71214 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8429.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2021 12:15:55.2173 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dqylbcbxGTYulVYI1mjYMtTDIRlKosobyZDzhrBGVMZ2IBMUazIwQw4HESHianV+8B214timCCsd2gGVAZSajA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8202 Subject: [dpdk-dev] [PATCH v5 9/9] app/bbdev: add test vectors for transport blocks X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds two test vectors for transport block in network byte order: - LDPC encode for Transport Block - LDPC decode for Transport block Signed-off-by: Nipun Gupta --- app/test-bbdev/test_vectors/ldpc_dec_tb.data | 122 +++++++++++++++++++ app/test-bbdev/test_vectors/ldpc_enc_tb.data | 60 +++++++++ 2 files changed, 182 insertions(+) create mode 100644 app/test-bbdev/test_vectors/ldpc_dec_tb.data create mode 100644 app/test-bbdev/test_vectors/ldpc_enc_tb.data diff --git a/app/test-bbdev/test_vectors/ldpc_dec_tb.data b/app/test-bbdev/test_vectors/ldpc_dec_tb.data new file mode 100644 index 0000000000..b991e8f305 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_dec_tb.data @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2020 NXP + +op_type = +RTE_BBDEV_OP_LDPC_DEC + +input0 = +0x817f8181, 0x7f7f8181, 0x817f7f81, 0x81817f81, 0x81817f81, 0x817f7f81, 0x7f7f7f7f, 0x7f7f7f81, +0x817f7f81, 0x817f7f81, 0x7f7f817f, 0x7f7f7f81, 0x81817f7f, 0x81818181, 0x817f8181, 0x7f817f81, +0x81817f7f, 0x7f7f817f, 0x81817f81, 0x817f8181, 0x7f7f7f81, 0x817f817f, 0x7f817f7f, 0x7f817f7f, +0x7f817f7f, 0x81817f7f, 0x7f818181, 0x817f7f7f, 0x8181817f, 0x81817f7f, 0x7f817f81, 0x7f7f7f7f, +0x7f817f7f, 0x81817f7f, 0x81818181, 0x817f817f, 0x81817f7f, 0x7f81817f, 0x7f7f7f7f, 0x7f7f7f7f, +0x7f818181, 0x7f7f7f81, 0x81817f81, 0x7f817f7f, 0x7f7f7f7f, 0x817f817f, 0x817f817f, 0x7f7f817f, +0x81817f81, 0x7f7f7f7f, 0x7f81817f, 0x817f817f, 0x7f7f8181, 0x7f7f7f7f, 0x817f7f7f, 0x81818181, +0x817f8181, 0x7f7f817f, 0x7f7f8181, 0x7f7f7f7f, 0x7f818181, 0x817f8181, 0x817f7f81, 0x817f8181, +0x817f7f81, 0x81817f7f, 0x7f7f8181, 0x81818181, 0x817f817f, 0x817f7f7f, 0x81818181, 0x7f817f81, +0x7f7f7f81, 0x81817f81, 0x7f817f7f, 0x7f818181, 0x7f7f7f81, 0x817f817f, 0x81818181, 0x81818181, +0x81817f81, 0x81817f81, 0x7f7f8181, 0x817f7f7f, 0x7f81817f, 0x817f817f, 0x81817f7f, 0x817f7f81, +0x81817f7f, 0x7f7f7f81, 0x7f817f81, 0x7f817f81, 0x817f7f7f, 0x7f818181, 0x81818181, 0x7f7f7f7f, +0x7f7f7f7f, 0x8181817f, 0x7f7f7f81, 0x7f817f81, 0x81817f81, 0x7f7f817f, 0x7f81817f, 0x817f8181, +0x7f81817f, 0x7f81817f, 0x817f7f7f, 0x7f81817f, 0x817f7f81, 0x817f7f81, 0x7f817f7f, 0x8181817f, +0x7f81817f, 0x7f7f8181, 0x817f8181, 0x817f7f7f, 0x817f7f81, 0x7f81817f, 0x7f7f817f, 0x7f817f7f, +0x7f7f8181, 0x81818181, 0x7f818181, 0x7f7f817f, 0x7f818181, 0x81818181, 0x7f817f7f, 0x817f817f, +0x817f817f, 0x817f7f7f, 0x81817f81, 0x81817f7f, 0x81817f81, 0x7f817f81, 0x7f817f7f, 0x7f817f7f, +0x817f7f7f, 0x817f7f7f, 0x7f7f7f7f, 0x7f7f7f81, 0x7f7f8181, 0x7f817f81, 0x7f817f7f, 0x817f7f7f, +0x7f7f8181, 0x8181817f, 0x7f7f8181, 0x7f7f7f81, 0x817f7f7f, 0x7f7f7f81, 0x817f8181, 0x7f7f817f, +0x7f81817f, 0x817f817f, 0x7f817f81, 0x7f7f8181, 0x7f818181, 0x7f817f81, 0x81818181, 0x81817f7f, +0x7f81817f, 0x7f81817f, 0x7f7f8181, 0x81818181, 0x817f8181, 0x7f7f817f, 0x7f817f7f, 0x7f7f8181, +0x7f81817f, 0x7f7f817f, 0x7f7f7f7f, 0x7f818181, 0x81817f7f, 0x8181817f, 0x7f81817f, 0x8181817f, +0x81817f81, 0x7f7f7f7f, 0x81818181, 0x7f7f817f, 0x7f81817f, 0x7f7f7f7f, 0x81817f81, 0x817f7f81, +0x817f7f81, 0x817f7f81, 0x81818181, 0x7f7f7f7f, 0x81817f81, 0x817f7f7f, 0x8181817f, 0x7f7f7f81, +0x81817f81, 0x817f7f81, 0x81818181, 0x7f7f7f7f, 0x81817f7f, 0x81817f81, 0x7f7f7f81, 0x7f7f7f7f, +0x817f817f, 0x7f818181, 0x8181817f, 0x81817f81, 0x7f7f7f81, 0x7f817f7f, 0x7f7f7f7f, 0x7f817f81, +0x8181817f, 0x7f7f7f7f, 0x81817f7f, 0x7f7f7f81, 0x7f81817f, 0x7f7f7f7f, 0x7f7f7f81, 0x817f8181, +0x7f7f8181, 0x7f7f7f81, 0x7f7f8181, 0x7f817f7f, 0x81818181, 0x7f81817f, 0x7f818181, 0x7f818181, +0x7f818181, 0x817f7f81, 0x7f7f8181, 0x81818181, 0x7f7f7f7f, 0x7f7f7f7f, 0x817f8181, 0x81818181, +0x7f7f817f, 0x817f8181, 0x81817f7f, 0x817f817f, 0x7f7f817f, 0x7f7f7f7f, 0x817f8181, 0x817f8181, +0x817f8181, 0x81818181, 0x7f7f817f, 0x7f817f81, 0x817f7f81, 0x7f7f7f81, 0x81817f81, 0x7f818181, +0x81817f7f, 0x7f818181, 0x81818181, 0x817f817f, 0x7f817f7f, 0x81818181, 0x817f8181, 0x7f7f7f7f, +0x7f817f81, 0x817f7f7f, 0x7f818181, 0x8181817f, 0x817f817f, 0x7f817f7f, 0x817f7f81, 0x7f818181, +0x817f7f7f, 0x817f7f81, 0x7f7f7f81, 0x81817f81, 0x7f81817f, 0x7f818181, 0x81817f7f, 0x817f7f81, +0x81817f81, 0x7f7f8181, 0x7f7f8181, 0x7f817f81, 0x7f7f817f, 0x817f7f7f, 0x7f7f7f7f, 0x817f7f7f, +0x7f7f8181, 0x817f8181, 0x817f8181, 0x7f817f81, 0x817f8181, 0x8181817f, 0x81817f7f, 0x7f817f7f, +0x7f817f7f, 0x7f817f81, 0x817f817f, 0x817f7f7f, 0x8181817f, 0x817f817f, 0x817f7f81, 0x81817f7f, +0x7f817f7f, 0x7f7f7f7f, 0x7f817f7f, 0x7f7f817f, 0x7f818181, 0x8181817f, 0x817f7f7f, 0x7f817f81, +0x7f7f8181, 0x81817f7f, 0x7f7f817f, 0x7f7f817f, 0x7f817f7f, 0x7f7f817f, 0x7f818181, 0x7f817f7f, +0x817f7f7f, 0x7f817f81, 0x81818181, 0x7f818181, 0x817f8181, 0x8181817f, 0x8181817f, 0x817f7f7f, +0x81817f81, 0x817f7f7f, 0x7f81817f, 0x817f8181, 0x7f818181, 0x7f817f7f, 0x81817f7f, 0x7f81817f, +0x81817f81, 0x7f7f7f81, 0x7f7f7f7f, 0x81818181, 0x817f7f7f, 0x81817f81, 0x817f7f81, 0x81817f7f, +0x81818181, 0x7f7f7f7f, 0x817f817f, 0x7f817f81, 0x817f7f7f, 0x7f817f81, 0x817f8181, 0x7f81817f, +0x7f818181, 0x7f7f8181, 0x817f817f, 0x7f7f7f7f, 0x81818181, 0x7f817f81, 0x81817f81, 0x7f81817f, +0x81818181, 0x7f7f817f, 0x81818181, 0x7f7f7f81, 0x817f7f81, 0x8181817f, 0x7f818181, 0x7f7f7f7f, +0x7f7f7f7f, 0x8181817f, 0x81817f81, 0x81818181, 0x7f7f817f, 0x81817f7f, 0x7f817f81, 0x817f8181, +0x81817f7f, 0x7f817f7f, 0x817f7f7f, 0x7f81817f, 0x817f7f7f, 0x7f7f7f7f, 0x7f7f8181, 0x7f7f8181, +0x7f81817f, 0x7f7f8181, 0x7f7f8181, 0x817f7f81, 0x8181817f, 0x81817f7f, 0x817f8181, 0x817f817f, +0x8181817f, 0x7f7f8181, 0x7f81817f, 0x817f817f, 0x7f817f81, 0x7f817f7f, 0x7f7f8181, 0x81818181, +0x7f817f81, 0x7f7f8181, 0x81817f7f, 0x7f7f7f81, 0x7f7f7f81, 0x7f7f7f7f, 0x7f81817f, 0x7f7f8181, +0x7f7f817f, 0x817f817f, 0x7f7f7f7f, 0x817f8181, 0x7f818181, 0x7f7f817f, 0x8181817f, 0x8181817f, +0x817f7f81, 0x8181817f, 0x817f8181, 0x7f817f7f, 0x81817f7f, 0x81818181, 0x7f7f8181, 0x7f817f81, +0x817f8181, 0x7f817f7f, 0x81818181, 0x81817f81, 0x7f817f81, 0x81817f7f, 0x7f818181, 0x8181817f, +0x7f7f7f81, 0x7f81817f, 0x7f7f8181, 0x81818181, 0x81817f7f, 0x817f8181, 0x81817f7f, 0x7f7f817f, +0x81818181, 0x7f7f8181, 0x7f7f817f, 0x817f817f, 0x7f817f81, 0x7f7f7f7f, 0x7f817f81, 0x7f817f7f, +0x7f81817f, 0x7f7f8181, 0x7f7f817f, 0x81818181, 0x7f7f8181, 0x817f7f81, 0x81817f81, 0x81817f7f, +0x81817f81, 0x81818181, 0x7f817f81, 0x7f7f7f7f, 0x81817f7f, 0x7f817f7f, 0x7f7f817f, 0x81817f7f, +0x81817f7f, 0x7f7f7f7f, 0x817f7f7f, 0x7f817f81, 0x81818181, 0x81817f7f, 0x7f817f7f, 0x8181817f, +0x7f81817f, 0x817f7f81, 0x7f817f7f, 0x7f7f7f7f, 0x817f7f81, 0x7f817f81, 0x81818181, 0x81817f81, +0x7f817f81, 0x81818181, 0x81818181, 0x8181817f, 0x7f7f817f, 0x817f7f7f, 0x817f7f7f, 0x7f7f7f7f, +0x81818181, 0x7f817f7f, 0x817f7f81, 0x7f7f8181, 0x817f8181, 0x81817f7f, 0x81817f7f, 0x817f7f7f, +0x817f817f, 0x7f818181, 0x7f817f7f, 0x817f8181, 0x7f817f7f, 0x817f8181, 0x7f7f817f, 0x81817f7f, +0x8181817f, 0x7f817f81, 0x7f7f7f81, 0x81818181, 0x7f7f7f81, 0x81818181, 0x7f7f817f, 0x817f7f7f, +0x817f817f, 0x7f7f8181, 0x7f7f7f81, 0x7f817f7f, 0x817f8181, 0x817f817f, 0x81818181, 0x81817f7f + +output0 = +0xea7bdad9, 0xabd8311a, 0x4e7ba2e2, 0x5c5c5c85, 0xc400ed50, 0x9bea8883, 0xb7f0 + +basegraph= +2 + +z_c= +28 + +n_cb= +1400 + +q_m= +2 + +n_filler= +56 + +ea = +2048 + +eb = +2048 + +iter_max= +8 + +expected_iter_count= +2 + +c = +1 + +r = +0 + +cab = +0 + +rv_index = +0 + +code_block_mode = +0 + +op_flags = +RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP, RTE_BBDEV_LDPC_DEC_BIG_ENDIAN + +expected_status = +OK diff --git a/app/test-bbdev/test_vectors/ldpc_enc_tb.data b/app/test-bbdev/test_vectors/ldpc_enc_tb.data new file mode 100644 index 0000000000..277db673c8 --- /dev/null +++ b/app/test-bbdev/test_vectors/ldpc_enc_tb.data @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2020 NXP + +op_type = +RTE_BBDEV_OP_LDPC_ENC + +input0 = +0xea7bdad9, 0xabd8311a, 0x4e7ba2e2, 0x5c5c5c85, 0xc400ed50, 0x9bea8883, 0xb7f0 + +output0 = +0x109dd93b, 0x5bfc1299, 0x44a1bd2c, 0x05ce87c4, 0x006cafc4, 0x2aa04d17, 0xf803a60d, 0xb9b7032b, +0x5f8af3c9, 0xffa174d1, 0x9ca683dd, 0x0f78551c, 0xb62d51e0, 0xe4996866, 0x42698b36, 0xa4f727f3, +0x445dcd8a, 0x84531088, 0x2b1813e3, 0xcf5735a6, 0x342bf366, 0xe6ec7026, 0x9d062f0d, 0x1e8d0f99, +0x01dc0f9d, 0x5041de7a, 0xb1061c0e, 0x776f4313, 0xfb00f397, 0xbb02acb2, 0x7d1952fb, 0x0bf4af7c, +0x794ae785, 0x9c76d198, 0x8082533d, 0x4ceb5bb3, 0xc9ae8a54, 0x58e72404, 0x472422c3, 0x8eeb7f58, +0x6c47b68d, 0xc9d8f01d, 0x6b585a0f, 0x6d5f0a37, 0x07e91f2f, 0xb5c2fde0, 0x3308684c, 0xabce9336, +0xf345a63e, 0x36011c35, 0xee27b0a2, 0x53fc4be9, 0xe7c5df4b, 0x2cbcf361, 0x4505a23f, 0xcd93f236, +0xc24c05fd, 0xe4cf580c, 0xdf590496, 0x0882eff5, 0x8ccb394f, 0xc2b4b47a, 0x82f1f15e, 0xcfab413a + +basegraph= +2 + +z_c= +28 + +n_cb= +1400 + +q_m= +2 + +n_filler= +56 + +ea = +2048 + +eb = +2048 + +c = +1 + +r = +0 + +cab = +0 + +rv_index = +0 + +code_block_mode = +0 + +op_flags = +RTE_BBDEV_LDPC_CRC_24B_ATTACH, RTE_BBDEV_LDPC_ENC_BIG_ENDIAN + +expected_status = +OK