From patchwork Wed Jun 2 15:56:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93797 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E894A0524; Wed, 2 Jun 2021 17:56:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F53F410E0; Wed, 2 Jun 2021 17:56:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A90B8410DF for ; Wed, 2 Jun 2021 17:56:51 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJqY019768; Wed, 2 Jun 2021 08:56:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=8noq4biWFTi7jYNzcE4xaJzPn4W7X8tkICKyMxBa29A=; b=C5PAHbiL6pNB1KkkD41y1oITjTZM0VbF3rcAMLjCxNGW2X3UHNhlxbONnMfa4/4S7/gF rwjVzUPlBC26REgJKO4ZinZzUQvi35jkaJ08ueV/CcqHxi4dqkWRp9BCYV2OCewFzfKV UFMp15Tl8JmBg/kw/+vEcFAOFyo9hVkYBxIOt65OdtQjNhGkng6X2sZr1vNERqDHwmYy Yonu2AaKdmElG47IN6bHFuO++KxUEZByLmGyt/s4ue9Ja4j361Z6TffA0/pubccAUPaB H2wwrew4BS8LSR2C0zd609Wif43TZ/+noYInPr2tYh7ga+NvY+aAxG04ZPPqUvnroz4c 1A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhan-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 08:56:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:56:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:56:48 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 049C63F703F; Wed, 2 Jun 2021 08:56:44 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Vidya Sagar Velumuri , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:15 +0530 Message-ID: <1622649385-22652-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT X-Proofpoint-GUID: Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 01/11] common/cnxk: add CPT HW defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add CPT hardware definitions. CPT is the hardware block on cnxk family of processors, that can be used to offload cryptographic operations. Signed-off-by: Anoob Joseph Signed-off-by: Vidya Sagar Velumuri Acked-by: Akhil Goyal --- drivers/common/cnxk/hw/cpt.h | 201 ++++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_api.h | 6 ++ 2 files changed, 207 insertions(+) create mode 100644 drivers/common/cnxk/hw/cpt.h diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h new file mode 100644 index 0000000..d6a935c --- /dev/null +++ b/drivers/common/cnxk/hw/cpt.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CPT_HW_H__ +#define __CPT_HW_H__ + +/* Register offsets */ + +#define CPT_COMP_NOT_DONE (0x0ull) +#define CPT_COMP_GOOD (0x1ull) +#define CPT_COMP_FAULT (0x2ull) +#define CPT_COMP_SWERR (0x3ull) +#define CPT_COMP_HWERR (0x4ull) +#define CPT_COMP_INSTERR (0x5ull) +#define CPT_COMP_WARN (0x6ull) /* [CN10K, .) */ + +#define CPT_LF_INT_VEC_MISC (0x0ull) +#define CPT_LF_INT_VEC_DONE (0x1ull) +#define CPT_LF_CTL (0x10ull) +#define CPT_LF_DONE_WAIT (0x30ull) +#define CPT_LF_INPROG (0x40ull) +#define CPT_LF_DONE (0x50ull) +#define CPT_LF_DONE_ACK (0x60ull) +#define CPT_LF_DONE_INT_ENA_W1S (0x90ull) +#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull) +#define CPT_LF_MISC_INT (0xb0ull) +#define CPT_LF_MISC_INT_W1S (0xc0ull) +#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull) +#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull) +#define CPT_LF_Q_BASE (0xf0ull) +#define CPT_LF_Q_SIZE (0x100ull) +#define CPT_LF_Q_INST_PTR (0x110ull) +#define CPT_LF_Q_GRP_PTR (0x120ull) +#define CPT_LF_NQX(a) (0x400ull | (uint64_t)(a) << 3) +#define CPT_LF_CTX_CTL (0x500ull) +#define CPT_LF_CTX_FLUSH (0x510ull) +#define CPT_LF_CTX_ERR (0x520ull) +#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull) +#define CPT_LF_CTX_ENC_PKT_CNT (0x540ull) +#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull) +#define CPT_LF_CTX_DEC_PKT_CNT (0x560ull) + +#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3) +#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3) + +/* Structures definitions */ + +union cpt_lf_ctl { + uint64_t u; + struct cpt_lf_ctl_s { + uint64_t ena : 1; + uint64_t fc_ena : 1; + uint64_t fc_up_crossing : 1; + uint64_t reserved_3_3 : 1; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_8_63 : 56; + } s; +}; + +union cpt_lf_ctx_flush { + uint64_t u; + struct { + uint64_t cptr : 46; + uint64_t inval : 1; + uint64_t res : 1; + uint64_t pf_func : 16; + } s; +}; + +union cpt_lf_inprog { + uint64_t u; + struct cpt_lf_inprog_s { + uint64_t inflight : 9; + uint64_t reserved_9_15 : 7; + uint64_t eena : 1; + uint64_t grp_drp : 1; + uint64_t reserved_18_30 : 13; + uint64_t grb_partial : 1; + uint64_t grb_cnt : 8; + uint64_t gwb_cnt : 8; + uint64_t reserved_48_63 : 16; + } s; +}; + +union cpt_lf_q_base { + uint64_t u; + struct cpt_lf_q_base_s { + uint64_t fault : 1; + uint64_t stopped : 1; + uint64_t reserved_2_6 : 5; + uint64_t addr : 46; + uint64_t reserved_53_63 : 11; + } s; +}; + +union cpt_lf_q_size { + uint64_t u; + struct cpt_lf_q_size_s { + uint64_t size_div40 : 15; + uint64_t reserved_15_63 : 49; + } s; +}; + +union cpt_lf_misc_int { + uint64_t u; + struct cpt_lf_misc_int_s { + uint64_t reserved_0_0 : 1; + uint64_t nqerr : 1; + uint64_t irde : 1; + uint64_t nwrp : 1; + uint64_t reserved_4_4 : 1; + uint64_t hwerr : 1; + uint64_t fault : 1; + uint64_t reserved_7_63 : 57; + } s; +}; + +union cpt_inst_w4 { + uint64_t u64; + struct { + uint64_t dlen : 16; + uint64_t param2 : 16; + uint64_t param1 : 16; + uint64_t opcode_major : 8; + uint64_t opcode_minor : 8; + } s; +}; + +union cpt_inst_w7 { + uint64_t u64; + struct { + uint64_t cptr : 60; + uint64_t ctx_val : 1; + uint64_t egrp : 3; + } s; +}; + +struct cpt_inst_s { + union cpt_inst_w0 { + struct { + uint64_t nixtxl : 3; + uint64_t doneint : 1; + uint64_t nixtx_addr : 60; + } s; + uint64_t u64; + } w0; + + uint64_t res_addr; + + union cpt_inst_w2 { + struct { + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_172_175 : 4; + uint64_t rvu_pf_func : 16; + } s; + uint64_t u64; + } w2; + + union cpt_inst_w3 { + struct { + uint64_t qord : 1; + uint64_t reserved_194_193 : 2; + uint64_t wqe_ptr : 61; + } s; + uint64_t u64; + } w3; + + union cpt_inst_w4 w4; + + uint64_t dptr; + + uint64_t rptr; + + union cpt_inst_w7 w7; +}; + +union cpt_res_s { + struct cpt_cn10k_res_s { + uint64_t compcode : 7; + uint64_t doneint : 1; + uint64_t uc_compcode : 8; + uint64_t rlen : 16; + uint64_t spi : 32; + + uint64_t esn; + } cn10k; + + struct cpt_cn9k_res_s { + uint64_t compcode : 8; + uint64_t uc_compcode : 8; + uint64_t doneint : 1; + uint64_t reserved_17_63 : 47; + + uint64_t reserved_64_127; + } cn9k; +}; + +#endif /* __CPT_HW_H__ */ diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 67f5d13..049854d 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -54,6 +54,11 @@ #define PCI_DEVID_CN9K_CGX 0xA059 #define PCI_DEVID_CN10K_RPM 0xA060 +#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD +#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE +#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 +#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 + #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 @@ -64,6 +69,7 @@ #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100 /* HW structure definition */ +#include "hw/cpt.h" #include "hw/nix.h" #include "hw/npa.h" #include "hw/npc.h" From patchwork Wed Jun 2 15:56:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93798 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1F77A0524; Wed, 2 Jun 2021 17:56:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A533C40E50; Wed, 2 Jun 2021 17:56:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8AE5340689 for ; Wed, 2 Jun 2021 17:56:56 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJdF019782; Wed, 2 Jun 2021 08:56:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Wed, 2 Jun 2021 08:56:49 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , , Archana Muniganti , "Vidya Sagar Velumuri" Date: Wed, 2 Jun 2021 21:26:16 +0530 Message-ID: <1622649385-22652-3-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: OwAgTBREIOg77Gdy2bDiB_0cmOijJQ0b X-Proofpoint-GUID: OwAgTBREIOg77Gdy2bDiB_0cmOijJQ0b X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 02/11] common/cnxk: add CPT dev config routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add routines to init, fini, configure & clear CPT device. Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 3 + drivers/common/cnxk/roc_cpt.c | 273 +++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 32 +++++ drivers/common/cnxk/roc_cpt_priv.h | 28 ++++ drivers/common/cnxk/roc_dev.c | 2 + drivers/common/cnxk/roc_dev_priv.h | 1 + drivers/common/cnxk/roc_platform.c | 1 + drivers/common/cnxk/roc_platform.h | 2 + drivers/common/cnxk/roc_priv.h | 3 + drivers/common/cnxk/version.map | 6 + 11 files changed, 352 insertions(+) create mode 100644 drivers/common/cnxk/roc_cpt.c create mode 100644 drivers/common/cnxk/roc_cpt.h create mode 100644 drivers/common/cnxk/roc_cpt_priv.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 178bce7..739e0e4 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_cpt.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 049854d..88a5611 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -106,4 +106,7 @@ /* Idev */ #include "roc_idev.h" +/* CPT */ +#include "roc_cpt.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c new file mode 100644 index 0000000..3c0683c --- /dev/null +++ b/drivers/common/cnxk/roc_cpt.c @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +static int +cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp) +{ + struct mbox *mbox = dev->mbox; + int rc; + + /* Get MSIX vector offsets */ + mbox_alloc_msg_msix_offset(mbox); + rc = mbox_process_msg(mbox, (void *)msix_rsp); + + return rc; +} + +static int +cpt_lfs_attach(struct dev *dev, int nb_lf) +{ + struct mbox *mbox; + struct rsrc_attach_req *req; + + mbox = dev->mbox; + /* Attach CPT(lf) */ + req = mbox_alloc_msg_attach_resources(mbox); + if (req == NULL) + return -ENOSPC; + + req->cptlfs = nb_lf; + + return mbox_process(mbox); +} + +static int +cpt_lfs_detach(struct dev *dev) +{ + struct mbox *mbox = dev->mbox; + struct rsrc_detach_req *req; + + req = mbox_alloc_msg_detach_resources(mbox); + if (req == NULL) + return -ENOSPC; + + req->cptlfs = 1; + req->partial = 1; + + return mbox_process(mbox); +} + +static int +cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf) +{ + struct mbox *mbox = dev->mbox; + struct free_rsrcs_rsp *rsp; + int rc; + + mbox_alloc_msg_free_rsrc_cnt(mbox); + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return -EIO; + + *nb_lf = rsp->cpt; + return 0; +} + +static int +cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk) +{ + struct cpt_lf_alloc_req_msg *req; + struct mbox *mbox = dev->mbox; + + req = mbox_alloc_msg_cpt_lf_alloc(mbox); + req->nix_pf_func = 0; + req->sso_pf_func = idev_sso_pffunc_get(); + req->eng_grpmsk = eng_grpmsk; + + return mbox_process(mbox); +} + +static int +cpt_lfs_free(struct dev *dev) +{ + mbox_alloc_msg_cpt_lf_free(dev->mbox); + + return mbox_process(dev->mbox); +} + +static int +cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps) +{ + struct cpt_caps_rsp_msg *rsp; + int ret; + + mbox_alloc_msg_cpt_caps_get(dev->mbox); + + ret = mbox_process_msg(dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + mbox_memcpy(hw_caps, rsp->eng_caps, + sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES); + + return 0; +} + +int +roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct msix_offset_rsp *rsp; + uint8_t eng_grpmsk; + int rc, i; + + /* Request LF resources */ + rc = cpt_lfs_attach(&cpt->dev, nb_lf); + if (rc) + return rc; + + eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) | + (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) | + (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]); + + rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk); + if (rc) + goto lfs_detach; + + rc = cpt_get_msix_offset(&cpt->dev, &rsp); + if (rc) + goto lfs_free; + + for (i = 0; i < nb_lf; i++) + cpt->lf_msix_off[i] = + (cpt->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ? + rsp->cpt1_lf_msixoff[i] : + rsp->cptlf_msixoff[i]; + + roc_cpt->nb_lf = nb_lf; + + return 0; + +lfs_free: + cpt_lfs_free(&cpt->dev); +lfs_detach: + cpt_lfs_detach(&cpt->dev); + return rc; +} + +int +roc_cpt_dev_init(struct roc_cpt *roc_cpt) +{ + struct plt_pci_device *pci_dev; + uint16_t nb_lf_avail; + struct dev *dev; + struct cpt *cpt; + int rc; + + if (roc_cpt == NULL || roc_cpt->pci_dev == NULL) + return -EINVAL; + + PLT_STATIC_ASSERT(sizeof(struct cpt) <= ROC_CPT_MEM_SZ); + + cpt = roc_cpt_to_cpt_priv(roc_cpt); + memset(cpt, 0, sizeof(*cpt)); + pci_dev = roc_cpt->pci_dev; + dev = &cpt->dev; + + /* Initialize device */ + rc = dev_init(dev, pci_dev); + if (rc) { + plt_err("Failed to init roc device"); + goto fail; + } + + cpt->pci_dev = pci_dev; + roc_cpt->lmt_base = dev->lmt_base; + + rc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps); + if (rc) { + plt_err("Could not determine hardware capabilities"); + goto fail; + } + + rc = cpt_available_lfs_get(&cpt->dev, &nb_lf_avail); + if (rc) { + plt_err("Could not get available lfs"); + goto fail; + } + + roc_cpt->nb_lf_avail = nb_lf_avail; + + dev->roc_cpt = roc_cpt; + + return 0; + +fail: + return rc; +} + +int +roc_cpt_dev_fini(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + + if (cpt == NULL) + return -EINVAL; + + roc_cpt->nb_lf_avail = 0; + + roc_cpt->lmt_base = 0; + + return dev_fini(&cpt->dev, cpt->pci_dev); +} + +void +roc_cpt_dev_clear(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + int i; + + if (cpt == NULL) + return; + + for (i = 0; i < roc_cpt->nb_lf; i++) + cpt->lf_msix_off[i] = 0; + + roc_cpt->nb_lf = 0; + + cpt_lfs_free(&cpt->dev); + + cpt_lfs_detach(&cpt->dev); +} + +int +roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct dev *dev = &cpt->dev; + struct cpt_eng_grp_req *req; + struct cpt_eng_grp_rsp *rsp; + int ret; + + req = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox); + if (req == NULL) + return -EIO; + + switch (eng_type) { + case CPT_ENG_TYPE_AE: + case CPT_ENG_TYPE_SE: + case CPT_ENG_TYPE_IE: + break; + default: + return -EINVAL; + } + + req->eng_type = eng_type; + ret = mbox_process_msg(dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + if (rsp->eng_grp_num > 8) { + plt_err("Invalid CPT engine group"); + return -ENOTSUP; + } + + roc_cpt->eng_grp[eng_type] = rsp->eng_grp_num; + + return rsp->eng_grp_num; +} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h new file mode 100644 index 0000000..2630955 --- /dev/null +++ b/drivers/common/cnxk/roc_cpt.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_CPT_H_ +#define _ROC_CPT_H_ + +#include "roc_api.h" + +#define ROC_CPT_MAX_LFS 64 + +struct roc_cpt { + struct plt_pci_device *pci_dev; + struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS]; + uint16_t nb_lf; + uint16_t nb_lf_avail; + uintptr_t lmt_base; + /**< CPT device capabilities */ + union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES]; + uint8_t eng_grp[CPT_MAX_ENG_TYPES]; + +#define ROC_CPT_MEM_SZ (6 * 1024) + uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; +} __plt_cache_aligned; + +int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); +int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt); +int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, + enum cpt_eng_type eng_type); +int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); +void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); +#endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h new file mode 100644 index 0000000..8cb2dbd --- /dev/null +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_CPT_PRIV_H_ +#define _ROC_CPT_PRIV_H_ + +/* Set number of number of hystbits to 6. + * This will trigger the FC writes whenever + * number of outstanding commands in the queue + * becomes multiple of 32. + */ +#define CPT_FC_NUM_HYST_BITS 6 + +struct cpt { + struct plt_pci_device *pci_dev; + struct dev dev; + uint16_t lf_msix_off[ROC_CPT_MAX_LFS]; + uint8_t lf_blkaddr[ROC_CPT_MAX_LFS]; +} __plt_cache_aligned; + +static inline struct cpt * +roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt) +{ + return (struct cpt *)&roc_cpt->reserved[0]; +} + +#endif /* _ROC_CPT_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index a39acc9..052ebe0 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -870,6 +870,8 @@ dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev) break; case PCI_DEVID_CNXK_RVU_SSO_TIM_VF: case PCI_DEVID_CNXK_RVU_NPA_VF: + case PCI_DEVID_CN10K_RVU_CPT_VF: + case PCI_DEVID_CN9K_RVU_CPT_VF: case PCI_DEVID_CNXK_RVU_AF_VF: case PCI_DEVID_CNXK_RVU_VF: case PCI_DEVID_CNXK_RVU_SDP_VF: diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h index 910cfb6..f8277fb 100644 --- a/drivers/common/cnxk/roc_dev_priv.h +++ b/drivers/common/cnxk/roc_dev_priv.h @@ -83,6 +83,7 @@ struct dev { uint16_t maxvf; struct dev_ops *ops; void *roc_nix; + void *roc_cpt; bool disable_shared_lmt; /* false(default): shared lmt mode enabled */ } __plt_cache_aligned; diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c index 3999fce..74dbdec 100644 --- a/drivers/common/cnxk/roc_platform.c +++ b/drivers/common/cnxk/roc_platform.c @@ -58,6 +58,7 @@ roc_plt_init(void) RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE); RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE); +RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE); RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE); RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE); RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE); diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 7864fa4..524585f 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -139,6 +139,7 @@ /* Log */ extern int cnxk_logtype_base; extern int cnxk_logtype_mbox; +extern int cnxk_logtype_cpt; extern int cnxk_logtype_npa; extern int cnxk_logtype_nix; extern int cnxk_logtype_npc; @@ -161,6 +162,7 @@ extern int cnxk_logtype_tm; ##args) #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) +#define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h index 5e7564c..54c28fc 100644 --- a/drivers/common/cnxk/roc_priv.h +++ b/drivers/common/cnxk/roc_priv.h @@ -32,4 +32,7 @@ /* TIM */ #include "roc_tim_priv.h" +/* CPT */ +#include "roc_cpt_priv.h" + #endif /* _ROC_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8e67c83..f8e286e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -2,6 +2,7 @@ INTERNAL { global: cnxk_logtype_base; + cnxk_logtype_cpt; cnxk_logtype_mbox; cnxk_logtype_nix; cnxk_logtype_npa; @@ -10,6 +11,11 @@ INTERNAL { cnxk_logtype_tim; cnxk_logtype_tm; roc_clk_freq_get; + roc_cpt_dev_clear; + roc_cpt_dev_configure; + roc_cpt_dev_fini; + roc_cpt_dev_init; + roc_cpt_eng_grp_add; roc_error_msg_get; roc_idev_lmt_base_addr_get; roc_idev_npa_maxpools_get; From patchwork Wed Jun 2 15:56:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93799 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D82D9A0524; Wed, 2 Jun 2021 17:57:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 46DCF410EE; Wed, 2 Jun 2021 17:57:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7803D410F2 for ; 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Wed, 02 Jun 2021 08:57:00 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:56:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:56:58 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 660463F703F; Wed, 2 Jun 2021 08:56:55 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Vidya Sagar Velumuri , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Aakash Sasidharan Date: Wed, 2 Jun 2021 21:26:17 +0530 Message-ID: <1622649385-22652-4-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wxJm6A3hQJ2jmzuGjDEn_iD-zn5fcjJr X-Proofpoint-GUID: wxJm6A3hQJ2jmzuGjDEn_iD-zn5fcjJr X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 03/11] common/cnxk: add mbox to configure RXC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add mailbox to configure tiemouts and thresholds in CPT RXC unit. Signed-off-by: Aakash Sasidharan Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 27 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 10 ++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 38 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 3c0683c..11d8b9d 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -5,6 +5,33 @@ #include "roc_api.h" #include "roc_priv.h" +int +roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct cpt_rxc_time_cfg_req *req; + struct dev *dev = &cpt->dev; + + req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox); + if (req == NULL) + return -ENOSPC; + + req->blkaddr = 0; + + /* The step value is in microseconds. */ + req->step = cfg->step; + + /* The timeout will be: limit * step microseconds */ + req->zombie_limit = cfg->zombie_limit; + req->zombie_thres = cfg->zombie_thres; + + /* The timeout will be: limit * step microseconds */ + req->active_limit = cfg->active_limit; + req->active_thres = cfg->active_thres; + + return mbox_process(dev->mbox); +} + static int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 2630955..5b84ec5 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -23,6 +23,16 @@ struct roc_cpt { uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; +struct roc_cpt_rxc_time_cfg { + uint32_t step; + uint16_t active_limit; + uint16_t active_thres; + uint16_t zombie_limit; + uint16_t zombie_thres; +}; + +int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, + struct roc_cpt_rxc_time_cfg *cfg); int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index f8e286e..1dbeebe 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,7 @@ INTERNAL { roc_cpt_dev_fini; roc_cpt_dev_init; roc_cpt_eng_grp_add; + roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_lmt_base_addr_get; roc_idev_npa_maxpools_get; From patchwork Wed Jun 2 15:56:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93800 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 213C9A0524; Wed, 2 Jun 2021 17:57:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8250C410ED; Wed, 2 Jun 2021 17:57:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0537040689 for ; Wed, 2 Jun 2021 17:57:06 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpISk019743; 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Wed, 2 Jun 2021 08:57:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:03 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 7E3183F703F; Wed, 2 Jun 2021 08:57:00 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Archana Muniganti , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph , Vidya Sagar Velumuri Date: Wed, 2 Jun 2021 21:26:18 +0530 Message-ID: <1622649385-22652-5-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 4NfAuntYdfdnZBlGc5Mp0J4zQFHbDRPK X-Proofpoint-GUID: 4NfAuntYdfdnZBlGc5Mp0J4zQFHbDRPK X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 04/11] common/cnxk: add CPT LF config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Archana Muniganti Add routines to init & fini CPT LFs. CPT LFs are queues to the hardware enabling instruction submissions. Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 262 ++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 20 +++ drivers/common/cnxk/version.map | 3 + 3 files changed, 285 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 11d8b9d..0ee3c02 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -5,6 +5,119 @@ #include "roc_api.h" #include "roc_priv.h" +#define CPT_IQ_FC_LEN 128 +#define CPT_IQ_GRP_LEN 16 + +#define CPT_IQ_NB_DESC_MULTIPLIER 40 + +/* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8). + * + * CPT requires 320 free entries (+8). And 40 entries are required for + * allowing CPT to discard packet when the queues are full (+1). + */ +#define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) \ + (PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8) + +#define CPT_IQ_GRP_SIZE(nb_desc) \ + (CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN) + +#define CPT_LF_MAX_NB_DESC 128000 +#define CPT_LF_DEFAULT_NB_DESC 1024 + +static void +cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb) +{ + /* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */ + if (enb) + plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) | + BIT_ULL(1)), + lf->rbase + CPT_LF_MISC_INT_ENA_W1S); + else + plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) | + BIT_ULL(1)), + lf->rbase + CPT_LF_MISC_INT_ENA_W1C); +} + +static void +cpt_lf_misc_irq(void *param) +{ + struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param; + struct dev *dev = lf->dev; + uint64_t intr; + + intr = plt_read64(lf->rbase + CPT_LF_MISC_INT); + if (intr == 0) + return; + + plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); + + /* Clear interrupt */ + plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); +} + +static int +cpt_lf_register_misc_irq(struct roc_cpt_lf *lf) +{ + struct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev; + struct plt_intr_handle *handle; + int rc, vec; + + handle = &pci_dev->intr_handle; + + vec = lf->msixoff + CPT_LF_INT_VEC_MISC; + /* Clear err interrupt */ + cpt_lf_misc_intr_enb_dis(lf, false); + /* Set used interrupt vectors */ + rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec); + /* Enable all dev interrupt except for RQ_DISABLED */ + cpt_lf_misc_intr_enb_dis(lf, true); + + return rc; +} + +static void +cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf) +{ + struct plt_pci_device *pci_dev = lf->roc_cpt->pci_dev; + struct plt_intr_handle *handle; + int vec; + + handle = &pci_dev->intr_handle; + + vec = lf->msixoff + CPT_LF_INT_VEC_MISC; + /* Clear err interrupt */ + cpt_lf_misc_intr_enb_dis(lf, false); + dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec); +} + +static int +cpt_lf_register_irqs(struct roc_cpt_lf *lf) +{ + int rc; + + if (lf->msixoff == MSIX_VECTOR_INVALID) { + plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x", + lf->msixoff); + return -EINVAL; + } + + /* Register lf err interrupt */ + rc = cpt_lf_register_misc_irq(lf); + if (rc) + plt_err("Error registering IRQs"); + + /* TODO */ + /* rc = cpt_lf_register_done_irq(cpt); */ + + return rc; +} + +static void +cpt_lf_unregister_irqs(struct roc_cpt_lf *lf) +{ + cpt_lf_unregister_misc_irq(lf); +} + int roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) { @@ -135,6 +248,69 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps) return 0; } +static uint32_t +cpt_lf_iq_mem_calc(uint32_t nb_desc) +{ + uint32_t len; + + /* Space for instruction group memory */ + len = CPT_IQ_GRP_SIZE(nb_desc); + + /* Align to 128B */ + len = PLT_ALIGN(len, ROC_ALIGN); + + /* Space for FC */ + len += CPT_IQ_FC_LEN; + + /* For instruction queues */ + len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER * + sizeof(struct cpt_inst_s); + + return len; +} + +static inline void +cpt_iq_init(struct roc_cpt_lf *lf) +{ + union cpt_lf_q_size lf_q_size = {.u = 0x0}; + union cpt_lf_q_base lf_q_base = {.u = 0x0}; + union cpt_lf_inprog lf_inprog; + union cpt_lf_ctl lf_ctl; + uintptr_t addr; + + lf->io_addr = lf->rbase + CPT_LF_NQX(0); + + /* Disable command queue */ + roc_cpt_iq_disable(lf); + + /* Set command queue base address */ + addr = (uintptr_t)lf->iq_vaddr + + PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN); + + lf_q_base.u = addr; + + plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE); + + /* Set command queue size */ + lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc); + plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE); + + /* Enable command queue execution */ + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + lf_inprog.s.eena = 1; + plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + + /* Enable instruction queue enqueuing */ + lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL); + lf_ctl.s.ena = 1; + lf_ctl.s.fc_ena = 1; + lf_ctl.s.fc_up_crossing = 1; + lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS; + plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); + + lf->fc_addr = (uint64_t *)addr; +} + int roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) { @@ -178,6 +354,49 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) } int +roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf) +{ + struct cpt *cpt; + void *iq_mem; + int rc; + + cpt = roc_cpt_to_cpt_priv(roc_cpt); + + if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC) + lf->nb_desc = CPT_LF_DEFAULT_NB_DESC; + + /* Allocate memory for instruction queue for CPT LF. */ + iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN); + + plt_cpt_dbg("Initializing %d CPT LF", lf->lf_id); + + lf->dev = &cpt->dev; + lf->roc_cpt = roc_cpt; + lf->msixoff = cpt->lf_msix_off[lf->lf_id]; + lf->rbase = cpt->dev.bar2 + + ((RVU_BLOCK_ADDR_CPT0 << 20) | (lf->lf_id << 12)); + lf->iq_vaddr = iq_mem; + lf->lmt_base = cpt->dev.lmt_base; + + /* Initialize instruction queue */ + cpt_iq_init(lf); + + rc = cpt_lf_register_irqs(lf); + if (rc) + goto lf_destroy; + + lf->pf_func = cpt->dev.pf_func; + + return 0; + +lf_destroy: + roc_cpt_iq_disable(lf); + plt_free(iq_mem); + + return rc; +} + +int roc_cpt_dev_init(struct roc_cpt *roc_cpt) { struct plt_pci_device *pci_dev; @@ -228,6 +447,18 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt) return rc; } +void +roc_cpt_lf_fini(struct roc_cpt_lf *lf) +{ + if (lf == NULL) + return; + + cpt_lf_unregister_irqs(lf); + + roc_cpt_iq_disable(lf); + plt_free(lf->iq_vaddr); +} + int roc_cpt_dev_fini(struct roc_cpt *roc_cpt) { @@ -298,3 +529,34 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type) return rsp->eng_grp_num; } + +void +roc_cpt_iq_disable(struct roc_cpt_lf *lf) +{ + union cpt_lf_ctl lf_ctl = {.u = 0x0}; + union cpt_lf_inprog lf_inprog; + int timeout = 20; + + /* Disable instructions enqueuing */ + plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); + + /* Wait for instruction queue to become empty */ + do { + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + if (!lf_inprog.s.inflight) + break; + + plt_delay_ms(20); + if (timeout-- < 0) { + plt_err("CPT LF %d is still busy", lf->lf_id); + break; + } + + } while (1); + + /* Disable executions in the LF's queue. + * The queue should be empty at this point + */ + lf_inprog.s.eena = 0x0; + plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); +} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 5b84ec5..abe492e 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -9,6 +9,23 @@ #define ROC_CPT_MAX_LFS 64 +struct roc_cpt_lf { + /* Input parameters */ + uint16_t lf_id; + uint32_t nb_desc; + /* End of Input parameters */ + struct plt_pci_device *pci_dev; + struct dev *dev; + struct roc_cpt *roc_cpt; + uintptr_t rbase; + uintptr_t lmt_base; + uint16_t msixoff; + uint16_t pf_func; + uint64_t *fc_addr; + uint64_t io_addr; + uint8_t *iq_vaddr; +} __plt_cache_aligned; + struct roc_cpt { struct plt_pci_device *pci_dev; struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS]; @@ -39,4 +56,7 @@ int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type); int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); +int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); +void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); +void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1dbeebe..63f5fda 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,9 @@ INTERNAL { roc_cpt_dev_fini; roc_cpt_dev_init; roc_cpt_eng_grp_add; + roc_cpt_iq_disable; + roc_cpt_lf_init; + roc_cpt_lf_fini; roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Wed Jun 2 15:56:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93801 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DFE8A0524; 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Wed, 02 Jun 2021 08:57:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:08 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id F117C3F7040; Wed, 2 Jun 2021 08:57:05 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Aakash Sasidharan , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Srujana Challa Date: Wed, 2 Jun 2021 21:26:19 +0530 Message-ID: <1622649385-22652-6-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 28-CszBA2hlHt_oW4B-bIqdk345EDUMp X-Proofpoint-GUID: 28-CszBA2hlHt_oW4B-bIqdk345EDUMp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 05/11] common/cnxk: add CPT diagnostics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Aakash Sasidharan Add routines to fetch and dump CPT statistics and states. Signed-off-by: Aakash Sasidharan Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 182 ++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 2 + drivers/common/cnxk/version.map | 2 + 3 files changed, 186 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 0ee3c02..a23e4bb 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -118,6 +118,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf) cpt_lf_unregister_misc_irq(lf); } +static void +cpt_lf_dump(struct roc_cpt_lf *lf) +{ + plt_cpt_dbg("CPT LF"); + plt_cpt_dbg("RBASE: 0x%016lx", lf->rbase); + plt_cpt_dbg("LMT_BASE: 0x%016lx", lf->lmt_base); + plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff); + plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id); + plt_cpt_dbg("NB DESC: %d", lf->nb_desc); + plt_cpt_dbg("FC_ADDR: 0x%016lx", (uintptr_t)lf->fc_addr); + plt_cpt_dbg("CQ.VADDR: 0x%016lx", (uintptr_t)lf->iq_vaddr); + + plt_cpt_dbg("CPT LF REG:"); + plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016lx", CPT_LF_CTL, + plt_read64(lf->rbase + CPT_LF_CTL)); + plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016lx", CPT_LF_INPROG, + plt_read64(lf->rbase + CPT_LF_INPROG)); + + plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016lx", CPT_LF_Q_BASE, + plt_read64(lf->rbase + CPT_LF_Q_BASE)); + plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016lx", CPT_LF_Q_SIZE, + plt_read64(lf->rbase + CPT_LF_Q_SIZE)); + plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016lx", CPT_LF_Q_INST_PTR, + plt_read64(lf->rbase + CPT_LF_Q_INST_PTR)); + plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016lx", CPT_LF_Q_GRP_PTR, + plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR)); +} + int roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg) { @@ -387,6 +415,8 @@ roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf) lf->pf_func = cpt->dev.pf_func; + cpt_lf_dump(lf); + return 0; lf_destroy: @@ -530,6 +560,158 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type) return rsp->eng_grp_num; } +static int +cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct cpt_rd_wr_reg_msg *msg; + struct dev *dev = &cpt->dev; + int ret; + + msg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox); + if (msg == NULL) + return -EIO; + + msg->hdr.pcifunc = dev->pf_func; + + msg->is_write = 0; + msg->reg_offset = reg; + msg->ret_val = val; + + ret = mbox_process_msg(dev->mbox, (void *)&msg); + if (ret) + return -EIO; + + *val = msg->val; + + return 0; +} + +static int +cpt_sts_print(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct dev *dev = &cpt->dev; + struct cpt_sts_req *req; + struct cpt_sts_rsp *rsp; + int ret; + + req = mbox_alloc_msg_cpt_sts_get(dev->mbox); + if (req == NULL) + return -EIO; + + req->blkaddr = 0; + ret = mbox_process_msg(dev->mbox, (void *)&rsp); + if (ret) + return -EIO; + + plt_print(" %s:\t0x%016lx", "inst_req_pc", rsp->inst_req_pc); + plt_print(" %s:\t0x%016lx", "inst_lat_pc", rsp->inst_lat_pc); + plt_print(" %s:\t\t0x%016lx", "rd_req_pc", rsp->rd_req_pc); + plt_print(" %s:\t\t0x%016lx", "rd_lat_pc", rsp->rd_lat_pc); + plt_print(" %s:\t\t0x%016lx", "rd_uc_pc", rsp->rd_uc_pc); + plt_print(" %s:\t0x%016lx", "active_cycles_pc", + rsp->active_cycles_pc); + plt_print(" %s:\t\t0x%016lx", "ctx_mis_pc", rsp->ctx_mis_pc); + plt_print(" %s:\t\t0x%016lx", "ctx_hit_pc", rsp->ctx_hit_pc); + plt_print(" %s:\t\t0x%016lx", "ctx_aop_pc", rsp->ctx_aop_pc); + plt_print(" %s:\t0x%016lx", "ctx_aop_lat_pc", rsp->ctx_aop_lat_pc); + plt_print(" %s:\t0x%016lx", "ctx_ifetch_pc", rsp->ctx_ifetch_pc); + plt_print(" %s:\t0x%016lx", "ctx_ifetch_lat_pc", + rsp->ctx_ifetch_lat_pc); + plt_print(" %s:\t0x%016lx", "ctx_ffetch_pc", rsp->ctx_ffetch_pc); + plt_print(" %s:\t0x%016lx", "ctx_ffetch_lat_pc", + rsp->ctx_ffetch_lat_pc); + plt_print(" %s:\t0x%016lx", "ctx_wback_pc", rsp->ctx_wback_pc); + plt_print(" %s:\t0x%016lx", "ctx_wback_lat_pc", + rsp->ctx_wback_lat_pc); + plt_print(" %s:\t\t0x%016lx", "ctx_psh_pc", rsp->ctx_psh_pc); + plt_print(" %s:\t0x%016lx", "ctx_psh_lat_pc", rsp->ctx_psh_lat_pc); + plt_print(" %s:\t\t0x%016lx", "ctx_err", rsp->ctx_err); + plt_print(" %s:\t\t0x%016lx", "ctx_enc_id", rsp->ctx_enc_id); + plt_print(" %s:\t0x%016lx", "ctx_flush_timer", rsp->ctx_flush_timer); + plt_print(" %s:\t\t0x%016lx", "rxc_time", rsp->rxc_time); + plt_print(" %s:\t0x%016lx", "rxc_time_cfg", rsp->rxc_time_cfg); + plt_print(" %s:\t0x%016lx", "rxc_active_sts", rsp->rxc_active_sts); + plt_print(" %s:\t0x%016lx", "rxc_zombie_sts", rsp->rxc_zombie_sts); + plt_print(" %s:\t0x%016lx", "rxc_dfrg", rsp->rxc_dfrg); + plt_print(" %s:\t0x%016lx", "x2p_link_cfg0", rsp->x2p_link_cfg0); + plt_print(" %s:\t0x%016lx", "x2p_link_cfg1", rsp->x2p_link_cfg1); + plt_print(" %s:\t0x%016lx", "busy_sts_ae", rsp->busy_sts_ae); + plt_print(" %s:\t0x%016lx", "free_sts_ae", rsp->free_sts_ae); + plt_print(" %s:\t0x%016lx", "busy_sts_se", rsp->busy_sts_se); + plt_print(" %s:\t0x%016lx", "free_sts_se", rsp->free_sts_se); + plt_print(" %s:\t0x%016lx", "busy_sts_ie", rsp->busy_sts_ie); + plt_print(" %s:\t0x%016lx", "free_sts_ie", rsp->free_sts_ie); + plt_print(" %s:\t0x%016lx", "exe_err_info", rsp->exe_err_info); + plt_print(" %s:\t\t0x%016lx", "cptclk_cnt", rsp->cptclk_cnt); + plt_print(" %s:\t\t0x%016lx", "diag", rsp->diag); + + return 0; +} + +int +roc_cpt_afs_print(struct roc_cpt *roc_cpt) +{ + uint64_t reg_val; + + plt_print("CPT AF registers:"); + + if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), ®_val)) + return -EIO; + + plt_print(" CPT_AF_LF0_CTL:\t0x%016lx", reg_val); + + if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), ®_val)) + return -EIO; + + plt_print(" CPT_AF_LF0_CTL2:\t0x%016lx", reg_val); + + cpt_sts_print(roc_cpt); + + return 0; +} + +static void +cpt_lf_print(struct roc_cpt_lf *lf) +{ + uint64_t reg_val; + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); + plt_print(" Encrypted byte count:\t%ld", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + plt_print(" Encrypted packet count:\t%ld", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT); + plt_print(" Decrypted byte count:\t%ld", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + plt_print(" Decrypted packet count:\t%ld", reg_val); +} + +int +roc_cpt_lfs_print(struct roc_cpt *roc_cpt) +{ + struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); + struct roc_cpt_lf *lf; + int lf_id; + + if (cpt == NULL) + return -EINVAL; + + for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) { + lf = roc_cpt->lf[lf_id]; + if (lf == NULL) + continue; + + plt_print("Count registers for CPT LF%d:", lf_id); + cpt_lf_print(lf); + } + + return 0; +} + void roc_cpt_iq_disable(struct roc_cpt_lf *lf) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index abe492e..692fa79 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -58,5 +58,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); +int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); +int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 63f5fda..4f28f64 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -11,6 +11,7 @@ INTERNAL { cnxk_logtype_tim; cnxk_logtype_tm; roc_clk_freq_get; + roc_cpt_afs_print; roc_cpt_dev_clear; roc_cpt_dev_configure; roc_cpt_dev_fini; @@ -19,6 +20,7 @@ INTERNAL { roc_cpt_iq_disable; roc_cpt_lf_init; roc_cpt_lf_fini; + roc_cpt_lfs_print; roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Wed Jun 2 15:56:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93802 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B8D4A0524; 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Wed, 02 Jun 2021 08:57:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:14 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id B45EA3F7041; Wed, 2 Jun 2021 08:57:10 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Aakash Sasidharan , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Vidya Sagar Velumuri Date: Wed, 2 Jun 2021 21:26:20 +0530 Message-ID: <1622649385-22652-7-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 4DPpDXtCZ4MiXh05LTMl51OG5U41E2wx X-Proofpoint-GUID: 4DPpDXtCZ4MiXh05LTMl51OG5U41E2wx X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 06/11] common/cnxk: add CPT LF flush X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Aakash Sasidharan Add routine to flush context from CPT context processor cache. Signed-off-by: Aakash Sasidharan Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_cpt.c | 18 ++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 1 + drivers/common/cnxk/version.map | 1 + 3 files changed, 20 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index a23e4bb..d95b94c 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -477,6 +477,24 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt) return rc; } +int +roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr) +{ + union cpt_lf_ctx_flush reg; + + if (lf == NULL) + return -ENOTSUP; + + reg.u = 0; + reg.s.pf_func = lf->pf_func; + reg.s.inval = 1; + reg.s.cptr = cptr; + + plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH); + + return 0; +} + void roc_cpt_lf_fini(struct roc_cpt_lf *lf) { diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 692fa79..2b43a5a 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -58,6 +58,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf); void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); +int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 4f28f64..ad559a4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -18,6 +18,7 @@ INTERNAL { roc_cpt_dev_init; roc_cpt_eng_grp_add; roc_cpt_iq_disable; + roc_cpt_lf_ctx_flush; roc_cpt_lf_init; roc_cpt_lf_fini; roc_cpt_lfs_print; From patchwork Wed Jun 2 15:56:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93803 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0EA2A0524; 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Wed, 02 Jun 2021 08:57:20 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:18 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 7E69D3F7051; Wed, 2 Jun 2021 08:57:15 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph , Vidya Sagar Velumuri Date: Wed, 2 Jun 2021 21:26:21 +0530 Message-ID: <1622649385-22652-8-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xJO_jvjcsF8kWQfIbdyjASOuEFzm_dfk X-Proofpoint-GUID: xJO_jvjcsF8kWQfIbdyjASOuEFzm_dfk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 07/11] common/cnxk: add SE microcode defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda Microcode SE opcodes support symmetric operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_api.h | 3 + drivers/common/cnxk/roc_se.h | 287 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 290 insertions(+) create mode 100644 drivers/common/cnxk/roc_se.h diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 88a5611..6511614 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -109,4 +109,7 @@ /* CPT */ #include "roc_cpt.h" +/* CPT microcode */ +#include "roc_se.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h new file mode 100644 index 0000000..165468a --- /dev/null +++ b/drivers/common/cnxk/roc_se.h @@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_SE_H__ +#define __ROC_SE_H__ + +/* SE opcodes */ +#define ROC_SE_MAJOR_OP_FC 0x33 +#define ROC_SE_FC_MINOR_OP_ENCRYPT 0x0 +#define ROC_SE_FC_MINOR_OP_DECRYPT 0x1 +#define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10 + +#define ROC_SE_MAJOR_OP_HASH 0x34 +#define ROC_SE_MAJOR_OP_HMAC 0x35 +#define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37 +#define ROC_SE_MAJOR_OP_KASUMI 0x38 +#define ROC_SE_MAJOR_OP_MISC 0x01 + +#define ROC_SE_MAX_AAD_SIZE 64 +#define ROC_SE_MAX_MAC_LEN 64 + +#define ROC_SE_OFF_CTRL_LEN 8 +#define ROC_SE_DMA_MODE (1 << 7) + +#define ROC_SE_MAX_SG_IN_OUT_CNT 32 +#define ROC_SE_MAX_SG_CNT (ROC_SE_MAX_SG_IN_OUT_CNT / 2) + +#define ROC_SE_SG_LIST_HDR_SIZE (8u) +#define ROC_SE_SG_ENTRY_SIZE sizeof(struct roc_se_sglist_comp) + +#define ROC_SE_ZS_EA 0x1 +#define ROC_SE_ZS_IA 0x2 +#define ROC_SE_K_F8 0x4 +#define ROC_SE_K_F9 0x8 + +#define ROC_SE_FC_GEN 0x1 +#define ROC_SE_PDCP 0x2 +#define ROC_SE_KASUMI 0x3 +#define ROC_SE_HASH_HMAC 0x4 + +#define ROC_SE_OP_CIPHER_ENCRYPT 0x1 +#define ROC_SE_OP_CIPHER_DECRYPT 0x2 +#define ROC_SE_OP_CIPHER_MASK \ + (ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_CIPHER_DECRYPT) + +#define ROC_SE_OP_AUTH_VERIFY 0x4 +#define ROC_SE_OP_AUTH_GENERATE 0x8 +#define ROC_SE_OP_AUTH_MASK \ + (ROC_SE_OP_AUTH_VERIFY | ROC_SE_OP_AUTH_GENERATE) + +#define ROC_SE_OP_ENCODE (ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_AUTH_GENERATE) +#define ROC_SE_OP_DECODE (ROC_SE_OP_CIPHER_DECRYPT | ROC_SE_OP_AUTH_VERIFY) + +#define ROC_SE_ALWAYS_USE_SEPARATE_BUF + +/* + * Parameters for Flexi Crypto + * requests + */ +#define ROC_SE_VALID_AAD_BUF 0x01 +#define ROC_SE_VALID_MAC_BUF 0x02 +#define ROC_SE_VALID_IV_BUF 0x04 +#define ROC_SE_SINGLE_BUF_INPLACE 0x08 +#define ROC_SE_SINGLE_BUF_HEADROOM 0x10 + +#define ROC_SE_ENCR_IV_OFFSET(__d_offs) (((__d_offs) >> 32) & 0xffff) +#define ROC_SE_ENCR_OFFSET(__d_offs) (((__d_offs) >> 16) & 0xffff) +#define ROC_SE_AUTH_OFFSET(__d_offs) ((__d_offs) & 0xffff) +#define ROC_SE_ENCR_DLEN(__d_lens) ((__d_lens) >> 32) +#define ROC_SE_AUTH_DLEN(__d_lens) ((__d_lens) & 0xffffffff) + +/* Salt length for AES-CTR/GCM/CCM and AES-GMAC */ +#define ROC_SALT_LEN 4 + +/* Key lengths */ +#define ROC_DES3_KEY_LEN 24 +#define ROC_AES128_KEY_LEN 16 +#define ROC_AES192_KEY_LEN 24 +#define ROC_AES256_KEY_LEN 32 + +#define ROC_AH_HDR_LEN 12 + +#define ROC_MD5_KEY_LENGTH 16 +#define ROC_SHA1_KEY_LENGTH 20 +#define ROC_SHA256_KEY_LENGTH 32 +#define ROC_SHA384_KEY_LENGTH 48 +#define ROC_SHA512_KEY_LENGTH 64 + +#define ROC_DES_BLOCK_LENGTH 8 +#define ROC_AES_BLOCK_LENGTH 16 + +typedef enum { ROC_SE_FROM_CTX = 0, ROC_SE_FROM_DPTR = 1 } roc_se_input_type; + +typedef enum { + ROC_SE_MD5_TYPE = 1, + ROC_SE_SHA1_TYPE = 2, + ROC_SE_SHA2_SHA224 = 3, + ROC_SE_SHA2_SHA256 = 4, + ROC_SE_SHA2_SHA384 = 5, + ROC_SE_SHA2_SHA512 = 6, + ROC_SE_GMAC_TYPE = 7, + ROC_SE_POLY1305 = 8, + ROC_SE_SHA3_SHA224 = 10, + ROC_SE_SHA3_SHA256 = 11, + ROC_SE_SHA3_SHA384 = 12, + ROC_SE_SHA3_SHA512 = 13, + ROC_SE_SHA3_SHAKE256 = 14, + ROC_SE_SHA3_SHAKE512 = 15, + + /* These are only for software use */ + ROC_SE_ZUC_EIA3 = 0x90, + ROC_SE_SNOW3G_UIA2 = 0x91, + ROC_SE_AES_CMAC_EIA2 = 0x92, + ROC_SE_KASUMI_F9_CBC = 0x93, + ROC_SE_KASUMI_F9_ECB = 0x94, +} roc_se_auth_type; + +typedef enum { + /* To support passthrough */ + ROC_SE_PASSTHROUGH = 0x0, + /* + * These are defined by MC for Flexi crypto + * for field of 4 bits + */ + ROC_SE_DES3_CBC = 0x1, + ROC_SE_DES3_ECB = 0x2, + ROC_SE_AES_CBC = 0x3, + ROC_SE_AES_ECB = 0x4, + ROC_SE_AES_CFB = 0x5, + ROC_SE_AES_CTR = 0x6, + ROC_SE_AES_GCM = 0x7, + ROC_SE_AES_XTS = 0x8, + ROC_SE_CHACHA20 = 0x9, + + /* These are only for software use */ + ROC_SE_ZUC_EEA3 = 0x90, + ROC_SE_SNOW3G_UEA2 = 0x91, + ROC_SE_AES_CTR_EEA2 = 0x92, + ROC_SE_KASUMI_F8_CBC = 0x93, + ROC_SE_KASUMI_F8_ECB = 0x94, +} roc_se_cipher_type; + +typedef enum { + /* Microcode errors */ + ROC_SE_NO_ERR = 0x00, + ROC_SE_ERR_OPCODE_UNSUPPORTED = 0x01, + + /* SCATTER GATHER */ + ROC_SE_ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02, + ROC_SE_ERR_SCATTER_GATHER_LIST = 0x03, + ROC_SE_ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04, + + /* SE GC */ + ROC_SE_ERR_GC_LENGTH_INVALID = 0x41, + ROC_SE_ERR_GC_RANDOM_LEN_INVALID = 0x42, + ROC_SE_ERR_GC_DATA_LEN_INVALID = 0x43, + ROC_SE_ERR_GC_DRBG_TYPE_INVALID = 0x44, + ROC_SE_ERR_GC_CTX_LEN_INVALID = 0x45, + ROC_SE_ERR_GC_CIPHER_UNSUPPORTED = 0x46, + ROC_SE_ERR_GC_AUTH_UNSUPPORTED = 0x47, + ROC_SE_ERR_GC_OFFSET_INVALID = 0x48, + ROC_SE_ERR_GC_HASH_MODE_UNSUPPORTED = 0x49, + ROC_SE_ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a, + ROC_SE_ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b, + ROC_SE_ERR_GC_ICV_MISCOMPARE = 0x4c, + ROC_SE_ERR_GC_DATA_UNALIGNED = 0x4d, + + /* API Layer */ + ROC_SE_ERR_REQ_PENDING = 0xfe, + ROC_SE_ERR_REQ_TIMEOUT = 0xff, + +} roc_se_error_code; + +typedef enum { + ROC_SE_AES_128_BIT = 0x1, + ROC_SE_AES_192_BIT = 0x2, + ROC_SE_AES_256_BIT = 0x3 +} roc_se_aes_type; + +struct roc_se_sglist_comp { + union { + uint64_t len; + struct { + uint16_t len[4]; + } s; + } u; + uint64_t ptr[4]; +}; + +struct roc_se_enc_context { + uint64_t iv_source : 1; + uint64_t aes_key : 2; + uint64_t rsvd_60 : 1; + uint64_t enc_cipher : 4; + uint64_t auth_input_type : 1; + uint64_t rsvd_52_54 : 3; + uint64_t hash_type : 4; + uint64_t mac_len : 8; + uint64_t rsvd_39_0 : 40; + uint8_t encr_key[32]; + uint8_t encr_iv[16]; +}; + +struct roc_se_hmac_context { + uint8_t ipad[64]; + uint8_t opad[64]; +}; + +struct roc_se_context { + struct roc_se_enc_context enc; + struct roc_se_hmac_context hmac; +}; + +struct roc_se_zuc_snow3g_ctx { + uint8_t encr_auth_iv[16]; + uint8_t ci_key[16]; + uint8_t zuc_const[32]; +}; + +struct roc_se_kasumi_ctx { + uint8_t reg_A[8]; + uint8_t ci_key[16]; +}; + +/* Buffer pointer */ +struct roc_se_buf_ptr { + void *vaddr; + uint32_t size; + uint32_t resv; +}; + +/* IOV Pointer */ +struct roc_se_iov_ptr { + int buf_cnt; + struct roc_se_buf_ptr bufs[0]; +}; + +struct roc_se_fc_params { + /* 0th cache line */ + union { + struct roc_se_buf_ptr bufs[1]; + struct { + struct roc_se_iov_ptr *src_iov; + struct roc_se_iov_ptr *dst_iov; + }; + }; + void *iv_buf; + void *auth_iv_buf; + struct roc_se_buf_ptr meta_buf; + struct roc_se_buf_ptr ctx_buf; + uint64_t rsvd2; + + /* 1st cache line */ + struct roc_se_buf_ptr aad_buf __plt_cache_aligned; + struct roc_se_buf_ptr mac_buf; +}; + +PLT_STATIC_ASSERT((offsetof(struct roc_se_fc_params, aad_buf) % 128) == 0); + +#define ROC_SE_PDCP_ALG_TYPE_ZUC 0 +#define ROC_SE_PDCP_ALG_TYPE_SNOW3G 1 +#define ROC_SE_PDCP_ALG_TYPE_AES_CTR 2 + +struct roc_se_ctx { + /* Below fields are accessed by sw */ + uint64_t enc_cipher : 8; + uint64_t hash_type : 8; + uint64_t mac_len : 8; + uint64_t auth_key_len : 8; + uint64_t fc_type : 4; + uint64_t hmac : 1; + uint64_t zsk_flags : 3; + uint64_t k_ecb : 1; + uint64_t pdcp_alg_type : 2; + uint64_t rsvd : 21; + union cpt_inst_w4 template_w4; + /* Below fields are accessed by hardware */ + union { + struct roc_se_context fctx; + struct roc_se_zuc_snow3g_ctx zs_ctx; + struct roc_se_kasumi_ctx k_ctx; + } se_ctx; + uint8_t auth_key[1024]; +}; + +#endif /* __ROC_SE_H__ */ From patchwork Wed Jun 2 15:56:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93804 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D12ACA0524; Wed, 2 Jun 2021 17:57:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D277740FDF; Wed, 2 Jun 2021 17:57:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0A30B410E5 for ; Wed, 2 Jun 2021 17:57:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpLdg019794; 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Wed, 2 Jun 2021 08:57:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:23 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id A512C3F703F; Wed, 2 Jun 2021 08:57:20 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Srujana Challa , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:22 +0530 Message-ID: <1622649385-22652-9-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YmLpha2PF9lZVte71csXRhlD6K59GmwF X-Proofpoint-GUID: YmLpha2PF9lZVte71csXRhlD6K59GmwF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 08/11] common/cnxk: add IE microcode defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Microcode IE opcodes support IPsec operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph Signed-off-by: Srujana Challa Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/roc_api.h | 2 + drivers/common/cnxk/roc_ie.h | 19 ++ drivers/common/cnxk/roc_ie_on.h | 18 ++ drivers/common/cnxk/roc_ie_ot.h | 588 +++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_platform.h | 1 + 5 files changed, 628 insertions(+) create mode 100644 drivers/common/cnxk/roc_ie.h create mode 100644 drivers/common/cnxk/roc_ie_on.h create mode 100644 drivers/common/cnxk/roc_ie_ot.h diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 6511614..d545bb9 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -110,6 +110,8 @@ #include "roc_cpt.h" /* CPT microcode */ +#include "roc_ie_on.h" +#include "roc_ie_ot.h" #include "roc_se.h" #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_ie.h b/drivers/common/cnxk/roc_ie.h new file mode 100644 index 0000000..a330ea1 --- /dev/null +++ b/drivers/common/cnxk/roc_ie.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_IE_H__ +#define __ROC_IE_H__ + +/* CNXK IPSEC helper macros */ +#define ROC_IE_AH_HDR_LEN 12 +#define ROC_IE_AES_GCM_IV_LEN 8 +#define ROC_IE_AES_GCM_MAC_LEN 16 +#define ROC_IE_AES_CBC_IV_LEN 16 +#define ROC_IE_SHA1_HMAC_LEN 12 +#define ROC_IE_AUTH_KEY_LEN_MAX 64 + +#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4 +#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16 + +#endif /* __ROC_IE_H__ */ diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h new file mode 100644 index 0000000..72ea037 --- /dev/null +++ b/drivers/common/cnxk/roc_ie_on.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_IE_ON_H__ +#define __ROC_IE_ON_H__ + +/* CN9K IPSEC LA opcodes */ +#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_OUTBOUND 0x20 +#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_INBOUND 0x21 +#define ROC_IE_ONL_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23 +#define ROC_IE_ONL_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24 + +/* CN9K IPSEC FP opcodes */ +#define ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x25 +#define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x26 + +#endif /* __ROC_IE_ON_H__ */ diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h new file mode 100644 index 0000000..1b382de --- /dev/null +++ b/drivers/common/cnxk/roc_ie_ot.h @@ -0,0 +1,588 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_IE_OT_H__ +#define __ROC_IE_OT_H__ + +/* CN10K IPSEC opcodes */ +#define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28 +#define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29 + +enum roc_ie_ot_ucc_ipsec { + ROC_IE_OT_UCC_SUCCESS = 0x00, + ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM = 0x02, + ROC_IE_OT_UCC_ERR_SA_INVAL = 0x03, + ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM = 0x04, + ROC_IE_OT_UCC_ERR_SA_EXPIRED = 0x05, + ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM = 0x06, + ROC_IE_OT_UCC_ERR_SA_OVERFLOW = 0x07, + ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM = 0x08, + ROC_IE_OT_UCC_ERR_SA_ESP_BAD_ALGO = 0x09, + ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0x0a, + ROC_IE_OT_UCC_ERR_SA_ESP_BAD_KEYS = 0x0b, + ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0x0c, + ROC_IE_OT_UCC_ERR_SA_AH_BAD_ALGO = 0x0d, + ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN = 0x0e, + ROC_IE_OT_UCC_ERR_SA_AH_BAD_KEYS = 0x0f, + ROC_IE_OT_UCC_ERR_SA_BAD_IP = 0x11, + ROC_IE_OT_UCC_ERR_SA_BAD_CTX = 0x13, + ROC_IE_OT_UCC_ERR_AOP_IPSEC = 0x17, + ROC_IE_OT_UCC_ERR_PKT_IP = 0x23, + ROC_IE_OT_UCC_ERR_PKT_IP6_BAD_EXT = 0x25, + ROC_IE_OT_UCC_ERR_PKT_IP6_HBH = 0x27, + ROC_IE_OT_UCC_ERR_PKT_IP6_BIGEXT = 0x29, + ROC_IE_OT_UCC_ERR_PKT_IP_FRAG = 0x2b, + ROC_IE_OT_UCC_ERR_PKT_IP_ULP = 0x2d, + ROC_IE_OT_UCC_ERR_PKT_SA_MISMATCH = 0x2f, + ROC_IE_OT_UCC_ERR_PKT_SPI_MISMATCH = 0x31, + ROC_IE_OT_UCC_ERR_PKT_ESP_BADPAD = 0x33, + ROC_IE_OT_UCC_ERR_PKT_BADICV = 0x35, + ROC_IE_OT_UCC_ERR_PKT_REPLAY_SEQ = 0x37, + ROC_IE_OT_UCC_ERR_PKT_REPLAY_WINDOW = 0x39, + ROC_IE_OT_UCC_ERR_PKT_BADNH = 0x3b, + ROC_IE_OT_UCC_ERR_PKT_SA_PORT_MISMATCH = 0x3d, +}; + +enum { + ROC_IE_OT_SA_AR_WIN_DISABLED = 0, + ROC_IE_OT_SA_AR_WIN_64 = 1, + ROC_IE_OT_SA_AR_WIN_128 = 2, + ROC_IE_OT_SA_AR_WIN_256 = 3, + ROC_IE_OT_SA_AR_WIN_512 = 4, + ROC_IE_OT_SA_AR_WIN_1024 = 5, + ROC_IE_OT_SA_AR_WIN_2048 = 6, + ROC_IE_OT_SA_AR_WIN_4096 = 7, +}; + +enum { + ROC_IE_OT_SA_PKT_FMT_FULL = 0, + ROC_IE_OT_SA_PKT_FMT_META = 1, +}; + +enum { + ROC_IE_OT_SA_PKT_OUTPUT_DECRYPTED = 0, + ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG = 1, + ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG = 2, + ROC_IE_OT_SA_PKT_OUTPUT_UCODE_BASED_DEFRAG = 3, +}; + +enum { + ROC_IE_OT_SA_DEFRAG_ALL = 0, + ROC_IE_OT_SA_DEFRAG_IN_ORDER = 1, + ROC_IE_OT_SA_DEFRAG_IN_REV_ORDER = 2, +}; + +enum { + ROC_IE_OT_SA_IV_SRC_DEFAULT = 0, + ROC_IE_OT_SA_IV_SRC_ENC_CTR = 1, + ROC_IE_OT_SA_IV_SRC_FROM_SA = 2, +}; + +enum { + ROC_IE_OT_SA_COPY_FROM_SA = 0, + ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR = 1, +}; + +enum { + ROC_IE_OT_SA_DIR_INBOUND = 0, + ROC_IE_OT_SA_DIR_OUTBOUND = 1, +}; + +enum { + ROC_IE_OT_SA_IP_VERSION_4 = 0, + ROC_IE_OT_SA_IP_VERSION_6 = 1, +}; + +enum { + ROC_IE_OT_SA_MODE_TRANSPORT = 0, + ROC_IE_OT_SA_MODE_TUNNEL = 1, +}; + +enum { + ROC_IE_OT_SA_PROTOCOL_AH = 0, + ROC_IE_OT_SA_PROTOCOL_ESP = 1, +}; + +enum { + ROC_IE_OT_SA_AES_KEY_LEN_128 = 1, + ROC_IE_OT_SA_AES_KEY_LEN_192 = 2, + ROC_IE_OT_SA_AES_KEY_LEN_256 = 3, +}; + +enum { + ROC_IE_OT_SA_ENC_NULL = 0, + ROC_IE_OT_SA_ENC_3DES_CBC = 2, + ROC_IE_OT_SA_ENC_AES_CBC = 3, + ROC_IE_OT_SA_ENC_AES_CTR = 4, + ROC_IE_OT_SA_ENC_AES_GCM = 5, + ROC_IE_OT_SA_ENC_AES_CCM = 6, +}; + +enum { + ROC_IE_OT_SA_AUTH_NULL = 0, + ROC_IE_OT_SA_AUTH_SHA1 = 2, + ROC_IE_OT_SA_AUTH_SHA2_256 = 4, + ROC_IE_OT_SA_AUTH_SHA2_384 = 5, + ROC_IE_OT_SA_AUTH_SHA2_512 = 6, + ROC_IE_OT_SA_AUTH_AES_GMAC = 7, + ROC_IE_OT_SA_AUTH_AES_XCBC_128 = 8, +}; + +enum { + ROC_IE_OT_SA_ENCAP_NONE = 0, + ROC_IE_OT_SA_ENCAP_UDP = 1, + ROC_IE_OT_SA_ENCAP_TCP = 2, +}; + +enum { + ROC_IE_OT_SA_LIFE_UNIT_OCTETS = 0, + ROC_IE_OT_SA_LIFE_UNIT_PKTS = 1, +}; + +enum { + ROC_IE_OT_SA_IP_HDR_VERIFY_DISABLED = 0, + ROC_IE_OT_SA_IP_HDR_VERIFY_DST_ADDR = 1, + ROC_IE_OT_SA_IP_HDR_VERIFY_SRC_DST_ADDR = 2, +}; + +enum { + ROC_IE_OT_REAS_STS_SUCCESS = 0, + ROC_IE_OT_REAS_STS_TIMEOUT = 1, + ROC_IE_OT_REAS_STS_EVICT = 2, + ROC_IE_OT_REAS_STS_BAD_ORDER = 3, + ROC_IE_OT_REAS_STS_TOO_MANY = 4, + ROC_IE_OT_REAS_STS_HSH_EVICT = 5, + ROC_IE_OT_REAS_STS_OVERLAP = 6, + ROC_IE_OT_REAS_STS_ZOMBIE = 7, + ROC_IE_OT_REAS_STS_L3P_ERR = 8, + ROC_IE_OT_REAS_STS_MAX = 9 +}; +/* Context units in bytes */ +#define ROC_CTX_UNIT_8B 8 +#define ROC_CTX_UNIT_128B 128 +#define ROC_CTX_MAX_CKEY_LEN 32 +#define ROC_CTX_MAX_OPAD_IPAD_LEN 128 + +/* Anti reply window size supported */ +#define ROC_AR_WIN_SIZE_MIN 64 +#define ROC_AR_WIN_SIZE_MAX 4096 +#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5 + +/* u64 array size to fit anti replay window bits */ +#define ROC_AR_WINBITS_SZ \ + (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \ + BITS_PER_LONG_LONG) + +/* Common bit fields between inbound and outbound SA */ +union roc_ot_ipsec_sa_word2 { + struct { + uint64_t valid : 1; + uint64_t dir : 1; + uint64_t outer_ip_ver : 1; + uint64_t rsvd0 : 1; + uint64_t mode : 1; + uint64_t protocol : 1; + uint64_t aes_key_len : 2; + + uint64_t enc_type : 3; + uint64_t life_unit : 1; + uint64_t auth_type : 4; + + uint64_t encap_type : 2; + uint64_t rsvd1 : 6; + + uint64_t rsvd2 : 7; + uint64_t async_mode : 1; + + uint64_t spi : 32; + } s; + uint64_t u64; +}; + +PLT_STATIC_ASSERT(sizeof(union roc_ot_ipsec_sa_word2) == 1 * sizeof(uint64_t)); + +union roc_ot_ipsec_outer_ip_hdr { + struct { + uint32_t dst_addr; + uint32_t src_addr; + } ipv4; + struct { + uint8_t src_addr[16]; + uint8_t dst_addr[16]; + } ipv6; +}; + +struct roc_ot_ipsec_inb_ctx_update_reg { + uint64_t ar_base; + uint64_t ar_valid_mask; + uint64_t hard_life; + uint64_t soft_life; + uint64_t mib_octs; + uint64_t mib_pkts; + uint64_t ar_winbits[ROC_AR_WINBITS_SZ]; +}; + +union roc_ot_ipsec_outb_iv { + uint64_t u64[2]; + uint8_t iv_dbg[16]; + struct { + uint8_t iv_dbg1[4]; + uint8_t salt[4]; + + uint32_t rsvd; + uint8_t iv_dbg2[4]; + } s; +}; + +struct roc_ot_ipsec_outb_ctx_update_reg { + uint64_t rsvd; + uint64_t esn_val; + uint64_t hard_life; + uint64_t soft_life; + uint64_t mib_octs; + uint64_t mib_pkts; +}; + +struct roc_ot_ipsec_inb_sa { + /* Word0 */ + union { + struct { + uint64_t ar_win : 3; + uint64_t hard_life_dec : 1; + uint64_t soft_life_dec : 1; + uint64_t count_glb_octets : 1; + uint64_t count_glb_pkts : 1; + uint64_t count_mib_bytes : 1; + + uint64_t count_mib_pkts : 1; + uint64_t hw_ctx_off : 7; + + uint64_t ctx_id : 16; + + uint64_t orig_pkt_fabs : 1; + uint64_t orig_pkt_free : 1; + uint64_t pkind : 6; + + uint64_t rsvd0 : 1; + uint64_t et_ovrwr : 1; + uint64_t pkt_output : 2; + uint64_t pkt_format : 1; + uint64_t defrag_opt : 2; + uint64_t x2p_dst : 1; + + uint64_t ctx_push_size : 7; + uint64_t rsvd1 : 1; + + uint64_t ctx_hdr_size : 2; + uint64_t aop_valid : 1; + uint64_t rsvd2 : 1; + uint64_t ctx_size : 4; + } s; + uint64_t u64; + } w0; + + /* Word1 */ + union { + struct { + uint64_t orig_pkt_aura : 20; + uint64_t rsvd3 : 4; + uint64_t orig_pkt_foff : 8; + uint64_t cookie : 32; + } s; + uint64_t u64; + } w1; + + /* Word 2 */ + union { + struct { + uint64_t valid : 1; + uint64_t dir : 1; + uint64_t outer_ip_ver : 1; + uint64_t rsvd4 : 1; + uint64_t ipsec_mode : 1; + uint64_t ipsec_protocol : 1; + uint64_t aes_key_len : 2; + + uint64_t enc_type : 3; + uint64_t life_unit : 1; + uint64_t auth_type : 4; + + uint64_t encap_type : 2; + uint64_t et_ovrwr_ddr_en : 1; + uint64_t esn_en : 1; + uint64_t tport_l4_incr_csum : 1; + uint64_t ip_hdr_verify : 2; + uint64_t rsvd5 : 1; + + uint64_t rsvd6 : 7; + uint64_t async_mode : 1; + + uint64_t spi : 32; + } s; + uint64_t u64; + } w2; + + /* Word3 */ + uint64_t rsvd7; + + /* Word4 - Word7 */ + uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN]; + + /* Word8 - Word9 */ + union { + struct { + uint32_t rsvd8; + uint8_t salt[4]; + } s; + uint64_t u64; + } w8; + uint64_t rsvd9; + + /* Word10 */ + union { + struct { + uint64_t rsvd10 : 32; + uint64_t udp_src_port : 16; + uint64_t udp_dst_port : 16; + } s; + uint64_t u64; + } w10; + + /* Word11 - Word14 */ + union roc_ot_ipsec_outer_ip_hdr outer_hdr; + + /* Word15 - Word30 */ + uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN]; + + /* Word31 - Word100 */ + struct roc_ot_ipsec_inb_ctx_update_reg ctx; +}; + +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w1) == + 1 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w2) == + 2 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, cipher_key) == + 4 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w8) == + 8 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w10) == + 10 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, outer_hdr) == + 11 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, hmac_opad_ipad) == + 15 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, ctx) == + 31 * sizeof(uint64_t)); + +struct roc_ot_ipsec_outb_sa { + /* Word0 */ + union { + struct { + uint64_t esn_en : 1; + uint64_t ip_id : 1; + uint64_t rsvd0 : 1; + uint64_t hard_life_dec : 1; + uint64_t soft_life_dec : 1; + uint64_t count_glb_octets : 1; + uint64_t count_glb_pkts : 1; + uint64_t count_mib_bytes : 1; + + uint64_t count_mib_pkts : 1; + uint64_t hw_ctx_off : 7; + + uint64_t rsvd1 : 32; + + uint64_t ctx_push_size : 7; + uint64_t rsvd2 : 1; + + uint64_t ctx_hdr_size : 2; + uint64_t aop_valid : 1; + uint64_t rsvd3 : 1; + uint64_t ctx_size : 4; + } s; + uint64_t u64; + } w0; + + /* Word1 */ + union { + struct { + uint64_t rsvd4 : 32; + uint64_t cookie : 32; + } s; + uint64_t u64; + } w1; + + /* Word 2 */ + union { + struct { + uint64_t valid : 1; + uint64_t dir : 1; + uint64_t outer_ip_ver : 1; + uint64_t rsvd5 : 1; + uint64_t ipsec_mode : 1; + uint64_t ipsec_protocol : 1; + uint64_t aes_key_len : 2; + + uint64_t enc_type : 3; + uint64_t life_unit : 1; + uint64_t auth_type : 4; + + uint64_t encap_type : 2; + uint64_t ipv4_df_src_or_ipv6_flw_lbl_src : 1; + uint64_t dscp_src : 1; + uint64_t iv_src : 2; + uint64_t ipid_gen : 1; + uint64_t rsvd6 : 1; + + uint64_t rsvd7 : 7; + uint64_t async_mode : 1; + + uint64_t spi : 32; + } s; + uint64_t u64; + } w2; + + /* Word3 */ + uint64_t rsvd8; + + /* Word4 - Word7 */ + uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN]; + + /* Word8 - Word9 */ + union roc_ot_ipsec_outb_iv iv; + + /* Word10 */ + union { + struct { + uint64_t rsvd9 : 4; + uint64_t ipv4_df_or_ipv6_flw_lbl : 20; + + uint64_t dscp : 6; + uint64_t rsvd10 : 2; + + uint64_t udp_dst_port : 16; + + uint64_t udp_src_port : 16; + } s; + uint64_t u64; + } w10; + + /* Word11 - Word14 */ + union roc_ot_ipsec_outer_ip_hdr outer_hdr; + + /* Word15 - Word30 */ + uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN]; + + /* Word31 - Word36 */ + struct roc_ot_ipsec_outb_ctx_update_reg ctx; +}; + +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w1) == + 1 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w2) == + 2 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, cipher_key) == + 4 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, iv) == + 8 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w10) == + 10 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, outer_hdr) == + 11 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) == + 15 * sizeof(uint64_t)); +PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) == + 31 * sizeof(uint64_t)); + +struct roc_ot_cpt_parse_hdr_s { + /* WORD 0 */ + union { + uint64_t u64; + struct { + uint8_t pad_len : 3; + uint8_t num_frags : 3; + uint8_t pkt_out : 2; + + uint8_t err_sum : 1; + uint8_t reas_sts : 4; + uint8_t reserved_53 : 1; + uint8_t et_owr : 1; + uint8_t pkt_fmt : 1; + + uint16_t match_id : 16; + + uint32_t cookie : 32; + }; + } w0; + + /* WORD 1 */ + uint64_t wqe_ptr; + + /* WORD 2 */ + union { + uint64_t u64; + struct { + uint8_t fi_pad : 3; + uint8_t fi_offset : 5; + uint8_t il3_off; + uint16_t orig_pf_func; + uint16_t reserved_145_160; + uint16_t frag_age; + }; + } w2; + + /* WORD 3 */ + union { + uint64_t u64; + struct { + uint32_t spi; + uint16_t reserved_209_224; + uint8_t uc_ccode; + uint8_t hw_ccode; + }; + } w3; + + /* WORD 4 */ + union { + uint64_t u64; + uint64_t esn; + uint64_t frag1_wqe_ptr; + }; +}; + +union roc_ot_frag_info { + uint16_t info; + struct { + uint16_t f_off : 13; + uint16_t f_mf : 1; + uint16_t f_rsv : 2; + }; +}; + +struct roc_ot_cpt_frag_info_s { + /* WORD 0 */ + union { + uint64_t u64; + struct { + union roc_ot_frag_info f3; + union roc_ot_frag_info f2; + union roc_ot_frag_info f1; + union roc_ot_frag_info f0; + }; + } w0; + + /* WORD 1 */ + union { + uint64_t u64; + struct { + uint16_t frag_size3; + uint16_t frag_size2; + uint16_t frag_size1; + uint16_t frag_size0; + }; + } w1; +}; + +#endif /* __ROC_IE_OT_H__ */ diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 524585f..97da87a 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -49,6 +49,7 @@ #define PLT_MODEL_MZ_NAME "roc_model_mz" #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE #define BITMASK_ULL GENMASK_ULL +#define PLT_ALIGN_CEIL RTE_ALIGN_CEIL /** Divide ceil */ #define PLT_DIV_CEIL(x, y) \ From patchwork Wed Jun 2 15:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93805 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F23CA0524; Wed, 2 Jun 2021 17:57:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B416410FC; Wed, 2 Jun 2021 17:57:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AE05F4069F for ; Wed, 2 Jun 2021 17:57:31 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJqk019768; Wed, 2 Jun 2021 08:57:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Wed, 2 Jun 2021 08:57:25 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:23 +0530 Message-ID: <1622649385-22652-10-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dIq2iZkImarahxLhGu0xtBNlY918_W_i X-Proofpoint-GUID: dIq2iZkImarahxLhGu0xtBNlY918_W_i X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 09/11] common/cnxk: add AE microcode defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda Microcode AE opcodes support asymmetric operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/roc_ae.h | 56 +++++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 3 +++ 2 files changed, 59 insertions(+) create mode 100644 drivers/common/cnxk/roc_ae.h diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h new file mode 100644 index 0000000..c549e18 --- /dev/null +++ b/drivers/common/cnxk/roc_ae.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_AE_H__ +#define __ROC_AE_H__ + +/* AE opcodes */ +#define ROC_AE_MAJOR_OP_MODEX 0x03 +#define ROC_AE_MAJOR_OP_ECDSA 0x04 +#define ROC_AE_MAJOR_OP_ECC 0x05 +#define ROC_AE_MINOR_OP_MODEX 0x01 +#define ROC_AE_MINOR_OP_PKCS_ENC 0x02 +#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03 +#define ROC_AE_MINOR_OP_PKCS_DEC 0x04 +#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05 +#define ROC_AE_MINOR_OP_MODEX_CRT 0x06 +#define ROC_AE_MINOR_OP_ECDSA_SIGN 0x01 +#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02 +#define ROC_AE_MINOR_OP_ECC_UMP 0x03 + +/** + * Enumeration roc_ae_ec_id + * + * Enumerates supported elliptic curves + */ +typedef enum { + ROC_AE_EC_ID_P192 = 0, + ROC_AE_EC_ID_P224 = 1, + ROC_AE_EC_ID_P256 = 2, + ROC_AE_EC_ID_P384 = 3, + ROC_AE_EC_ID_P521 = 4, + ROC_AE_EC_ID_PMAX = 5 +} roc_ae_ec_id; + +/* Prime and order fields of built-in elliptic curves */ +struct roc_ae_ec_group { + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } prime; + + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } order; +}; + +struct roc_ae_ec_ctx { + /* Prime length defined by microcode for EC operations */ + uint8_t curveid; +}; + +#endif /* __ROC_AE_H__ */ diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 2b43a5a..1e7a208 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -7,6 +7,9 @@ #include "roc_api.h" +#define ROC_AE_CPT_BLOCK_TYPE1 0 +#define ROC_AE_CPT_BLOCK_TYPE2 1 + #define ROC_CPT_MAX_LFS 64 struct roc_cpt_lf { From patchwork Wed Jun 2 15:56:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93806 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B468A0524; 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Wed, 02 Jun 2021 08:57:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:33 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 991D13F703F; Wed, 2 Jun 2021 08:57:30 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , Date: Wed, 2 Jun 2021 21:26:24 +0530 Message-ID: <1622649385-22652-11-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MVxRweg-mcKpAdJl0Kv78boteXVJleE5 X-Proofpoint-GUID: MVxRweg-mcKpAdJl0Kv78boteXVJleE5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 10/11] common/cnxk: add lmtline init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add routine to initialize LMTLINE which facilitates instruction submission to CPT. Add common macros required in the enqueue operations. Signed-off-by: Anoob Joseph Signed-off-by: Ankur Dwivedi --- drivers/common/cnxk/roc_cpt.c | 20 ++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 31 +++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 52 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index d95b94c..6f344ee 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -760,3 +760,23 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf) lf_inprog.s.eena = 0x0; plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); } + +int +roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, + int lf_id) +{ + struct roc_cpt_lf *lf; + + lf = roc_cpt->lf[lf_id]; + if (lf == NULL) + return -ENOTSUP; + + lmtline->io_addr = lf->io_addr; + if (roc_model_is_cn10k()) + lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4; + + lmtline->fc_addr = lf->fc_addr; + lmtline->lmt_base = lf->lmt_base; + + return 0; +} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 1e7a208..885c84d 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -11,6 +11,34 @@ #define ROC_AE_CPT_BLOCK_TYPE2 1 #define ROC_CPT_MAX_LFS 64 +#define ROC_CN10K_CPT_INST_DW_M1 \ + ((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7)) + +/* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of + * APT_LMT_ARG_S + */ +#define ROC_CN10K_CPT_LMT_ARG \ + (ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) | \ + ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14)) + +struct roc_cpt_lmtline { + uint64_t io_addr; + uint64_t *fc_addr; + uintptr_t lmt_base; +}; struct roc_cpt_lf { /* Input parameters */ @@ -65,4 +93,7 @@ int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); +int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, + struct roc_cpt_lmtline *lmtline, int lf_id); + #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index ad559a4..1fa01f1 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,7 @@ INTERNAL { roc_cpt_lf_init; roc_cpt_lf_fini; roc_cpt_lfs_print; + roc_cpt_lmtline_init; roc_cpt_rxc_time_cfg; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Wed Jun 2 15:56:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93807 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BBC2FA0524; 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Wed, 02 Jun 2021 08:57:41 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:57:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:57:40 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 9BC243F703F; Wed, 2 Jun 2021 08:57:35 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:25 +0530 Message-ID: <1622649385-22652-12-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 44F1pg5povcOqE9S6uNobtcoLAYkK2u- X-Proofpoint-GUID: 44F1pg5povcOqE9S6uNobtcoLAYkK2u- X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 11/11] common/cnxk: add fpm tables X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda Add scalar FPM tables to be used for asymmetric operations. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_ae_fpm_tables.c | 1140 +++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_ae_fpm_tables.h | 13 + drivers/common/cnxk/version.map | 2 + 4 files changed, 1156 insertions(+) create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.c create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 739e0e4..fbe4a48 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_ae_fpm_tables.c', 'roc_cpt.c', 'roc_dev.c', 'roc_idev.c', diff --git a/drivers/common/cnxk/roc_ae_fpm_tables.c b/drivers/common/cnxk/roc_ae_fpm_tables.c new file mode 100644 index 0000000..afb2a50 --- /dev/null +++ b/drivers/common/cnxk/roc_ae_fpm_tables.c @@ -0,0 +1,1140 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_ae_fpm_tables.h" +#include "roc_ae.h" + +#define AE_FPM_TBL_NAME "ae_fpm_tbl" + +/* + * AE FPM table sizes Enumeration + * + * 15 table entries * (X, Y, Z coordinates) * Coordinate Offset + * Coordinate Offset depends on elliptic curve as mentioned below, + * 6 quadwords for P-192, P-224 and P-256 + * 7 quadwords for P-384 + * 9 quadwords for P-521 + */ +typedef enum { + AE_FPM_P192_LEN = 2160, + AE_FPM_P224_LEN = 2160, + AE_FPM_P256_LEN = 2160, + AE_FPM_P384_LEN = 2520, + AE_FPM_P521_LEN = 3240 +} ae_fpm_len; + +/* FPM table address and length */ +struct ae_fpm_entry { + const uint8_t *data; + int len; +}; + +struct ae_fpm_tbl { + uint64_t refcount; + uint8_t fpm_tbl[]; +}; + +/* + * Pre-computed ECC FMUL tables needed by cpt microcode + * for NIST curves P-192, P-256, P-384, P-521, P-224. + */ + +const uint8_t ae_fpm_tbl_p192[AE_FPM_P192_LEN] = { + 0xf4, 0xff, 0x0a, 0xfd, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x37, 0x68, 0x81, 0xb6, 0x60, 0xfe, 0xc0, 0x64, 0x38, 0x73, 0x43, 0xe9, + 0x47, 0x5d, 0xae, 0xa4, 0xec, 0xcd, 0x57, 0xe8, 0xac, 0x8d, 0x8a, 0x19, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xc9, 0xfe, 0xf5, 0xb9, 0x5b, 0x51, 0x02, 0x28, 0x37, 0x4c, 0x0a, 0x4c, + 0x19, 0x2e, 0xbc, 0xd6, 0x22, 0x98, 0xf2, 0x04, 0xce, 0x6a, 0x83, 0xf9, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0xe4, 0xb8, 0x20, 0xf4, 0xc5, 0x74, 0xd0, 0x06, 0xd5, 0x86, 0x44, + 0xef, 0xeb, 0x2c, 0xc0, 0xe7, 0x13, 0xa4, 0x00, 0x10, 0xc3, 0xc9, 0x49, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x78, 0xcb, 0x0e, 0x2d, 0x64, 0xee, 0xdf, 0x27, 0xaf, 0x7d, 0x5e, + 0xb8, 0x5e, 0x1f, 0x99, 0xd8, 0x73, 0xce, 0xd7, 0x6c, 0xb7, 0xbe, 0x1f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xef, 0xc9, 0x12, 0x9c, 0x52, 0xa6, 0x7f, 0x9c, 0xa3, 0xd7, 0xb9, 0x57, + 0x60, 0x04, 0xd9, 0xad, 0xfc, 0x59, 0x98, 0x08, 0xdc, 0x41, 0xf8, 0xe2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xbb, 0x6c, 0x6b, 0x59, 0x7f, 0xdf, 0x92, 0x8a, 0xad, 0x16, 0x7e, 0xf0, + 0xd7, 0xf9, 0x3b, 0xf4, 0xfa, 0xa9, 0xe4, 0x32, 0x15, 0x4e, 0x06, 0x1c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0c, 0x3d, 0x0d, 0x63, 0xd5, 0x2c, 0x8f, 0x3f, 0x61, 0x01, 0xb2, 0xbe, + 0xd5, 0xf7, 0xe0, 0x8f, 0xd8, 0x77, 0xcd, 0xdd, 0xd6, 0xae, 0x3c, 0xf3, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; + +const uint8_t ae_fpm_tbl_p224[AE_FPM_P224_LEN] = { + 0x34, 0x32, 0x80, 0xd6, 0x11, 0x5c, 0x1d, 0x21, 0x4a, 0x03, 0xc1, 0xd3, + 0x56, 0xc2, 0x11, 0x22, 0x6b, 0xb4, 0xbf, 0x7f, 0x32, 0x13, 0x90, 0xb9, + 0x00, 0x00, 0x00, 0x00, 0xb7, 0x0e, 0x0c, 0xbd, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x44, 0xd5, 0x81, 0x99, 0x85, 0x00, 0x7e, 0x34, 0xcd, 0x43, 0x75, 0xa0, + 0x5a, 0x07, 0x47, 0x64, 0xb5, 0xf7, 0x23, 0xfb, 0x4c, 0x22, 0xdf, 0xe6, + 0x00, 0x00, 0x00, 0x00, 0xbd, 0x37, 0x63, 0x88, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xc8, 0xae, 0x4d, 0x94, 0xff, 0x48, 0xdb, 0xc5, 0xb5, 0xc8, 0x8b, 0x66, + 0x32, 0xc8, 0x7a, 0x44, 0x66, 0xc7, 0x27, 0x87, 0x2b, 0x8d, 0x08, 0x1c, + 0x00, 0x00, 0x00, 0x00, 0x5b, 0xe5, 0xde, 0x8b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xc6, 0xf8, 0x1e, 0x08, 0x47, 0xfb, 0x64, 0xdb, 0xc8, 0xe3, 0x75, 0x3e, + 0x9d, 0x5a, 0x58, 0x31, 0xa2, 0x13, 0x38, 0x8c, 0x65, 0x8a, 0x02, 0xae, + 0x00, 0x00, 0x00, 0x00, 0xde, 0x52, 0x6c, 0x0d, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xee, 0x8f, 0x93, 0x0d, 0x2b, 0x30, 0x9e, 0xe8, 0xb6, 0x78, 0xea, 0x1a, + 0x0f, 0x59, 0x7e, 0x02, 0x14, 0x74, 0x52, 0x56, 0x6c, 0x25, 0x7d, 0x3e, + 0x00, 0x00, 0x00, 0x00, 0x09, 0xbe, 0x54, 0xb7, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xf6, 0x12, 0x1f, 0xdd, 0x96, 0xa2, 0x05, 0xda, 0x12, 0xa8, 0xe4, 0xf9, + 0x98, 0x15, 0x8e, 0xe1, 0x1b, 0x1d, 0x05, 0x44, 0x47, 0xf2, 0xc3, 0x3a, + 0x00, 0x00, 0x00, 0x00, 0x32, 0xf7, 0x1c, 0x32, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x26, 0x73, 0x99, 0x28, 0x0e, 0x4e, 0x09, 0x58, 0x79, 0xab, 0xae, 0x5c, + 0xa8, 0xeb, 0x9c, 0x0b, 0xe9, 0xa8, 0xac, 0xf0, 0x74, 0x0e, 0xa3, 0x35, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0xb6, 0xce, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x92, 0x09, 0xdc, 0xfe, 0x40, 0x85, 0x7c, 0x64, 0xa2, 0x3f, 0xe4, 0x34, + 0x50, 0xb4, 0x25, 0x87, 0x2a, 0x6f, 0x38, 0x62, 0xb6, 0xfe, 0x44, 0xb1, + 0x00, 0x00, 0x00, 0x00, 0x9e, 0xd1, 0x3b, 0x1b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xf9, 0xfb, 0xf4, 0x91, 0x9a, 0x5f, 0x1c, 0x42, 0x56, 0x8b, 0xc4, 0x34, + 0x8a, 0x69, 0xdd, 0x65, 0x3d, 0x01, 0x11, 0x6e, 0x47, 0x78, 0xdf, 0x49, + 0x00, 0x00, 0x00, 0x00, 0x56, 0x65, 0xff, 0xd2, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xca, 0x4b, 0x80, 0x12, 0xe5, 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0xc4, 0x7d, 0x0a, 0xa0, 0xc7, 0xbe, 0xeb, + 0x00, 0x00, 0x00, 0x00, 0xca, 0x62, 0xa6, 0x8b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5c, 0x26, 0x7c, 0x9c, 0xfb, 0xe5, 0x6a, 0x33, 0x89, 0x37, 0x74, 0x21, + 0x13, 0x71, 0x46, 0x6b, 0x60, 0xd0, 0x38, 0xc4, 0x90, 0xef, 0x7d, 0xec, + 0x00, 0x00, 0x00, 0x00, 0x27, 0xde, 0xcf, 0x82, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x14, 0xf5, 0x42, 0xbe, 0x9e, 0x07, 0x9c, 0x4a, 0x60, 0x56, 0x3b, + 0xcf, 0xe2, 0x06, 0x81, 0xb0, 0xc0, 0x46, 0x49, 0xfb, 0x97, 0x61, 0x5a, + 0x00, 0x00, 0x00, 0x00, 0x2f, 0xa4, 0x2d, 0x2b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x86, 0xe5, 0x99, 0xb4, 0xcf, 0x64, 0x05, 0x25, 0xa3, 0x44, 0xe4, 0x18, + 0x5f, 0x72, 0x58, 0x47, 0x7f, 0xbd, 0x84, 0xd7, 0x0a, 0x38, 0xa0, 0xd4, + 0x00, 0x00, 0x00, 0x00, 0x11, 0x8d, 0x15, 0xd5, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe8, 0x5b, 0x13, 0xf0, 0x09, 0xc6, 0x14, 0x58, 0xc4, 0xf3, 0x1b, 0x3d, + 0x17, 0x0f, 0x1c, 0xfa, 0x7d, 0x61, 0x7e, 0x7e, 0x9c, 0xea, 0x52, 0x0a, + 0x00, 0x00, 0x00, 0x00, 0x89, 0x05, 0xdb, 0xb7, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x26, 0xf8, 0xab, 0x68, 0xb4, 0x27, 0x56, 0x1d, 0x04, 0xed, 0x8c, 0x65, + 0xfd, 0xd1, 0x62, 0x2e, 0x80, 0x4c, 0x4a, 0x1d, 0x67, 0x90, 0x50, 0xed, + 0x00, 0x00, 0x00, 0x00, 0x3b, 0x02, 0x2a, 0x4b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0xe9, 0x36, 0x25, 0x8d, 0x97, 0x84, 0xea, 0xe9, 0x50, 0x4a, 0x27, + 0x66, 0x6e, 0x0c, 0xd2, 0xce, 0x40, 0xfe, 0xfb, 0xf2, 0xc6, 0x53, 0xb4, + 0x00, 0x00, 0x00, 0x00, 0xb6, 0x32, 0x22, 0x76, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xfc, 0x88, 0xcf, 0x76, 0x3c, 0x0b, 0x0d, 0x76, 0xb2, 0xc3, 0xc7, 0x8c, + 0x8c, 0x53, 0x5f, 0x4c, 0xba, 0x0d, 0x13, 0xdb, 0x7b, 0xac, 0xf0, 0x19, + 0x00, 0x00, 0x00, 0x00, 0x7e, 0x11, 0x95, 0x29, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; + +const uint8_t ae_fpm_tbl_p256[AE_FPM_P256_LEN] = { + 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96, 0x77, 0x03, 0x7d, 0x81, + 0x2d, 0xeb, 0x33, 0xa0, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, + 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5, 0x2b, 0xce, 0x33, 0x57, + 0x6b, 0x31, 0x5e, 0xce, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, + 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x06, 0xeb, 0xb0, 0xf6, 0x21, 0xa0, 0x1b, 0x2d, 0xc0, 0x04, 0xe4, 0x04, + 0x8b, 0x7b, 0x0f, 0x98, 0x64, 0x13, 0x1b, 0xcd, 0xfe, 0xd6, 0xf6, 0x68, + 0xfa, 0xc0, 0x15, 0x40, 0x4d, 0x4d, 0x3d, 0xab, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; + +const uint8_t ae_fpm_tbl_p384[AE_FPM_P384_LEN] = { + 0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xb7, 0x55, 0x02, 0xf2, 0x5d, + 0xbf, 0x55, 0x29, 0x6c, 0x59, 0xf7, 0x41, 0xe0, 0x82, 0x54, 0x2a, 0x38, + 0x6e, 0x1d, 0x3b, 0x62, 0x8b, 0xa7, 0x9b, 0x98, 0x8e, 0xb1, 0xc7, 0x1e, + 0xf3, 0x20, 0xad, 0x74, 0xaa, 0x87, 0xca, 0x22, 0xbe, 0x8b, 0x05, 0x37, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x43, 0x1d, 0x7c, + 0x90, 0xea, 0x0e, 0x5f, 0x0a, 0x60, 0xb1, 0xce, 0x1d, 0x7e, 0x81, 0x9d, + 0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0xf8, 0xf4, 0x1d, 0xbd, + 0x28, 0x9a, 0x14, 0x7c, 0x5d, 0x9e, 0x98, 0xbf, 0x92, 0x92, 0xdc, 0x29, + 0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x39, 0xc1, 0xb3, 0x28, 0xd8, 0xee, 0x21, 0xc9, 0x2c, 0x3e, 0x0c, 0x91, + 0x55, 0x87, 0x17, 0xdb, 0x4b, 0x58, 0x80, 0x8b, 0x3f, 0x86, 0x86, 0xa9, + 0x43, 0x60, 0x39, 0x09, 0x18, 0x14, 0x1b, 0x1a, 0xd6, 0xe9, 0x8b, 0x0d, + 0x37, 0xca, 0x7a, 0xbc, 0xf5, 0x32, 0x38, 0x9a, 0x06, 0x0c, 0xbd, 0x1b, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x7e, 0x18, 0x39, + 0x23, 0xd8, 0x6e, 0xcd, 0x31, 0xea, 0x31, 0xb1, 0x08, 0x5a, 0x4e, 0x9a, + 0xbc, 0x40, 0xce, 0x5a, 0xbe, 0x64, 0x36, 0x03, 0xbd, 0x22, 0xcf, 0xb2, + 0xa2, 0x12, 0x41, 0x63, 0x6f, 0x04, 0xca, 0xa2, 0xde, 0x3a, 0x82, 0xba, + 0xb9, 0xd2, 0x85, 0x2c, 0xc3, 0xb3, 0x8e, 0x69, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x26, 0x4e, 0x52, 0x46, 0xeb, 0x09, 0xa0, 0xe5, 0xf8, 0xf4, 0xbe, 0x11, + 0x32, 0xcd, 0xf0, 0x3c, 0xda, 0x9d, 0x54, 0x83, 0x5f, 0xae, 0xfa, 0x4f, + 0xbb, 0xbc, 0x4f, 0xd0, 0x17, 0xa3, 0x1b, 0x22, 0xc3, 0xde, 0xcd, 0x0c, + 0x86, 0xf0, 0x61, 0x45, 0x52, 0x8e, 0xf1, 0x67, 0x0a, 0x5f, 0x2c, 0xab, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x1e, 0x98, 0x58, + 0xc1, 0x4f, 0x0d, 0xd6, 0x55, 0x05, 0x38, 0xa8, 0x09, 0xcb, 0x75, 0x24, + 0xbd, 0x60, 0xca, 0xb4, 0xc8, 0x7f, 0xed, 0x22, 0xf8, 0xb7, 0x6f, 0xdd, + 0x63, 0x1d, 0x05, 0x8d, 0x58, 0x03, 0xea, 0xa1, 0x1a, 0x1d, 0xcf, 0x14, + 0x7b, 0x9b, 0x1f, 0xbe, 0x7b, 0xcc, 0xf5, 0x6c, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xa6, 0x28, 0xb0, 0x9a, 0xaa, 0x03, 0xbd, 0x53, 0xba, 0x06, 0x54, 0x58, + 0xa4, 0xf5, 0x2d, 0x78, 0xdb, 0x29, 0x87, 0x89, 0x4d, 0x10, 0xdd, 0xea, + 0xb4, 0x2a, 0x31, 0xaf, 0x8a, 0x3e, 0x29, 0x7d, 0x40, 0xf7, 0xf9, 0xe7, + 0x06, 0x42, 0x12, 0x79, 0xc1, 0x9e, 0x0b, 0x4c, 0x80, 0x01, 0x19, 0xc4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x2d, 0x0f, 0xc5, + 0xe6, 0xc8, 0x8c, 0x41, 0xaf, 0x68, 0xaa, 0x6d, 0xe6, 0x39, 0xd8, 0x58, + 0xc1, 0xc7, 0xca, 0xd1, 0x35, 0xf6, 0xeb, 0xf2, 0x57, 0x7a, 0x30, 0xea, + 0xe3, 0x56, 0x7a, 0xf9, 0xe5, 0xa0, 0x19, 0x1d, 0x1f, 0x5b, 0x77, 0xf6, + 0x16, 0xf3, 0xfd, 0xbf, 0x03, 0x56, 0xb3, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x99, 0x15, 0x60, 0xaa, 0x13, 0x39, 0x09, 0x90, 0x97, 0xdb, 0xb1, + 0xc6, 0xcb, 0x00, 0x17, 0xd3, 0x7d, 0xe4, 0x24, 0xb8, 0x60, 0xfa, 0xe6, + 0x9b, 0xb1, 0x83, 0xb2, 0x70, 0xb3, 0x75, 0xdd, 0x56, 0x7a, 0x62, 0x33, + 0xcd, 0x6c, 0xe3, 0xa3, 0xaa, 0xb8, 0xbb, 0x9f, 0x0f, 0xdc, 0x30, 0x88, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0xc5, 0xb9, 0x81, + 0x60, 0x0a, 0xd5, 0xa6, 0xeb, 0xdf, 0x73, 0xf2, 0xd6, 0x2f, 0xaa, 0x44, + 0x6d, 0x95, 0x5b, 0xb3, 0xc9, 0x74, 0x7b, 0xf3, 0xf6, 0x00, 0x5f, 0xc8, + 0x15, 0xeb, 0x04, 0xac, 0xf0, 0xaf, 0x01, 0xd1, 0x28, 0x20, 0x50, 0xb5, + 0x48, 0x94, 0x2f, 0x81, 0x31, 0x4f, 0x6d, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x22, 0x11, 0x21, 0x77, 0x16, 0x60, 0x5e, 0x23, 0x47, 0xd2, 0xc8, + 0x9e, 0xf2, 0x81, 0xc8, 0x54, 0xba, 0x45, 0x99, 0x56, 0x7d, 0x63, 0x42, + 0xce, 0x0f, 0xba, 0x30, 0x77, 0xc0, 0xf0, 0x3f, 0x70, 0x22, 0xf8, 0x02, + 0xcb, 0x36, 0x74, 0x44, 0x73, 0x34, 0xa9, 0x36, 0xa9, 0xa6, 0xa0, 0x52, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb5, 0x46, 0x1f, 0x68, + 0xd6, 0x58, 0xa0, 0x1a, 0x0a, 0x64, 0xd5, 0x19, 0xc2, 0xbd, 0x0e, 0xfa, + 0x9e, 0x2e, 0xee, 0x8f, 0x69, 0x7a, 0x92, 0x80, 0x8e, 0x5d, 0x9b, 0x89, + 0x7d, 0x0e, 0x01, 0x7a, 0x1f, 0x7c, 0x5c, 0x36, 0x7c, 0xbd, 0x4c, 0xcd, + 0x7f, 0xfc, 0xef, 0xf7, 0xf6, 0x32, 0xc9, 0x26, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x0a, 0xe2, 0xe6, 0x0e, 0x75, 0x83, 0x44, 0x45, 0x1c, 0x70, 0x7a, + 0x37, 0x1a, 0x2c, 0xa5, 0x25, 0x65, 0x1d, 0x10, 0x50, 0x52, 0xdd, 0x32, + 0xbf, 0x88, 0xde, 0x7f, 0x48, 0x62, 0xb9, 0x54, 0xfa, 0xfc, 0xe2, 0x6e, + 0x03, 0x81, 0xef, 0x13, 0xdc, 0x91, 0x6c, 0x17, 0x96, 0x0e, 0x09, 0x0e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xed, 0x17, 0xcc, 0x44, + 0x02, 0x6b, 0x08, 0x89, 0x95, 0xc0, 0x1f, 0xf1, 0x9b, 0x42, 0x44, 0x1b, + 0x40, 0x89, 0x64, 0x78, 0xcc, 0x16, 0x06, 0x97, 0x52, 0xd1, 0x54, 0xb8, + 0x0b, 0xa0, 0x4a, 0x35, 0xb3, 0xd9, 0x2e, 0xa4, 0x70, 0x1c, 0x29, 0x52, + 0x26, 0x6e, 0x8a, 0x40, 0xd6, 0x9e, 0xca, 0x0a, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe4, 0xbf, 0xc2, 0xc0, 0x49, 0x05, 0xca, 0x71, 0xf3, 0x3a, 0x45, 0x0a, + 0xd1, 0x56, 0xf7, 0x61, 0x3d, 0x8b, 0x29, 0xdb, 0xd0, 0x88, 0x48, 0xc2, + 0x09, 0x7d, 0xa3, 0x95, 0xa2, 0x30, 0x96, 0x86, 0x21, 0x19, 0x05, 0x03, + 0x5f, 0x49, 0x72, 0xd7, 0xb2, 0xd1, 0x05, 0x58, 0x17, 0xcb, 0xaa, 0x12, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdd, 0xce, 0xbb, 0x55, + 0x75, 0x3e, 0xe3, 0x24, 0xe8, 0x7a, 0xb0, 0x7c, 0x69, 0x24, 0x66, 0x6f, + 0x9b, 0x47, 0x5d, 0x74, 0x4e, 0xcf, 0x1a, 0x68, 0xf8, 0x2b, 0xe8, 0xf5, + 0x2e, 0x62, 0x36, 0xc0, 0x23, 0x7c, 0x0d, 0xba, 0x3c, 0xfd, 0x05, 0x6b, + 0x35, 0x4c, 0xd8, 0x72, 0xc3, 0xc6, 0xcb, 0xd2, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x8d, 0x10, 0x4d, 0x24, 0x70, 0x8d, 0x4c, 0xee, 0x19, 0x7d, 0x69, 0x58, + 0x81, 0x9c, 0xf0, 0x43, 0x47, 0xfc, 0x87, 0xfa, 0xf0, 0x71, 0x22, 0x10, + 0x10, 0x3d, 0xf7, 0x85, 0x5c, 0x20, 0x15, 0x58, 0x30, 0xb0, 0xa9, 0xe8, + 0x61, 0x1e, 0xf6, 0x38, 0x00, 0xb1, 0x9a, 0xc8, 0xfd, 0xfe, 0xbf, 0xec, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd4, 0x0e, 0x8d, 0x6f, + 0xd2, 0x01, 0xe0, 0x3e, 0xbb, 0x7c, 0x96, 0x9c, 0x22, 0x28, 0xff, 0x5f, + 0x68, 0x81, 0x02, 0x82, 0x63, 0x61, 0x64, 0xc5, 0xcd, 0xbb, 0x3c, 0xd2, + 0xe7, 0x54, 0x22, 0x0d, 0x14, 0x18, 0xfe, 0x25, 0xe9, 0xf6, 0xed, 0xc4, + 0xa7, 0x2f, 0x91, 0x05, 0x9e, 0xe3, 0x60, 0x31, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x64, 0xd2, 0xc2, 0x73, 0xb7, 0x69, 0x73, 0x7a, 0x2c, 0xc0, 0x24, 0x51, + 0x97, 0xd5, 0x3f, 0xfd, 0xc3, 0xb6, 0xac, 0x4b, 0xe8, 0x6c, 0x46, 0xbd, + 0x17, 0xe9, 0x41, 0x1f, 0x68, 0x5e, 0x92, 0x6d, 0x13, 0x6d, 0xf3, 0x6b, + 0x75, 0x20, 0x3a, 0x36, 0x3f, 0x95, 0x61, 0xe0, 0x8b, 0xf0, 0xb2, 0x7e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdd, 0x6f, 0xf8, 0xd5, + 0x27, 0xe9, 0x90, 0xa7, 0xc3, 0x4b, 0xe5, 0x86, 0xf9, 0x86, 0x7a, 0x60, + 0xea, 0x08, 0x87, 0x47, 0x85, 0x54, 0xe0, 0x14, 0xcf, 0xce, 0xd6, 0x64, + 0x6f, 0x52, 0xe4, 0xcb, 0x4b, 0x1a, 0x5a, 0x20, 0x41, 0x2a, 0xb6, 0x41, + 0x0b, 0x06, 0xf0, 0x06, 0x39, 0x62, 0x95, 0x87, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x4c, 0x0d, 0xd2, 0x85, 0x65, 0x1f, 0x82, 0x32, 0x5c, 0x51, 0xe7, + 0x78, 0x5d, 0x3e, 0xf7, 0xb8, 0x3a, 0x18, 0x61, 0x88, 0xe9, 0x55, 0x32, + 0x53, 0x9f, 0x94, 0xad, 0x52, 0x2c, 0x29, 0x31, 0x15, 0x27, 0x4e, 0x5b, + 0x89, 0x80, 0xf1, 0x37, 0x9f, 0xd7, 0xb0, 0x10, 0xdf, 0x0f, 0x66, 0xd7, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0xa7, 0xb9, 0x4a, + 0x40, 0x64, 0xe4, 0xc0, 0xd4, 0x4e, 0xba, 0x45, 0x25, 0xd7, 0xd2, 0x11, + 0x0a, 0x80, 0x6b, 0x54, 0xbe, 0x8a, 0x04, 0xe3, 0x92, 0x92, 0x26, 0xbd, + 0x14, 0x90, 0x33, 0xde, 0x79, 0x5f, 0x6f, 0xa3, 0xc9, 0x73, 0x92, 0x46, + 0x32, 0x1a, 0xa9, 0xa3, 0xb9, 0x26, 0x02, 0x25, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x49, 0xbc, 0xc2, 0xf5, 0x8b, 0x70, 0x7b, 0x8e, 0x29, 0x01, 0xb5, 0x19, + 0x1d, 0x92, 0x89, 0x83, 0x2e, 0x4c, 0x29, 0x56, 0x7d, 0x49, 0xc7, 0x80, + 0xeb, 0xd1, 0xcf, 0xf8, 0x4c, 0x6a, 0x99, 0x64, 0x2c, 0xae, 0xbb, 0xd3, + 0x16, 0xee, 0x3e, 0x13, 0x36, 0xa5, 0x43, 0xee, 0xa8, 0x7a, 0x68, 0xf7, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0xb4, 0x1c, 0x29, + 0xb5, 0x69, 0x94, 0x6d, 0x15, 0x10, 0xe7, 0xd4, 0x3e, 0xf2, 0x26, 0x7e, + 0x91, 0x23, 0x50, 0x72, 0xd4, 0xb3, 0x39, 0x4d, 0x58, 0xea, 0xff, 0x04, + 0x8f, 0xbd, 0x85, 0xd1, 0xd3, 0x49, 0xab, 0x03, 0x78, 0xa6, 0x78, 0x47, + 0xf2, 0x77, 0xba, 0xcd, 0xa5, 0x0e, 0xe4, 0x1c, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0xb0, 0x56, 0x58, 0x5f, 0x86, 0x3b, 0xbd, 0xe9, 0x2c, 0xdc, 0x5a, + 0xb4, 0x83, 0x28, 0x3d, 0xeb, 0xb3, 0x12, 0x09, 0xdc, 0x7c, 0x42, 0x1d, + 0x3a, 0xfc, 0xbd, 0x79, 0x6d, 0x01, 0xa5, 0xa8, 0xe2, 0xb0, 0x67, 0xca, + 0xa0, 0x8b, 0x6a, 0x51, 0x02, 0x6e, 0x0d, 0xc2, 0xe8, 0xcb, 0x7a, 0xeb, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xc3, 0x50, 0x29, + 0x02, 0xdd, 0xe1, 0x8a, 0x64, 0xc1, 0x5f, 0xac, 0xd8, 0xc6, 0xcf, 0x36, + 0x17, 0xea, 0x27, 0x01, 0x10, 0x78, 0x1e, 0x45, 0xd6, 0x8d, 0x1f, 0xfc, + 0x1f, 0x34, 0x43, 0xd8, 0x4b, 0xe2, 0x56, 0x37, 0x8c, 0x74, 0x61, 0xa5, + 0xae, 0x88, 0x66, 0xba, 0xd8, 0xef, 0x24, 0xe1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xac, 0x3a, 0x78, 0xd0, 0xd2, 0x65, 0xa9, 0x1c, 0x1a, 0x29, 0xf8, 0xef, + 0x6c, 0x8f, 0x83, 0xd3, 0xef, 0x98, 0xfd, 0xde, 0x8f, 0xd8, 0xd8, 0x17, + 0xdf, 0x45, 0x9e, 0xa1, 0xc4, 0x2b, 0xf7, 0x48, 0x14, 0xda, 0xfc, 0x39, + 0x81, 0xa7, 0x3d, 0xc7, 0xb0, 0x3d, 0xfa, 0x54, 0xc5, 0x2a, 0xfa, 0x2d, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x40, 0x6f, 0x6e, + 0x6c, 0x0d, 0x2c, 0xe7, 0xcd, 0x12, 0x0b, 0x2b, 0x41, 0xfd, 0x72, 0xca, + 0xef, 0x5d, 0x90, 0x06, 0x78, 0xf6, 0x02, 0xdd, 0xf5, 0xf8, 0xa2, 0xd1, + 0x8a, 0xcc, 0xf2, 0x29, 0xaa, 0xfd, 0x1f, 0xcf, 0xce, 0x6d, 0x90, 0x8a, + 0x2c, 0xe2, 0x88, 0x5a, 0x0e, 0x6d, 0x85, 0xf2, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x89, 0x10, 0x9a, 0x0e, 0xc6, 0x26, 0x66, 0xde, 0xc8, 0xc1, 0x2e, 0x75, + 0x7f, 0xfc, 0xd0, 0x1e, 0xa8, 0x20, 0x61, 0x69, 0xc4, 0x8b, 0x5a, 0xb0, + 0x4b, 0xc2, 0xfd, 0xcf, 0xf9, 0x83, 0xac, 0x6c, 0x59, 0xcf, 0xca, 0x71, + 0x55, 0x97, 0x7d, 0x23, 0x12, 0x64, 0xcb, 0x33, 0x57, 0x66, 0xc9, 0x6a, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x69, 0x13, 0x81, + 0x2e, 0x01, 0x4b, 0x4b, 0x31, 0xd2, 0x87, 0x07, 0xe4, 0x48, 0x3e, 0xc5, + 0xcb, 0xf7, 0x19, 0x0c, 0xff, 0xb1, 0x97, 0x58, 0xb6, 0x67, 0x17, 0xa0, + 0x65, 0xa5, 0xf2, 0x48, 0xd9, 0x4a, 0xd8, 0xfa, 0xc5, 0x3b, 0x4f, 0x69, + 0x11, 0x9e, 0xbe, 0xee, 0xa1, 0xa1, 0xa3, 0x76, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; + +const uint8_t ae_fpm_tbl_p521[AE_FPM_P521_LEN] = { + 0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66, 0x33, 0x48, 0xb3, 0xc1, + 0x85, 0x6a, 0x42, 0x9b, 0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde, + 0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28, 0xf8, 0x28, 0xaf, 0x60, + 0x6b, 0x4d, 0x3d, 0xba, 0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 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0xee, 0x3a, 0x97, 0x81, 0x71, 0xc3, 0x42, 0x1b, + 0x5b, 0x6d, 0x51, 0xc0, 0x01, 0xed, 0x96, 0x12, 0x52, 0x56, 0x02, 0x26, + 0x6c, 0xc1, 0xdb, 0xed, 0x90, 0x72, 0x2e, 0x36, 0xfa, 0xa6, 0x4f, 0x19, + 0xc2, 0xc7, 0x0c, 0xba, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 +}; + +const struct ae_fpm_entry ae_fpm_tbl_scalar[ROC_AE_EC_ID_PMAX] = { + { + .data = ae_fpm_tbl_p192, + .len = sizeof(ae_fpm_tbl_p192) + }, + { + .data = ae_fpm_tbl_p224, + .len = sizeof(ae_fpm_tbl_p224) + }, + { + .data = ae_fpm_tbl_p256, + .len = sizeof(ae_fpm_tbl_p256) + }, + { + .data = ae_fpm_tbl_p384, + .len = sizeof(ae_fpm_tbl_p384) + }, + { + .data = ae_fpm_tbl_p521, + .len = sizeof(ae_fpm_tbl_p521) + } +}; + +int +roc_ae_fpm_get(uint64_t *tbl) +{ + const char name[] = AE_FPM_TBL_NAME; + const struct plt_memzone *mz; + struct ae_fpm_tbl *fpm; + int i, len = 0; + uint8_t *data; + + if (tbl == NULL) + return -EINVAL; + + /* Compute FPM table size for all supported curves */ + for (i = 0; i < ROC_AE_EC_ID_PMAX; i++) + len += ae_fpm_tbl_scalar[i].len; + + mz = plt_memzone_lookup(name); + if (mz == NULL) { + /* Create memzone first time */ + mz = plt_memzone_reserve_cache_align( + name, sizeof(struct ae_fpm_tbl) + len); + if (mz == NULL) + return -ENOMEM; + } + + fpm = (struct ae_fpm_tbl *)mz->addr; + + if (__atomic_fetch_add(&fpm->refcount, 1, __ATOMIC_SEQ_CST) != 0) + return 0; + + data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t)); + + for (i = ROC_AE_EC_ID_P192; i < ROC_AE_EC_ID_PMAX; i++) { + memcpy(data, ae_fpm_tbl_scalar[i].data, + ae_fpm_tbl_scalar[i].len); + tbl[i] = plt_cpu_to_be_64((uintptr_t)data); + data = PLT_PTR_ADD(data, ae_fpm_tbl_scalar[i].len); + } + + return 0; +} + +void +roc_ae_fpm_put(void) +{ + const char name[] = AE_FPM_TBL_NAME; + const struct plt_memzone *mz; + struct ae_fpm_tbl *fpm; + + mz = plt_memzone_lookup(name); + if (mz == NULL) + return; + + fpm = (struct ae_fpm_tbl *)mz->addr; + /* Decrement number of devices using FPM table */ + if (__atomic_sub_fetch(&fpm->refcount, 1, __ATOMIC_SEQ_CST) == 0) + plt_memzone_free(mz); +} diff --git a/drivers/common/cnxk/roc_ae_fpm_tables.h b/drivers/common/cnxk/roc_ae_fpm_tables.h new file mode 100644 index 0000000..1cc5b02 --- /dev/null +++ b/drivers/common/cnxk/roc_ae_fpm_tables.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_AE_FPM_TABLES_H_ +#define _ROC_AE_FPM_TABLES_H_ + +#include "roc_api.h" + +int __roc_api roc_ae_fpm_get(uint64_t *tbl); +void __roc_api roc_ae_fpm_put(void); + +#endif /* _ROC_AE_FPM_TABLES_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1fa01f1..7ab0ee7 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -10,6 +10,8 @@ INTERNAL { cnxk_logtype_sso; cnxk_logtype_tim; cnxk_logtype_tm; + roc_ae_fpm_get; + roc_ae_fpm_put; roc_clk_freq_get; roc_cpt_afs_print; roc_cpt_dev_clear;