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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT048.mail.protection.outlook.com (10.13.173.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4150.30 via Frontend Transport; Fri, 28 May 2021 13:25:45 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 May 2021 13:25:42 +0000 From: Jiawei Wang To: , , , , Shahaf Shuler CC: , Date: Fri, 28 May 2021 16:25:23 +0300 Message-ID: <20210528132524.32451-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 054df0e9-c43a-477c-fdb0-08d921dc195a X-MS-TrafficTypeDiagnostic: BL0PR12MB5506: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:308; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 13:25:45.0061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 054df0e9-c43a-477c-fdb0-08d921dc195a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5506 Subject: [dpdk-dev] [PATCH 1/2] common/mlx5: add glue function for duplicate rule ability X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add glue function to update the duplicate rule allow/disallow through rdma-core DV API. Signed-off-by: Jiawei Wang --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/linux/mlx5_glue.c | 12 ++++++++++++ drivers/common/mlx5/linux/mlx5_glue.h | 1 + 3 files changed, 15 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 007834a49b..c0bfab1f33 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -191,6 +191,8 @@ has_sym_args = [ 'mlx5dv_dump_dr_rule' ], [ 'HAVE_MLX5_DR_ACTION_ASO_CT', 'infiniband/mlx5dv.h', 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ], + [ 'HAVE_MLX5_DR_ALLOW_DUPLICATE', 'infiniband/mlx5dv.h', + 'mlx5dv_dr_domain_allow_duplicate_rules' ], ] config = configuration_data() foreach arg:has_sym_args diff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c index d3bd645a5b..145cf83fd9 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.c +++ b/drivers/common/mlx5/linux/mlx5_glue.c @@ -1321,6 +1321,17 @@ mlx5_glue_dv_alloc_pp(struct ibv_context *context, #endif } +static void +mlx5_glue_dr_allow_duplicate_rules(void *domain, uint32_t allow) +{ +#ifdef HAVE_MLX5_DR_ALLOW_DUPLICATE + mlx5dv_dr_domain_allow_duplicate_rules(domain, allow); +#else + (void)(allow); + (void)(domain); +#endif +} + static void mlx5_glue_dv_free_pp(struct mlx5dv_pp *pp) { @@ -1441,6 +1452,7 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) { mlx5_glue_dr_create_flow_action_sampler, .dr_create_flow_action_dest_array = mlx5_glue_dr_action_create_dest_array, + .dr_allow_duplicate_rules = mlx5_glue_dr_allow_duplicate_rules, .devx_query_eqn = mlx5_glue_devx_query_eqn, .devx_create_event_channel = mlx5_glue_devx_create_event_channel, .devx_destroy_event_channel = mlx5_glue_devx_destroy_event_channel, diff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h index 97462e9ab8..56246bca18 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.h +++ b/drivers/common/mlx5/linux/mlx5_glue.h @@ -336,6 +336,7 @@ struct mlx5_glue { struct mlx5dv_devx_async_event_hdr *event_data, size_t event_resp_len); void (*dr_reclaim_domain_memory)(void *domain, uint32_t enable); + void (*dr_allow_duplicate_rules)(void *domain, uint32_t allow); struct mlx5dv_pp *(*dv_alloc_pp)(struct ibv_context *context, size_t pp_context_sz, const void *pp_context, From patchwork Fri May 28 13:25:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei Wang X-Patchwork-Id: 93543 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C532A0547; Fri, 28 May 2021 15:25:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 56F0F410FC; Fri, 28 May 2021 15:25:54 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2050.outbound.protection.outlook.com [40.107.92.50]) by mails.dpdk.org (Postfix) with ESMTP id 8EDB2410F2 for ; Fri, 28 May 2021 15:25:52 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; 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Fri, 28 May 2021 13:25:47 +0000 From: Jiawei Wang To: , , , , Shahaf Shuler CC: , Date: Fri, 28 May 2021 16:25:24 +0300 Message-ID: <20210528132524.32451-2-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210528132524.32451-1-jiaweiw@nvidia.com> References: <20210528132524.32451-1-jiaweiw@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e903aa3c-1735-4f0c-ca3d-08d921dc1d1b X-MS-TrafficTypeDiagnostic: DM8PR12MB5462: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sAEklFb0k7nUAw3AKMEIr/mFG4jurz9dzkL08zzAMKSIgZN9Ikr1/4rtxvntqHjNrG/yNwVFiofMdGvMdOzdkDR/Wkg+NA9n2qJEsvnwbTfr+cc3YF3P8kKSgiZuDRmXVHJTfgUC65GZW3cpSzUx/N5iUoUM8j1j1KCAR1HoxKFB+FyV/06lVRZNrU5PUlbuhvS9sjnTA0PK62sMurZNFXhlRlG4tHADMGMkchrTvWYwxfEUQ/PBVT0H/2BFqsPdD2EniPKywJRr4zhHG/Res595upCJ7bKTBkgZL8uFJKxmPWo2l054gPrgLve1orgXtV2whq8dKGiHhOmM4/GYKeOezJuNaQqnb9LHKXMYKsixkkiEhnrBN5Y6dqS4XXPnxKZedpy6fllx8KAx3Ue9E2JkduKhTN71nGfyhMywlnBfiCO7zMkvmEeUidOpfNu+BgoR6IcA4FtzzsOiB+B2vgShPvbDNm1YcwjvLGPwMrT8RKDZDDnDn68p50cDIMUUVoODHfT3gUuTTSAcg5K1X1URdLlecY4GGq5wdNYzi9LczMV9GAkHo2imA5xmdFJ0EkVxBtJFBAMVndIjVVFQsMQ9m7auhytL7wEXi1+rC0gkYh0fSJ98+fdCkowOZttxKOyQcoAfFGRXp+UtmdPtLtoDpfQECYIJ/3KEgsK3K66PSpmtK+xqS9/Jv1C0SHon X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(39860400002)(396003)(376002)(346002)(46966006)(36840700001)(70206006)(70586007)(2906002)(356005)(5660300002)(6666004)(7636003)(36860700001)(82740400003)(82310400003)(1076003)(86362001)(426003)(55016002)(8936002)(316002)(336012)(8676002)(110136005)(478600001)(36906005)(2616005)(54906003)(83380400001)(26005)(6636002)(107886003)(47076005)(4326008)(6286002)(36756003)(7696005)(186003)(16526019)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 13:25:51.2639 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e903aa3c-1735-4f0c-ca3d-08d921dc1d1b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5462 Subject: [dpdk-dev] [PATCH 2/2] net/mlx5: control rules with identical pattern behavior X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In order to allow\disallow configuring rules with identical patterns, the new device argument 'allow_duplicate_pattern' is introduced. If allow, these rules be inserted successfully and only the first rule take affect. If disallow, the first rule will be inserted and other rules be rejected. The default is to allow. Set it to 0 if disallow, for example: -a ,allow_duplicate_pattern=0 Signed-off-by: Jiawei Wang --- doc/guides/nics/mlx5.rst | 10 ++++++++++ doc/guides/rel_notes/release_21_08.rst | 6 ++++++ drivers/net/mlx5/linux/mlx5_os.c | 7 +++++++ drivers/net/mlx5/mlx5.c | 6 ++++++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 3 +++ 6 files changed, 34 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 83299646dd..26f4a25441 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1058,6 +1058,16 @@ Driver options By default, the PMD will set this value to 1. +- ``allow_duplicate_pattern`` parameter [int] + + There are two options to choose: + + - 0. Prevent insertion of rules with the same pattern items on non-root table. + + - 1. Allow insertion of rules with the same pattern items. + + By default, the PMD will set this value to 1. + .. _mlx5_firmware_config: Firmware configuration diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst index a6ecfdf3ce..e6f696a71d 100644 --- a/doc/guides/rel_notes/release_21_08.rst +++ b/doc/guides/rel_notes/release_21_08.rst @@ -55,6 +55,12 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Mellanox mlx5 net driver and common layer.** + + Updated Mellanox mlx5 driver with new features and improvements, including: + + * Added devargs options ``allow_duplicate_pattern``. + Removed Items ------------- diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 534a56a555..7c4384ca77 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -355,6 +355,12 @@ mlx5_alloc_shared_dr(struct mlx5_priv *priv) mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1); } sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); + if (!priv->config.allow_duplicate_pattern) { + mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0); + mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0); + if (sh->fdb_domain) + mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0); + } #endif /* HAVE_MLX5DV_DR */ sh->default_miss_action = mlx5_glue->dr_create_flow_action_default_miss(); @@ -2359,6 +2365,7 @@ mlx5_os_pci_probe_pf(struct rte_pci_device *pci_dev, dev_config.dv_flow_en = 1; dev_config.decap_en = 1; dev_config.log_hp_size = MLX5_ARG_UNSET; + dev_config.allow_duplicate_pattern = 1; list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, &list[i], &dev_config, diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index cf1815cb74..ef15b115d8 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -175,6 +175,9 @@ /* Decap will be used or not. */ #define MLX5_DECAP_EN "decap_en" +/* Device parameter to configure allow or prevent duplicate rules pattern. */ +#define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" + /* Shared memory between primary and secondary processes. */ struct mlx5_shared_data *mlx5_shared_data; @@ -1948,6 +1951,8 @@ mlx5_args_check(const char *key, const char *val, void *opaque) config->sys_mem_en = !!tmp; } else if (strcmp(MLX5_DECAP_EN, key) == 0) { config->decap_en = !!tmp; + } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { + config->allow_duplicate_pattern = !!tmp; } else { DRV_LOG(WARNING, "%s: unknown parameter", key); rte_errno = EINVAL; @@ -2007,6 +2012,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_RECLAIM_MEM, MLX5_SYS_MEM_EN, MLX5_DECAP_EN, + MLX5_ALLOW_DUPLICATE_PATTERN, NULL, }; struct rte_kvargs *kvlist; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 32b2817bf2..63e7779d6f 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -244,6 +244,8 @@ struct mlx5_dev_config { unsigned int sys_mem_en:1; /* The default memory allocator. */ unsigned int decap_en:1; /* Whether decap will be used or not. */ unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ + unsigned int allow_duplicate_pattern:1; + /* Allow/Prevent the duplicate rules pattern. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index c50649a107..17d5a942d8 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -13299,6 +13299,9 @@ flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "hardware refuses to create flow"); + if (!priv->config.allow_duplicate_pattern && + errno == EEXIST) + DRV_LOG(INFO, "duplicate rules not supported"); goto error; } if (priv->vmwa_context &&