From patchwork Sun Apr 25 09:26:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 92124 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3AB04A0548; Sun, 25 Apr 2021 11:26:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1DEA04115E; Sun, 25 Apr 2021 11:26:50 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 4252241143; Sun, 25 Apr 2021 11:26:48 +0200 (CEST) IronPort-SDR: VAqEbG0Ctoh++Ikq7Aula1fheUHVZENAK9ZMNq3n7GPgrzLPPrPR3fkJ7Rp4VDnYqeNiHhqKoN 4hHMWzn+Pu3A== X-IronPort-AV: E=McAfee;i="6200,9189,9964"; a="193037906" X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="193037906" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2021 02:26:47 -0700 IronPort-SDR: 9D/I+6Q31R1jBBNcaVVcbHc2oEIracU0/GP8X3XXC5Qw0k0UyPLkpoXLWnyom98TV53LOhoasE E/3MZUXjukVA== X-IronPort-AV: E=Sophos;i="5.82,250,1613462400"; d="scan'208";a="464781638" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2021 02:26:44 -0700 From: Alvin Zhang To: qi.z.zhang@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, Alvin Zhang , stable@dpdk.org Date: Sun, 25 Apr 2021 17:26:39 +0800 Message-Id: <20210425092639.1428-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [dpdk-dev] [DPDK] net/ice: fix txq mbuf release mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In some cases, it seems that the txq mbuf vector release mode is enabled first, and then it is confirmed that the conditions for using the vector mode are not met. This patch puts the txq vector mode startup process after the condition detection. Fixes: 28f9002ab67f ("net/ice: add Tx AVX512 offload path") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang Acked-by: Leyi Rong --- drivers/net/ice/ice_rxtx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 92fbbc1..49abcb2 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -3303,13 +3303,6 @@ if (tx_check_ret >= 0 && rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { ad->tx_vec_allowed = true; - for (i = 0; i < dev->data->nb_tx_queues; i++) { - txq = dev->data->tx_queues[i]; - if (txq && ice_txq_vec_setup(txq)) { - ad->tx_vec_allowed = false; - break; - } - } if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && @@ -3329,6 +3322,15 @@ if (!use_avx512 && tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) ad->tx_vec_allowed = false; + if (ad->tx_vec_allowed) { + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq && ice_txq_vec_setup(txq)) { + ad->tx_vec_allowed = false; + break; + } + } + } } else { ad->tx_vec_allowed = false; }