From patchwork Mon Apr 5 16:24:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 90566 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 82637A0C42; Mon, 5 Apr 2021 18:24:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 135954068C; Mon, 5 Apr 2021 18:24:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id F134E4014E; Mon, 5 Apr 2021 18:24:25 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 135G5n47009477; Mon, 5 Apr 2021 09:24:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=LD+knSe1ipSF4fcoqklACTAErjjzyqKv2a5buDbtFd4=; b=TXxDMToJDGOMfJPzxN/oU51RMktzKwPPF50DrGasNbJJBJPsDRZly/XbLpWy7e6mwblx nxz4pwRULGvqKuFDElLeBppv15/bYaR8T8X2yEFCCU359gh5sKWmstMJy3oO5glnwoyu 0QfGLfgd2kDOfwGU2Tl8NxaxBCwZPsAJm3rGMsj2KpyyxDm0G3PR9LQcCwPgfj3VPOEh P/z5aEKPUGwssHmJEx7ilbUV4IcxY968mTV+cXQiLQwc1ZUri6UiIFWZim/e5zMWeKtc KoBsfzMIpYATUZIwI5FQIPmk4bRSAEugzGeUIvV6yQnObDtB5VL7aRSJD+WP+d5MPoBo kg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37q2mebsjb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 05 Apr 2021 09:24:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Apr 2021 09:24:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 5 Apr 2021 09:24:24 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 02CC83F703F; Mon, 5 Apr 2021 09:24:21 -0700 (PDT) From: Harman Kalra To: Pavan Nikhilesh , Jerin Jacob CC: , Harman Kalra , Date: Mon, 5 Apr 2021 21:54:15 +0530 Message-ID: <20210405162415.13818-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Proofpoint-GUID: 8qYtJZUw1OjC2AjmOHKqkHttc1Y-QvRe X-Proofpoint-ORIG-GUID: 8qYtJZUw1OjC2AjmOHKqkHttc1Y-QvRe X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-05_13:2021-04-01, 2021-04-05 signatures=0 Subject: [dpdk-dev] [PATCH] event/octeontx2: fix device reconfigure for single slot X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When device is re-configured, memory allocated for work slot is freed and new memory is allocated. Due to this we may loose some important configurations/mappings done with initial work slot memory. For example, whenever rte_event_eth_tx_adapter_queue_add is called some important meta i.e. txq handle is stored in work slot structure. If device gets reconfigured after this tx adaptor add, txq to work slot mapping will be lost resulting in seg fault during packet processing, as txq handle could not be retrieved from work slot. Fixes: 67b5f4686459 ("event/octeontx2: add port config functions") Cc: stable@dpdk.org Signed-off-by: Harman Kalra --- drivers/event/octeontx2/otx2_evdev.c | 34 +++++++++++++--------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index 7e2343599..a6beed069 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -885,29 +885,27 @@ sso_configure_ports(const struct rte_eventdev *event_dev) struct otx2_ssogws *ws; uintptr_t base; - /* Free memory prior to re-allocation if needed */ if (event_dev->data->ports[i] != NULL) { ws = event_dev->data->ports[i]; - rte_free(ssogws_get_cookie(ws)); - ws = NULL; - } + } else { + /* Allocate event port memory */ + ws = rte_zmalloc_socket("otx2_sso_ws", + sizeof(struct otx2_ssogws) + + RTE_CACHE_LINE_SIZE, + RTE_CACHE_LINE_SIZE, + event_dev->data->socket_id); + if (ws == NULL) { + otx2_err("Failed to alloc memory for port=%d", + i); + rc = -ENOMEM; + break; + } - /* Allocate event port memory */ - ws = rte_zmalloc_socket("otx2_sso_ws", - sizeof(struct otx2_ssogws) + - RTE_CACHE_LINE_SIZE, - RTE_CACHE_LINE_SIZE, - event_dev->data->socket_id); - if (ws == NULL) { - otx2_err("Failed to alloc memory for port=%d", i); - rc = -ENOMEM; - break; + /* First cache line is reserved for cookie */ + ws = (struct otx2_ssogws *) + ((uint8_t *)ws + RTE_CACHE_LINE_SIZE); } - /* First cache line is reserved for cookie */ - ws = (struct otx2_ssogws *) - ((uint8_t *)ws + RTE_CACHE_LINE_SIZE); - ws->port = i; base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12); sso_set_port_ops(ws, base);