From patchwork Thu Mar 25 16:03:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: smadarf@marvell.com X-Patchwork-Id: 89912 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5E41A0A02; Fri, 26 Mar 2021 10:48:05 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5A46440685; Fri, 26 Mar 2021 10:48:05 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 47EE3140E4D for ; Thu, 25 Mar 2021 17:06:55 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12PG5ojE013696 for ; Thu, 25 Mar 2021 09:06:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Jn/kyGB3vXOMd1dLiKTEvgLmILrfNWwHTo/VUthpjA4=; b=HfNWm04HIrj/1fCYbm0Wn5FJfAbN0kad53XMcJ9Ae5Ba3iK2VhpcYW/hHLv/9ew2f82t aIxEcUBTGixipYTIaB5Nr4eU93bcfkRVUm3aEQNXIKnzzSzkQpxyV7swlp0jf5cROtV7 fpq+SobTcA+E45CNh8pREY5p955CItYHod5wURb7YCVvsMqc7zxDjKDUMvdf+HL/IfMH bxhMgOGcAVes4s/vv3w1G0OCEW94fSSbeUeoo61eNnKN2iey0hgLK7gwfMk1ETco8p6Y 909g26M6atrwTjXJouNPX9tkRAwoA0KUeO8h3ylR1QC1x9d+JXsc9PAxminRmI5UFGMV wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37dgjp9pnb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 25 Mar 2021 09:06:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 25 Mar 2021 09:06:52 -0700 Received: from vvenus303.il.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 25 Mar 2021 09:06:51 -0700 From: To: CC: , , , Date: Thu, 25 Mar 2021 12:03:21 -0400 Message-ID: <20210325160321.22016-1-smadarf@marvell.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-25_04:2021-03-24, 2021-03-25 signatures=0 X-Mailman-Approved-At: Fri, 26 Mar 2021 10:48:05 +0100 Subject: [dpdk-dev] [PATCH v1] net/octeontx2: support flow action port id X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Smadar Fuks Action port_id was not supported until now. In this patch the action port_id supports passing from input port PF to output port which is one of input port respective VF Signed-off-by: Smadar Fuks Acked-by: Jerin Jacob --- doc/guides/nics/octeontx2.rst | 6 +++ drivers/net/octeontx2/otx2_ethdev.c | 6 +-- drivers/net/octeontx2/otx2_ethdev.h | 5 +++ drivers/net/octeontx2/otx2_ethdev_devargs.c | 2 +- drivers/net/octeontx2/otx2_flow_parse.c | 47 ++++++++++++++++++++- 5 files changed, 61 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index cca7f7fc7..258c1693f 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -401,6 +401,12 @@ Actions: +----+-----------------------------------------+ | 11 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN | +----+-----------------------------------------+ + | 12 | RTE_FLOW_ACTION_TYPE_PORT_ID | + +----+-----------------------------------------+ + +.. note:: + + ``RTE_FLOW_ACTION_TYPE_PORT_ID`` is only supported between PF and its VFs. .. _table_octeontx2_supported_egress_action_types: diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 389b66d03..4f95917e7 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -2802,6 +2802,6 @@ static struct rte_pci_driver pci_nix = { .remove = nix_remove, }; -RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix); -RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map); -RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci"); +RTE_PMD_REGISTER_PCI(OCTEONTX2_PMD, pci_nix); +RTE_PMD_REGISTER_PCI_TABLE(OCTEONTX2_PMD, pci_nix_map); +RTE_PMD_REGISTER_KMOD_DEP(OCTEONTX2_PMD, "vfio-pci"); diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 99f0469d8..5a9dc9be0 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -164,6 +164,11 @@ /* Additional timesync values. */ #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL +#define OCTEONTX2_PMD net_octeontx2 + +#define otx2_ethdev_is_same_driver(dev) \ + (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0) + enum nix_q_size_e { nix_q_size_16, /* 16 entries */ nix_q_size_64, /* 64 entries */ diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c index 8d9feb3a8..83f905315 100644 --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c @@ -201,7 +201,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) return -EINVAL; } -RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2, +RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX2_PMD, OTX2_RSS_RETA_SIZE "=<64|128|256>" OTX2_IPSEC_IN_MAX_SPI "=<1-65535>" OTX2_SCL_ENABLE "=1" diff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c index bbb845811..63a33142a 100644 --- a/drivers/net/octeontx2/otx2_flow_parse.c +++ b/drivers/net/octeontx2/otx2_flow_parse.c @@ -900,14 +900,17 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev, { struct otx2_eth_dev *hw = dev->data->dev_private; struct otx2_npc_flow_info *npc = &hw->npc_flow; + const struct rte_flow_action_port_id *port_act; const struct rte_flow_action_count *act_count; const struct rte_flow_action_mark *act_mark; const struct rte_flow_action_queue *act_q; const struct rte_flow_action_vf *vf_act; + uint16_t pf_func, vf_id, port_id, pf_id; + char if_name[RTE_ETH_NAME_MAX_LEN]; bool vlan_insert_action = false; + struct rte_eth_dev *eth_dev; const char *errmsg = NULL; int sel_act, req_act = 0; - uint16_t pf_func, vf_id; int errcode = 0; int mark = 0; int rq = 0; @@ -983,6 +986,48 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev, } break; + case RTE_FLOW_ACTION_TYPE_PORT_ID: + port_act = (const struct rte_flow_action_port_id *) + actions->conf; + port_id = port_act->id; + if (rte_eth_dev_get_name_by_port(port_id, if_name)) { + errmsg = "Name not found for output port id"; + errcode = EINVAL; + goto err_exit; + } + eth_dev = rte_eth_dev_allocated(if_name); + if (!eth_dev) { + errmsg = "eth_dev not found for output port id"; + errcode = EINVAL; + goto err_exit; + } + if (!otx2_ethdev_is_same_driver(eth_dev)) { + errmsg = "Output port id unsupported type"; + errcode = ENOTSUP; + goto err_exit; + } + if (!otx2_dev_is_vf(otx2_eth_pmd_priv(eth_dev))) { + errmsg = "Output port should be VF"; + errcode = ENOTSUP; + goto err_exit; + } + vf_id = otx2_eth_pmd_priv(eth_dev)->vf; + if (vf_id >= hw->maxvf) { + errmsg = "Invalid vf for output port"; + errcode = EINVAL; + goto err_exit; + } + pf_id = otx2_eth_pmd_priv(eth_dev)->pf; + if (pf_id != hw->pf) { + errmsg = "Output port unsupported PF"; + errcode = ENOTSUP; + goto err_exit; + } + pf_func &= (0xfc00); + pf_func = (pf_func | (vf_id + 1)); + req_act |= OTX2_FLOW_ACT_VF; + break; + case RTE_FLOW_ACTION_TYPE_QUEUE: /* Applicable only to ingress flow */ act_q = (const struct rte_flow_action_queue *)