From patchwork Fri Mar 19 04:43:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 89527 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EABD3A0562; Fri, 19 Mar 2021 05:44:12 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BC1A140143; Fri, 19 Mar 2021 05:44:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 50B784003F for ; Fri, 19 Mar 2021 05:44:11 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12J4etJF010237 for ; Thu, 18 Mar 2021 21:44:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vYkz0MDD6/UBG/qGjz7KEG5yhMByQ/EBBZVPTobv6Fw=; b=bENybCvrS1GzKXHliwFTILcgVVIkBvO+Gkj0tGyN6QtbPUQQbdT/zYNxNDSizCn42dZA iYw4507YdOJiiOARILdv3il2KqE+1y2bGvhje5fLskCCl6XUgjEhIC7RyCH8/1CpuAPt mjGYWkE/gr9Qp/MJbP1g0ymjy86bZoxSFCMVdoscSdC6+1fRgMLs2xz2WxL2wl8qqBte S5PQJ2aJNsDPDp4dY48KSOVYLH4He5u/e0o5vK1xh1dNepNAe4Xg++kS5Koh7tJ8Ub9P fS+QwBqx5YmansH1fGLDlafdiZQMNSuL9EVEuhBW7v8Ycv/bf7gqkRIbV8VosR60uGP4 9w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37cakqa137-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Mar 2021 21:44:09 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Mar 2021 21:44:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Mar 2021 21:44:04 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id D5F463F7043; Thu, 18 Mar 2021 21:44:02 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: , Satheesh Paul Date: Fri, 19 Mar 2021 10:13:56 +0530 Message-ID: <20210319044356.192114-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-19_01:2021-03-17, 2021-03-19 signatures=0 Subject: [dpdk-dev] [PATCH] net/octeontx2: add support for rte_flow_item_raw X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add support for rte_flow_item_raw to parse custom L2 and L3 protocols. Signed-off-by: Satheesh Paul Acked-by: Jerin Jacob --- doc/guides/nics/octeontx2.rst | 39 +++++++- drivers/common/octeontx2/hw/otx2_npc.h | 2 + drivers/common/octeontx2/otx2_mbox.h | 6 +- drivers/net/octeontx2/otx2_ethdev.c | 8 ++ drivers/net/octeontx2/otx2_ethdev_devargs.c | 6 ++ drivers/net/octeontx2/otx2_flow.h | 1 + drivers/net/octeontx2/otx2_flow_dump.c | 3 + drivers/net/octeontx2/otx2_flow_parse.c | 99 ++++++++++++++++++++- drivers/net/octeontx2/otx2_flow_utils.c | 6 +- 9 files changed, 162 insertions(+), 8 deletions(-) diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index 5e1621c1b..cca7f7fc7 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -167,7 +167,7 @@ Runtime Config Options With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2", "dsa", "chlen90b" and "chlen24b". + types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa". - ``RSS tag as XOR`` (default ``0``) @@ -362,6 +362,8 @@ Patterns: +----+--------------------------------+ | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 | +----+--------------------------------+ + | 25 | RTE_FLOW_ITEM_TYPE_RAW | + +----+--------------------------------+ .. note:: @@ -417,3 +419,38 @@ Actions: +----+-----------------------------------------+ | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP | +----+-----------------------------------------+ + +Custom protocols supported in RTE Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols. + +* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level. +* ``NGIO`` can be parsed at L3 level. + +For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the +respective switch header. + +For example:: + + -a 0002:02:00.0,switch_header="vlan_exdsa" + +The below fields of ``struct rte_flow_item_raw`` shall be used to specify the +pattern. + +- ``relative`` Selects the layer at which parsing is done. + + - 0 for ``exdsa`` and ``vlan_exdsa``. + + - 1 for ``NGIO``. + +- ``offset`` The offset in the header where the pattern should be matched. +- ``length`` Length of the pattern. +- ``pattern`` Pattern as a byte string. + +Example usage in testpmd:: + + ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \ + --rx-offloads=0x00080000 --rxq 8 --txq 8 + testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \ + spec ab pattern mask ab offset is 4 / end actions queue index 1 / end diff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h index dd507d57a..b4e3c1eed 100644 --- a/drivers/common/octeontx2/hw/otx2_npc.h +++ b/drivers/common/octeontx2/hw/otx2_npc.h @@ -205,6 +205,7 @@ enum npc_kpu_lb_ltype { NPC_LT_LB_EXDSA, NPC_LT_LB_EXDSA_VLAN, NPC_LT_LB_FDSA, + NPC_LT_LB_VLAN_EXDSA, NPC_LT_LB_CUSTOM0 = 0xE, NPC_LT_LB_CUSTOM1 = 0xF, }; @@ -220,6 +221,7 @@ enum npc_kpu_lc_ltype { NPC_LT_LC_MPLS, NPC_LT_LC_NSH, NPC_LT_LC_FCOE, + NPC_LT_LC_NGIO, NPC_LT_LC_CUSTOM0 = 0xE, NPC_LT_LC_CUSTOM1 = 0xF, }; diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h index 7e7667bf0..5ba96f452 100644 --- a/drivers/common/octeontx2/otx2_mbox.h +++ b/drivers/common/octeontx2/otx2_mbox.h @@ -354,11 +354,13 @@ struct ready_msg_rsp { }; enum npc_pkind_type { - NPC_RX_CHLEN24B_PKIND = 57ULL, + NPC_RX_VLAN_EXDSA_PKIND = 56ULL, + NPC_RX_CHLEN24B_PKIND, NPC_RX_CPT_HDR_PKIND, NPC_RX_CHLEN90B_PKIND, NPC_TX_HIGIG_PKIND, NPC_RX_HIGIG_PKIND, + NPC_RX_EXDSA_PKIND, NPC_RX_EDSA_PKIND, NPC_TX_DEF_PKIND, }; @@ -373,6 +375,8 @@ struct npc_set_pkind { #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1) #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2) #define OTX2_PRIV_FLAGS_FDSA BIT_ULL(3) +#define OTX2_PRIV_FLAGS_EXDSA BIT_ULL(4) +#define OTX2_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5) #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) uint64_t __otx2_io mode; #define PKIND_TX BIT_ULL(0) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index e9fbbca4d..389b66d03 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -122,6 +122,14 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable) OTX2_PRIV_FLAGS_CH_LEN_24B) { req->mode = OTX2_PRIV_FLAGS_CUSTOM; req->pkind = NPC_RX_CHLEN24B_PKIND; + } else if (dev->npc_flow.switch_header_type == + OTX2_PRIV_FLAGS_EXDSA) { + req->mode = OTX2_PRIV_FLAGS_CUSTOM; + req->pkind = NPC_RX_EXDSA_PKIND; + } else if (dev->npc_flow.switch_header_type == + OTX2_PRIV_FLAGS_VLAN_EXDSA) { + req->mode = OTX2_PRIV_FLAGS_CUSTOM; + req->pkind = NPC_RX_VLAN_EXDSA_PKIND; } if (enable == 0) diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c index 71d3e9747..8d9feb3a8 100644 --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c @@ -119,6 +119,12 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) if (strcmp(value, "chlen24b") == 0) *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B; + if (strcmp(value, "exdsa") == 0) + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EXDSA; + + if (strcmp(value, "vlan_exdsa") == 0) + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_VLAN_EXDSA; + return 0; } diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h index f8a19055b..82a5064d9 100644 --- a/drivers/net/octeontx2/otx2_flow.h +++ b/drivers/net/octeontx2/otx2_flow.h @@ -30,6 +30,7 @@ enum { #define NPC_IH_LENGTH 8 #define NPC_TPID_LENGTH 2 #define NPC_HIGIG2_LENGTH 16 +#define NPC_MAX_RAW_ITEM_LEN 16 #define NPC_COUNTER_NONE (-1) /* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */ #define NPC_MAX_EXTRACT_DATA_LEN (64) diff --git a/drivers/net/octeontx2/otx2_flow_dump.c b/drivers/net/octeontx2/otx2_flow_dump.c index d11ee3b28..3f8607130 100644 --- a/drivers/net/octeontx2/otx2_flow_dump.c +++ b/drivers/net/octeontx2/otx2_flow_dump.c @@ -74,11 +74,14 @@ const char *ltype_str[NPC_MAX_LID][NPC_MAX_LT] = { [NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG", [NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ", [NPC_LID_LB][NPC_LT_LB_ETAG] = "LB_ETAG", + [NPC_LID_LB][NPC_LT_LB_EXDSA] = "LB_EXDSA", + [NPC_LID_LB][NPC_LT_LB_VLAN_EXDSA] = "LB_VLAN_EXDSA", [NPC_LID_LC][0] = "NONE", [NPC_LID_LC][NPC_LT_LC_IP] = "LC_IP", [NPC_LID_LC][NPC_LT_LC_IP6] = "LC_IP6", [NPC_LID_LC][NPC_LT_LC_ARP] = "LC_ARP", [NPC_LID_LC][NPC_LT_LC_IP6_EXT] = "LC_IP6_EXT", + [NPC_LID_LC][NPC_LT_LC_NGIO] = "LC_NGIO", [NPC_LID_LD][0] = "NONE", [NPC_LID_LD][NPC_LT_LD_ICMP] = "LD_ICMP", [NPC_LID_LD][NPC_LT_LD_ICMP6] = "LD_ICMP6", diff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c index e9b940f6c..bbb845811 100644 --- a/drivers/net/octeontx2/otx2_flow_parse.c +++ b/drivers/net/octeontx2/otx2_flow_parse.c @@ -489,13 +489,45 @@ flow_check_lc_ip_tunnel(struct otx2_parse_state *pst) pst->tunnel = 1; } +static int +otx2_flow_raw_item_prepare(const struct rte_flow_item_raw *raw_spec, + const struct rte_flow_item_raw *raw_mask, + struct otx2_flow_item_info *info, + uint8_t *spec_buf, uint8_t *mask_buf) +{ + uint32_t custom_hdr_size = 0; + + memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN); + memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN); + custom_hdr_size = raw_spec->offset + raw_spec->length; + + memcpy(spec_buf + raw_spec->offset, raw_spec->pattern, + raw_spec->length); + + if (raw_mask->pattern) { + memcpy(mask_buf + raw_spec->offset, raw_mask->pattern, + raw_spec->length); + } else { + memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length); + } + + info->len = custom_hdr_size; + info->spec = spec_buf; + info->mask = mask_buf; + + return 0; +} + /* Outer IPv4, Outer IPv6, MPLS, ARP */ int otx2_flow_parse_lc(struct otx2_parse_state *pst) { + uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN]; + uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN]; uint8_t hw_mask[NPC_MAX_EXTRACT_DATA_LEN]; + const struct rte_flow_item_raw *raw_spec; struct otx2_flow_item_info info; - int lid, lt; + int lid, lt, len; int rc; if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS) @@ -531,6 +563,30 @@ otx2_flow_parse_lc(struct otx2_parse_state *pst) info.len = sizeof(struct rte_flow_item_ipv6_ext); info.hw_hdr_len = 40; break; + case RTE_FLOW_ITEM_TYPE_RAW: + raw_spec = pst->pattern->spec; + if (!raw_spec->relative) + return 0; + + len = raw_spec->length + raw_spec->offset; + if (len > NPC_MAX_RAW_ITEM_LEN) { + rte_flow_error_set(pst->error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Spec length too big"); + return -rte_errno; + } + + otx2_flow_raw_item_prepare((const struct rte_flow_item_raw *) + pst->pattern->spec, + (const struct rte_flow_item_raw *) + pst->pattern->mask, &info, + raw_spec_buf, raw_mask_buf); + + lid = NPC_LID_LC; + lt = NPC_LT_LC_NGIO; + info.hw_mask = &hw_mask; + otx2_flow_get_hw_supp_mask(pst, &info, lid, lt); + break; default: /* No match at this layer */ return 0; @@ -552,10 +608,13 @@ int otx2_flow_parse_lb(struct otx2_parse_state *pst) { const struct rte_flow_item *pattern = pst->pattern; + uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN]; + uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN]; const struct rte_flow_item *last_pattern; + const struct rte_flow_item_raw *raw_spec; char hw_mask[NPC_MAX_EXTRACT_DATA_LEN]; struct otx2_flow_item_info info; - int lid, lt, lflags; + int lid, lt, lflags, len; int nr_vlans = 0; int rc; @@ -638,13 +697,44 @@ otx2_flow_parse_lb(struct otx2_parse_state *pst) info.def_mask = &rte_flow_item_e_tag_mask; info.len = sizeof(struct rte_flow_item_e_tag); + } else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_RAW) { + raw_spec = pst->pattern->spec; + if (raw_spec->relative) + return 0; + len = raw_spec->length + raw_spec->offset; + if (len > NPC_MAX_RAW_ITEM_LEN) { + rte_flow_error_set(pst->error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Spec length too big"); + return -rte_errno; + } + + if (pst->npc->switch_header_type == + OTX2_PRIV_FLAGS_VLAN_EXDSA) { + lt = NPC_LT_LB_VLAN_EXDSA; + } else if (pst->npc->switch_header_type == + OTX2_PRIV_FLAGS_EXDSA) { + lt = NPC_LT_LB_EXDSA; + } else { + rte_flow_error_set(pst->error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "exdsa or vlan_exdsa not enabled on" + " port"); + return -rte_errno; + } + + otx2_flow_raw_item_prepare((const struct rte_flow_item_raw *) + pst->pattern->spec, + (const struct rte_flow_item_raw *) + pst->pattern->mask, &info, + raw_spec_buf, raw_mask_buf); + + info.hw_hdr_len = 0; } else { return 0; } info.hw_mask = &hw_mask; - info.spec = NULL; - info.mask = NULL; otx2_flow_get_hw_supp_mask(pst, &info, lid, lt); rc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error); @@ -656,6 +746,7 @@ otx2_flow_parse_lb(struct otx2_parse_state *pst) return otx2_flow_update_parse_state(pst, &info, lid, lt, lflags); } + int otx2_flow_parse_la(struct otx2_parse_state *pst) { diff --git a/drivers/net/octeontx2/otx2_flow_utils.c b/drivers/net/octeontx2/otx2_flow_utils.c index d5f0645dc..35f7d0f4b 100644 --- a/drivers/net/octeontx2/otx2_flow_utils.c +++ b/drivers/net/octeontx2/otx2_flow_utils.c @@ -390,7 +390,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item, } /* We have valid spec */ - info->spec = item->spec; + if (item->type != RTE_FLOW_ITEM_TYPE_RAW) + info->spec = item->spec; /* If mask is not set, use default mask, err if default mask is * also NULL. @@ -405,7 +406,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item, } info->mask = info->def_mask; } else { - info->mask = item->mask; + if (item->type != RTE_FLOW_ITEM_TYPE_RAW) + info->mask = item->mask; } /* mask specified must be subset of hw supported mask