From patchwork Mon Jan 18 20:34:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86821 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 98992A0A03; Mon, 18 Jan 2021 21:35:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83DE3140E2A; Mon, 18 Jan 2021 21:35:38 +0100 (CET) Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mails.dpdk.org (Postfix) with ESMTP id 65A6C140E25 for ; Mon, 18 Jan 2021 21:35:35 +0100 (CET) Received: by mail-pj1-f41.google.com with SMTP id g15so6312069pjd.2 for ; Mon, 18 Jan 2021 12:35:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B4UI11kE2DNoQedH08fP0vqG/hiVRwSZOAYmeDV4EOk=; b=ZNY31uba3qlHeZWIrRTjitJjW7r2Ys5rfBCTaYJLE6vhUyjPsuG+xu+SDwdcYf3ERL 54MwYRxYd3lG3LOdRHxFs6wN4q+nq+Ln2DdctCI8pzfPe6WmOtQIVkCZtqhtkKvbYabz IbKVfc/SCDnRuxavn74diKSg16NQl0lRoh4Pi8zJ/bdDJrspxghnxuiw0mtvxG5K/3LH UUp1y/eebLX7Jp76Qf7ALPsV8tDjJE4LRKHZi10uRYzKaKQDSVtha1yd1NHhoCVHRP+v iczmblbf18OIKIVPHVEGi4i+VcWs+WzKUzaVNX0Hi6z4IPI85mIy9eLFIusqXpZpljiw 6taQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B4UI11kE2DNoQedH08fP0vqG/hiVRwSZOAYmeDV4EOk=; b=ALNQ2/R4+WdY8idpOZecbL9u3Ft935HlaxRQJ0a/OFjKim3XnQgBwrPlKhx8qwNjKh D485uWwVJU0KnEm9/8SP1PpFkrfsBG4WVFghl+kASnWpjTpyU1YU/uyWT/0YCS5ez98Z oNWzhkIFbX0kYJWNQtqLNwjZMrUZbsi/6jNVcfOJ0/LWtjvjyjUQdXOb89UuIzql61Bt wpfAToY4GAyH8zrqYVZWaZD9JWY/q3s/Qc9R85ZcRMK0qUMPCRpwkHYbzuaVGhNLkVSY SoxJ9XUX7FJqwDWVHapH9trdlo1WRJxWW76Cbx7B4VgOXO5OJ5+CR7eheSW2RZLHQ8cg CM2w== X-Gm-Message-State: AOAM533mksP3j3rJB1Gk9KXgFObgozMy/WECdE2hqAlFu0GCH/alDKjf OOeGFIpNvbbNzdPfvuhBi0LuSUbSvutl4A== X-Google-Smtp-Source: ABdhPJwhAGKdSHASgbNTy2w5x8yHRbIQzxxnkf9lMMN5zn8HXnokS+y2adH5FdAmP8weCasjPlcUQg== X-Received: by 2002:a17:90a:9603:: with SMTP id v3mr1172794pjo.128.1611002134253; Mon, 18 Jan 2021 12:35:34 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:33 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:34:56 -0800 Message-Id: <20210118203508.1332-2-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 01/13] net/ionic: strip out unneeded interrupt code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Only the NotifyQ uses an interrupt, so simplify the other queues. Simplify ionic_dev_cmd_adminq_init() and ionic_cq_init(). Move ionic_intr_alloc() into ionic_notify_qcq_alloc(). Create ionic_lif_notifyq_deinit(). Simplify ionic_lif_qcq_deinit(). Remove unneeded flags and defines. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 8 +-- drivers/net/ionic/ionic_dev.h | 12 ++-- drivers/net/ionic/ionic_lif.c | 116 ++++++++++++++++------------------ drivers/net/ionic/ionic_lif.h | 2 - 4 files changed, 59 insertions(+), 79 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index 4b5e24f98c..3507d4166f 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -323,9 +323,7 @@ ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, } void -ionic_dev_cmd_adminq_init(struct ionic_dev *idev, - struct ionic_qcq *qcq, - uint16_t intr_index) +ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq) { struct ionic_queue *q = &qcq->q; struct ionic_cq *cq = &qcq->cq; @@ -335,7 +333,7 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, .q_init.type = q->type, .q_init.index = q->index, .q_init.flags = IONIC_QINIT_F_ENA, - .q_init.intr_index = intr_index, + .q_init.intr_index = IONIC_INTR_NONE, .q_init.ring_size = rte_log2_u32(q->num_descs), .q_init.ring_base = q->base_pa, .q_init.cq_ring_base = cq->base_pa, @@ -348,7 +346,6 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, - struct ionic_intr_info *intr, uint32_t num_descs, size_t desc_size) { if (desc_size == 0) { @@ -365,7 +362,6 @@ ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, } cq->lif = lif; - cq->bound_intr = intr; cq->num_descs = num_descs; cq->desc_size = desc_size; cq->tail_idx = 0; diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 6588a373fc..6ee2918959 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -165,11 +165,9 @@ struct ionic_queue { struct ionic_doorbell __iomem *db; }; -#define IONIC_INTR_INDEX_NOT_ASSIGNED (-1) -#define IONIC_INTR_NAME_MAX_SZ (32) +#define IONIC_INTR_NONE (-1) struct ionic_intr_info { - char name[IONIC_INTR_NAME_MAX_SZ]; int index; uint32_t vector; struct ionic_intr __iomem *ctrl; @@ -184,7 +182,6 @@ struct ionic_cq { bool done_color; void *base; rte_iova_t base_pa; - struct ionic_intr_info *bound_intr; }; /** ionic_admin_ctx - Admin command context. @@ -234,15 +231,14 @@ void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver); void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); void ionic_dev_cmd_lif_reset(struct ionic_dev *idev); -void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, - uint16_t intr_index); + +void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq); struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q); int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, - struct ionic_intr_info *intr, uint32_t num_descs, - size_t desc_size); + uint32_t num_descs, size_t desc_size); void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q); typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint32_t cq_desc_index, diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index f39b54e8ef..856e977186 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -20,7 +20,6 @@ ionic_qcq_enable(struct ionic_qcq *qcq) { struct ionic_queue *q = &qcq->q; struct ionic_lif *lif = q->lif; - struct ionic_dev *idev = &lif->adapter->idev; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.q_control = { @@ -31,11 +30,6 @@ ionic_qcq_enable(struct ionic_qcq *qcq) }, }; - if (qcq->flags & IONIC_QCQ_F_INTR) { - ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, - IONIC_INTR_MASK_CLEAR); - } - return ionic_adminq_post_wait(lif, &ctx); } @@ -44,7 +38,6 @@ ionic_qcq_disable(struct ionic_qcq *qcq) { struct ionic_queue *q = &qcq->q; struct ionic_lif *lif = q->lif; - struct ionic_dev *idev = &lif->adapter->idev; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.q_control = { @@ -55,11 +48,6 @@ ionic_qcq_disable(struct ionic_qcq *qcq) }, }; - if (qcq->flags & IONIC_QCQ_F_INTR) { - ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, - IONIC_INTR_MASK_SET); - } - return ionic_adminq_post_wait(lif, &ctx); } @@ -584,7 +572,7 @@ ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) void ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr) { - if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED) + if (intr->index != IONIC_INTR_NONE) lif->adapter->intrs[intr->index] = false; } @@ -640,7 +628,8 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0); if (!new->q.info) { IONIC_PRINT(ERR, "Cannot allocate queue info"); - return -ENOMEM; + err = -ENOMEM; + goto err_out_free_qcq; } new->q.type = type; @@ -649,25 +638,13 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, desc_size, sg_desc_size); if (err) { IONIC_PRINT(ERR, "Queue initialization failed"); - return err; + goto err_out_free_info; } - if (flags & IONIC_QCQ_F_INTR) { - err = ionic_intr_alloc(lif, &new->intr); - if (err) - return err; - - ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index, - IONIC_INTR_MASK_SET); - } else { - new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; - } - - err = ionic_cq_init(lif, &new->cq, &new->intr, - num_descs, cq_desc_size); + err = ionic_cq_init(lif, &new->cq, num_descs, cq_desc_size); if (err) { IONIC_PRINT(ERR, "Completion queue initialization failed"); - goto err_out_free_intr; + goto err_out_free_info; } new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, @@ -677,7 +654,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, if (!new->base_z) { IONIC_PRINT(ERR, "Cannot reserve queue DMA memory"); err = -ENOMEM; - goto err_out_free_intr; + goto err_out_free_info; } new->base = new->base_z->addr; @@ -709,9 +686,10 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type, return 0; -err_out_free_intr: - if (flags & IONIC_QCQ_F_INTR) - ionic_intr_free(lif, &new->intr); +err_out_free_info: + rte_free(new->q.info); +err_out_free_qcq: + rte_free(new); return err; } @@ -800,21 +778,32 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif) static int ionic_notify_qcq_alloc(struct ionic_lif *lif) { - uint32_t flags; + struct ionic_qcq *nqcq; + struct ionic_dev *idev = &lif->adapter->idev; + uint32_t flags = 0; int err = -ENOMEM; - flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR; - err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify", flags, IONIC_NOTIFYQ_LENGTH, sizeof(struct ionic_notifyq_cmd), sizeof(union ionic_notifyq_comp), 0, - &lif->notifyqcq); + &nqcq); if (err) return err; + err = ionic_intr_alloc(lif, &nqcq->intr); + if (err) { + ionic_qcq_free(nqcq); + return err; + } + + ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index, + IONIC_INTR_MASK_SET); + + lif->notifyqcq = nqcq; + return 0; } @@ -1040,30 +1029,36 @@ ionic_lif_rss_teardown(struct ionic_lif *lif) } static void -ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) +ionic_lif_qcq_deinit(struct ionic_qcq *qcq) { - struct ionic_dev *idev = &lif->adapter->idev; - - if (!(qcq->flags & IONIC_QCQ_F_INITED)) - return; - - if (qcq->flags & IONIC_QCQ_F_INTR) - ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, - IONIC_INTR_MASK_SET); - qcq->flags &= ~IONIC_QCQ_F_INITED; } void ionic_lif_txq_deinit(struct ionic_qcq *qcq) { - ionic_lif_qcq_deinit(qcq->lif, qcq); + ionic_lif_qcq_deinit(qcq); } void ionic_lif_rxq_deinit(struct ionic_qcq *qcq) { - ionic_lif_qcq_deinit(qcq->lif, qcq); + ionic_lif_qcq_deinit(qcq); +} + +static void +ionic_lif_notifyq_deinit(struct ionic_lif *lif) +{ + struct ionic_qcq *nqcq = lif->notifyqcq; + struct ionic_dev *idev = &lif->adapter->idev; + + if (!(nqcq->flags & IONIC_QCQ_F_INITED)) + return; + + ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, + IONIC_INTR_MASK_SET); + + nqcq->flags &= ~IONIC_QCQ_F_INITED; } bool @@ -1227,7 +1222,7 @@ ionic_lif_adminq_init(struct ionic_lif *lif) struct ionic_q_init_comp comp; int err; - ionic_dev_cmd_adminq_init(idev, qcq, qcq->intr.index); + ionic_dev_cmd_adminq_init(idev, qcq); err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); if (err) return err; @@ -1242,10 +1237,6 @@ ionic_lif_adminq_init(struct ionic_lif *lif) IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index); IONIC_PRINT(DEBUG, "adminq->db %p", q->db); - if (qcq->flags & IONIC_QCQ_F_INTR) - ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, - IONIC_INTR_MASK_CLEAR); - qcq->flags |= IONIC_QCQ_F_INITED; return 0; @@ -1292,9 +1283,8 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index); IONIC_PRINT(DEBUG, "notifyq->db %p", q->db); - if (qcq->flags & IONIC_QCQ_F_INTR) - ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, - IONIC_INTR_MASK_CLEAR); + ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, + IONIC_INTR_MASK_CLEAR); qcq->flags |= IONIC_QCQ_F_INITED; @@ -1372,7 +1362,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) .type = q->type, .index = q->index, .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = cq->bound_intr->index, + .intr_index = IONIC_INTR_NONE, .ring_size = rte_log2_u32(q->num_descs), .ring_base = q->base_pa, .cq_ring_base = cq->base_pa, @@ -1418,7 +1408,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) .type = q->type, .index = q->index, .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = cq->bound_intr->index, + .intr_index = IONIC_INTR_NONE, .ring_size = rte_log2_u32(q->num_descs), .ring_base = q->base_pa, .cq_ring_base = cq->base_pa, @@ -1544,10 +1534,10 @@ ionic_lif_init(struct ionic_lif *lif) ionic_rx_filters_deinit(lif); err_out_notifyq_deinit: - ionic_lif_qcq_deinit(lif, lif->notifyqcq); + ionic_lif_notifyq_deinit(lif); err_out_adminq_deinit: - ionic_lif_qcq_deinit(lif, lif->adminqcq); + ionic_lif_qcq_deinit(lif->adminqcq); return err; } @@ -1560,8 +1550,8 @@ ionic_lif_deinit(struct ionic_lif *lif) ionic_rx_filters_deinit(lif); ionic_lif_rss_teardown(lif); - ionic_lif_qcq_deinit(lif, lif->notifyqcq); - ionic_lif_qcq_deinit(lif, lif->adminqcq); + ionic_lif_notifyq_deinit(lif); + ionic_lif_qcq_deinit(lif->adminqcq); lif->state &= ~IONIC_LIF_F_INITED; } diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index 4f48845eb9..d245c6da01 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -48,8 +48,6 @@ struct ionic_rx_stats { #define IONIC_QCQ_F_INITED BIT(0) #define IONIC_QCQ_F_SG BIT(1) -#define IONIC_QCQ_F_INTR BIT(2) -#define IONIC_QCQ_F_NOTIFYQ BIT(3) #define IONIC_QCQ_F_DEFERRED BIT(4) /* Queue / Completion Queue */ From patchwork Mon Jan 18 20:34:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86822 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A1ACA0A03; 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Mon, 18 Jan 2021 12:35:36 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:34:57 -0800 Message-Id: <20210118203508.1332-3-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 02/13] net/ionic: observe endianness in firmware commands X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The IONIC firmware is little-endian. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 27 +++--- drivers/net/ionic/ionic_ethdev.c | 27 +++--- drivers/net/ionic/ionic_lif.c | 138 ++++++++++++++++--------------- drivers/net/ionic/ionic_main.c | 6 +- 4 files changed, 109 insertions(+), 89 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index 3507d4166f..c3016b2d50 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -165,7 +165,7 @@ ionic_dev_cmd_port_init(struct ionic_dev *idev) union ionic_dev_cmd cmd = { .port_init.opcode = IONIC_CMD_PORT_INIT, .port_init.index = 0, - .port_init.info_pa = idev->port_info_pa, + .port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa), }; ionic_dev_cmd_go(idev, &cmd); @@ -202,7 +202,7 @@ ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed) .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, .port_setattr.index = 0, .port_setattr.attr = IONIC_PORT_ATTR_SPEED, - .port_setattr.speed = speed, + .port_setattr.speed = rte_cpu_to_le_32(speed), }; ionic_dev_cmd_go(idev, &cmd); @@ -215,7 +215,7 @@ ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu) .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, .port_setattr.index = 0, .port_setattr.attr = IONIC_PORT_ATTR_MTU, - .port_setattr.mtu = mtu, + .port_setattr.mtu = rte_cpu_to_le_32(mtu), }; ionic_dev_cmd_go(idev, &cmd); @@ -292,7 +292,7 @@ ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa) { union ionic_dev_cmd cmd = { .lif_init.opcode = IONIC_CMD_LIF_INIT, - .lif_init.info_pa = info_pa, + .lif_init.info_pa = rte_cpu_to_le_64(info_pa), }; ionic_dev_cmd_go(idev, &cmd); @@ -331,12 +331,12 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq) union ionic_dev_cmd cmd = { .q_init.opcode = IONIC_CMD_Q_INIT, .q_init.type = q->type, - .q_init.index = q->index, - .q_init.flags = IONIC_QINIT_F_ENA, - .q_init.intr_index = IONIC_INTR_NONE, + .q_init.index = rte_cpu_to_le_32(q->index), + .q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA), + .q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .q_init.ring_size = rte_log2_u32(q->num_descs), - .q_init.ring_base = q->base_pa, - .q_init.cq_ring_base = cq->base_pa, + .q_init.ring_base = rte_cpu_to_le_64(q->base_pa), + .q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa), }; IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver); @@ -517,9 +517,14 @@ ionic_adminq_cb(struct ionic_queue *q, struct ionic_admin_ctx *ctx = cb_arg; struct ionic_admin_comp *cq_desc_base = q->bound_cq->base; struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index]; + uint16_t comp_index; - if (unlikely(cq_desc->comp_index != q_desc_index)) { - IONIC_WARN_ON(cq_desc->comp_index != q_desc_index); + if (!ctx) + return; + + comp_index = rte_le_to_cpu_16(cq_desc->comp_index); + if (unlikely(comp_index != q_desc_index)) { + IONIC_WARN_ON(comp_index != q_desc_index); return; } diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index 2face7c635..a5b2301e46 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -374,13 +374,15 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; IONIC_PRINT_CALL(); dev_info->max_rx_queues = (uint16_t) - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); dev_info->max_tx_queues = (uint16_t) - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); + /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; @@ -389,7 +391,7 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, dev_info->max_mtu = IONIC_MAX_MTU; dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; - dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; + dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; dev_info->speed_capa = @@ -534,6 +536,7 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; uint32_t i, j, index, num; + uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -543,15 +546,15 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, return -EINVAL; } - if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { + if (reta_size != tbl_sz) { IONIC_PRINT(ERR, "The size of hash lookup table configured " "(%d) does not match the number hardware can support " "(%d)", - reta_size, ident->lif.eth.rss_ind_tbl_sz); + reta_size, tbl_sz); return -EINVAL; } - num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; + num = tbl_sz / RTE_RETA_GROUP_SIZE; for (i = 0; i < num; i++) { for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { @@ -574,14 +577,15 @@ ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, struct ionic_adapter *adapter = lif->adapter; struct ionic_identity *ident = &adapter->ident; int i, num; + uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); - if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { + if (reta_size != tbl_sz) { IONIC_PRINT(ERR, "The size of hash lookup table configured " "(%d) does not match the number hardware can support " "(%d)", - reta_size, ident->lif.eth.rss_ind_tbl_sz); + reta_size, tbl_sz); return -EINVAL; } @@ -1228,11 +1232,12 @@ eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, goto err_free_adapter; } - adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; + adapter->max_mac_addrs = + rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); - if (adapter->ident.dev.nlifs != 1) { + if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { IONIC_PRINT(ERR, "Unexpected request for %d LIFs", - adapter->ident.dev.nlifs); + rte_le_to_cpu_32(adapter->ident.dev.nlifs)); goto err_free_adapter; } diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 856e977186..15e291b604 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -25,7 +25,7 @@ ionic_qcq_enable(struct ionic_qcq *qcq) .cmd.q_control = { .opcode = IONIC_CMD_Q_CONTROL, .type = q->type, - .index = q->index, + .index = rte_cpu_to_le_32(q->index), .oper = IONIC_Q_ENABLE, }, }; @@ -43,7 +43,7 @@ ionic_qcq_disable(struct ionic_qcq *qcq) .cmd.q_control = { .opcode = IONIC_CMD_Q_CONTROL, .type = q->type, - .index = q->index, + .index = rte_cpu_to_le_32(q->index), .oper = IONIC_Q_DISABLE, }, }; @@ -241,7 +241,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) .pending_work = true, .cmd.rx_filter_add = { .opcode = IONIC_CMD_RX_FILTER_ADD, - .match = IONIC_RX_FILTER_MATCH_MAC, + .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), }, }; int err; @@ -253,7 +253,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) return err; IONIC_PRINT(INFO, "rx_filter add (id %d)", - ctx.comp.rx_filter_add.filter_id); + rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); } @@ -280,7 +280,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) return -ENOENT; } - ctx.cmd.rx_filter_del.filter_id = f->filter_id; + ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); ionic_rx_filter_free(f); rte_spinlock_unlock(&lif->rx_filters.lock); @@ -290,7 +290,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) return err; IONIC_PRINT(INFO, "rx_filter del (id %d)", - ctx.cmd.rx_filter_del.filter_id); + rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); return 0; } @@ -364,8 +364,8 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) .pending_work = true, .cmd.rx_filter_add = { .opcode = IONIC_CMD_RX_FILTER_ADD, - .match = IONIC_RX_FILTER_MATCH_VLAN, - .vlan.vlan = vid, + .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), + .vlan.vlan = rte_cpu_to_le_16(vid), }, }; int err; @@ -375,7 +375,7 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) return err; IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, - ctx.comp.rx_filter_add.filter_id); + rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); } @@ -402,7 +402,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) return -ENOENT; } - ctx.cmd.rx_filter_del.filter_id = f->filter_id; + ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); ionic_rx_filter_free(f); rte_spinlock_unlock(&lif->rx_filters.lock); @@ -411,7 +411,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) return err; IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, - ctx.cmd.rx_filter_del.filter_id); + rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); return 0; } @@ -438,7 +438,7 @@ ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) .pending_work = true, .cmd.rx_mode_set = { .opcode = IONIC_CMD_RX_MODE_SET, - .rx_mode = rx_mode, + .rx_mode = rte_cpu_to_le_16(rx_mode), }, }; int err; @@ -530,7 +530,7 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_MTU, - .mtu = new_mtu, + .mtu = rte_cpu_to_le_32(new_mtu), }, }; int err; @@ -942,16 +942,19 @@ int ionic_lif_rss_config(struct ionic_lif *lif, const uint16_t types, const uint8_t *key, const uint32_t *indir) { + struct ionic_adapter *adapter = lif->adapter; struct ionic_admin_ctx ctx = { .pending_work = true, .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_RSS, - .rss.types = types, - .rss.addr = lif->rss_ind_tbl_pa, + .rss.types = rte_cpu_to_le_16(types), + .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), }, }; unsigned int i; + uint16_t tbl_sz = + rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -961,7 +964,7 @@ ionic_lif_rss_config(struct ionic_lif *lif, memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); if (indir) - for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++) + for (i = 0; i < tbl_sz; i++) lif->rss_ind_tbl[i] = indir[i]; memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, @@ -973,6 +976,7 @@ ionic_lif_rss_config(struct ionic_lif *lif, static int ionic_lif_rss_setup(struct ionic_lif *lif) { + struct ionic_adapter *adapter = lif->adapter; static const uint8_t toeplitz_symmetric_key[] = { 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, @@ -981,7 +985,8 @@ ionic_lif_rss_setup(struct ionic_lif *lif) 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, }; uint32_t i; - uint16_t tbl_sz = lif->adapter->ident.lif.eth.rss_ind_tbl_sz; + uint16_t tbl_sz = + rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); IONIC_PRINT_CALL(); @@ -1107,7 +1112,8 @@ ionic_link_status_check(struct ionic_lif *lif) return; if (link_up) { - adapter->link_speed = lif->info->status.link_speed; + adapter->link_speed = + rte_le_to_cpu_32(lif->info->status.link_speed); IONIC_PRINT(DEBUG, "Link up - %d Gbps", adapter->link_speed); } else { @@ -1230,7 +1236,7 @@ ionic_lif_adminq_init(struct ionic_lif *lif) ionic_dev_cmd_comp(idev, &comp); q->hw_type = comp.hw_type; - q->hw_index = comp.hw_index; + q->hw_index = rte_le_to_cpu_32(comp.hw_index); q->db = ionic_db_map(lif, q); IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); @@ -1255,18 +1261,17 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA), - .intr_index = qcq->intr.index, + .index = rte_cpu_to_le_32(q->index), + .intr_index = rte_cpu_to_le_16(qcq->intr.index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | + IONIC_QINIT_F_ENA), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), } }; - IONIC_PRINT(DEBUG, "notifyq_init.index %d", - ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); @@ -1276,7 +1281,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = NULL; IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); @@ -1299,7 +1304,7 @@ ionic_lif_set_features(struct ionic_lif *lif) .cmd.lif_setattr = { .opcode = IONIC_CMD_LIF_SETATTR, .attr = IONIC_LIF_ATTR_FEATURES, - .features = lif->features, + .features = rte_cpu_to_le_64(lif->features), }, }; int err; @@ -1308,8 +1313,8 @@ ionic_lif_set_features(struct ionic_lif *lif) if (err) return err; - lif->hw_features = (ctx.cmd.lif_setattr.features & - ctx.comp.lif_setattr.features); + lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & + ctx.comp.lif_setattr.features); if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); @@ -1360,20 +1365,20 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = IONIC_INTR_NONE, + .index = rte_cpu_to_le_32(q->index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | + IONIC_QINIT_F_ENA), + .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, - .cq_ring_base = cq->base_pa, - .sg_ring_base = q->sg_base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), + .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), + .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), }, }; int err; - IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "txq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); @@ -1383,7 +1388,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = ionic_db_map(lif, q); IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); @@ -1406,20 +1411,20 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, - .index = q->index, - .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA, - .intr_index = IONIC_INTR_NONE, + .index = rte_cpu_to_le_32(q->index), + .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | + IONIC_QINIT_F_ENA), + .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), .ring_size = rte_log2_u32(q->num_descs), - .ring_base = q->base_pa, - .cq_ring_base = cq->base_pa, - .sg_ring_base = q->sg_base_pa, + .ring_base = rte_cpu_to_le_64(q->base_pa), + .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), + .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), }, }; int err; - IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index); - IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", - ctx.cmd.q_init.ring_base); + IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); + IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", ctx.cmd.q_init.ring_size); IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); @@ -1429,7 +1434,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) return err; q->hw_type = ctx.comp.q_init.hw_type; - q->hw_index = ctx.comp.q_init.hw_index; + q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); q->db = ionic_db_map(lif, q); qcq->flags |= IONIC_QCQ_F_INITED; @@ -1496,7 +1501,7 @@ ionic_lif_init(struct ionic_lif *lif) if (err) return err; - lif->hw_index = comp.hw_index; + lif->hw_index = rte_cpu_to_le_16(comp.hw_index); err = ionic_lif_adminq_init(lif); if (err) @@ -1582,10 +1587,11 @@ ionic_lif_configure(struct ionic_lif *lif) struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; struct ionic_identity *ident = &lif->adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; uint32_t ntxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); uint32_t nrxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; @@ -1722,6 +1728,7 @@ ionic_lif_identify(struct ionic_adapter *adapter) { struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; + union ionic_lif_config *cfg = &ident->lif.eth.config; int err; unsigned int i; unsigned int lif_words = sizeof(ident->lif.words) / @@ -1741,23 +1748,23 @@ ionic_lif_identify(struct ionic_adapter *adapter) ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", - ident->lif.capabilities); + rte_le_to_cpu_64(ident->lif.capabilities)); IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", - ident->lif.eth.max_ucast_filters); + rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", - ident->lif.eth.max_mcast_filters); + rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", - ident->lif.eth.config.features); + rte_le_to_cpu_64(cfg->features)); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]); + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); return 0; } @@ -1766,12 +1773,13 @@ int ionic_lifs_size(struct ionic_adapter *adapter) { struct ionic_identity *ident = &adapter->ident; - uint32_t nintrs, dev_nintrs = ident->dev.nintrs; + union ionic_lif_config *cfg = &ident->lif.eth.config; + uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); adapter->max_ntxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); adapter->max_nrxqs_per_lif = - ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; + rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); nintrs = 1 /* notifyq */; diff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c index 467696a546..3f15a6f2f2 100644 --- a/drivers/net/ionic/ionic_main.c +++ b/drivers/net/ionic/ionic_main.c @@ -340,8 +340,10 @@ ionic_port_identify(struct ionic_adapter *adapter) ioread32(&idev->dev_cmd->data[i]); } - IONIC_PRINT(INFO, "speed %d", ident->port.config.speed); - IONIC_PRINT(INFO, "mtu %d", ident->port.config.mtu); + IONIC_PRINT(INFO, "speed %d", + rte_le_to_cpu_32(ident->port.config.speed)); + IONIC_PRINT(INFO, "mtu %d", + rte_le_to_cpu_32(ident->port.config.mtu)); IONIC_PRINT(INFO, "state %d", ident->port.config.state); IONIC_PRINT(INFO, "an_enable %d", ident->port.config.an_enable); IONIC_PRINT(INFO, "fec_type %d", ident->port.config.fec_type); From patchwork Mon Jan 18 20:34:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86823 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66423A0A03; Mon, 18 Jan 2021 21:35:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 96295140E3F; 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Add a new field to struct ionic_rx_filter to store the CPU-endian match type. Use a local variable for the VLAN when searching the hash table. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_rx_filter.c | 22 +++++++++++----------- drivers/net/ionic/ionic_rx_filter.h | 1 + 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/ionic/ionic_rx_filter.c b/drivers/net/ionic/ionic_rx_filter.c index fe624538df..320b9019b3 100644 --- a/drivers/net/ionic/ionic_rx_filter.c +++ b/drivers/net/ionic/ionic_rx_filter.c @@ -25,7 +25,7 @@ ionic_rx_filter_del(struct ionic_lif *lif, struct ionic_rx_filter *f) .pending_work = true, .cmd.rx_filter_del = { .opcode = IONIC_CMD_RX_FILTER_DEL, - .filter_id = f->filter_id, + .filter_id = rte_cpu_to_le_32(f->filter_id), }, }; @@ -74,25 +74,24 @@ ionic_rx_filter_save(struct ionic_lif *lif, uint32_t flow_id, return -ENOMEM; f->flow_id = flow_id; - f->filter_id = ctx->comp.rx_filter_add.filter_id; + f->filter_id = rte_le_to_cpu_32(ctx->comp.rx_filter_add.filter_id); f->rxq_index = rxq_index; + f->match = rte_le_to_cpu_16(f->cmd.match); memcpy(&f->cmd, &ctx->cmd, sizeof(f->cmd)); - switch (f->cmd.match) { + switch (f->match) { case IONIC_RX_FILTER_MATCH_VLAN: - key = f->cmd.vlan.vlan & IONIC_RX_FILTER_HLISTS_MASK; + key = rte_le_to_cpu_16(f->cmd.vlan.vlan); break; case IONIC_RX_FILTER_MATCH_MAC: memcpy(&key, f->cmd.mac.addr, sizeof(key)); - key &= IONIC_RX_FILTER_HLISTS_MASK; - break; - case IONIC_RX_FILTER_MATCH_MAC_VLAN: - key = f->cmd.mac_vlan.vlan & IONIC_RX_FILTER_HLISTS_MASK; break; default: return -EINVAL; } + key &= IONIC_RX_FILTER_HLISTS_MASK; + rte_spinlock_lock(&lif->rx_filters.lock); LIST_INSERT_HEAD(&lif->rx_filters.by_hash[key], f, by_hash); @@ -111,11 +110,12 @@ ionic_rx_filter_by_vlan(struct ionic_lif *lif, uint16_t vid) { uint32_t key = vid & IONIC_RX_FILTER_HLISTS_MASK; struct ionic_rx_filter *f; + __le16 vid_le = rte_cpu_to_le_16(vid); LIST_FOREACH(f, &lif->rx_filters.by_hash[key], by_hash) { - if (f->cmd.match != IONIC_RX_FILTER_MATCH_VLAN) + if (f->match != IONIC_RX_FILTER_MATCH_VLAN) continue; - if (f->cmd.vlan.vlan == vid) + if (f->cmd.vlan.vlan == vid_le) return f; } @@ -130,7 +130,7 @@ ionic_rx_filter_by_addr(struct ionic_lif *lif, const uint8_t *addr) struct ionic_rx_filter *f; LIST_FOREACH(f, &lif->rx_filters.by_hash[key], by_hash) { - if (f->cmd.match != IONIC_RX_FILTER_MATCH_MAC) + if (f->match != IONIC_RX_FILTER_MATCH_MAC) continue; if (memcmp(addr, f->cmd.mac.addr, RTE_ETHER_ADDR_LEN) == 0) return f; diff --git a/drivers/net/ionic/ionic_rx_filter.h b/drivers/net/ionic/ionic_rx_filter.h index 6204a7b535..e1dd5f910c 100644 --- a/drivers/net/ionic/ionic_rx_filter.h +++ b/drivers/net/ionic/ionic_rx_filter.h @@ -15,6 +15,7 @@ struct ionic_rx_filter { uint32_t flow_id; uint32_t filter_id; uint16_t rxq_index; + uint16_t match; struct ionic_rx_filter_add_cmd cmd; LIST_ENTRY(ionic_rx_filter) by_hash; LIST_ENTRY(ionic_rx_filter) by_id; From patchwork Mon Jan 18 20:34:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86824 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97E31A0A03; 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Mon, 18 Jan 2021 12:35:39 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:34:59 -0800 Message-Id: <20210118203508.1332-5-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 04/13] net/ionic: add an array-size macro X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Using the IONIC_ARRAY_SIZE() macro makes the code clearer. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 10 ++++------ drivers/net/ionic/ionic_ethdev.c | 3 +-- drivers/net/ionic/ionic_lif.c | 9 +++------ drivers/net/ionic/ionic_main.c | 32 +++++++++++--------------------- drivers/net/ionic/ionic_osdep.h | 2 ++ 5 files changed, 21 insertions(+), 35 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index c3016b2d50..c4e871187d 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -87,9 +87,8 @@ void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem) { union ionic_dev_cmd_comp *comp = mem; - unsigned int i; - uint32_t comp_size = sizeof(comp->words) / - sizeof(comp->words[0]); + uint32_t comp_size = IONIC_ARRAY_SIZE(comp->words); + uint32_t i; for (i = 0; i < comp_size; i++) comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]); @@ -98,9 +97,8 @@ ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem) void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) { - unsigned int i; - uint32_t cmd_size = sizeof(cmd->words) / - sizeof(cmd->words[0]); + uint32_t cmd_size = IONIC_ARRAY_SIZE(cmd->words); + uint32_t i; IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd", ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode); diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index a5b2301e46..9238bf7d36 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -207,8 +207,7 @@ static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { tx_desc_data_error)}, }; -#define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ - sizeof(rte_ionic_xstats_strings[0])) +#define IONIC_NB_HW_STATS IONIC_ARRAY_SIZE(rte_ionic_xstats_strings) static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 15e291b604..df8832f908 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -1729,13 +1729,10 @@ ionic_lif_identify(struct ionic_adapter *adapter) struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; union ionic_lif_config *cfg = &ident->lif.eth.config; + uint32_t lif_words = IONIC_ARRAY_SIZE(ident->lif.words); + uint32_t cmd_words = IONIC_ARRAY_SIZE(idev->dev_cmd->data); + uint32_t i, nwords; int err; - unsigned int i; - unsigned int lif_words = sizeof(ident->lif.words) / - sizeof(ident->lif.words[0]); - unsigned int cmd_words = sizeof(idev->dev_cmd->data) / - sizeof(idev->dev_cmd->data[0]); - unsigned int nwords; ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC, IONIC_IDENTITY_VERSION_1); diff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c index 3f15a6f2f2..12b8d682cd 100644 --- a/drivers/net/ionic/ionic_main.c +++ b/drivers/net/ionic/ionic_main.c @@ -263,15 +263,11 @@ ionic_identify(struct ionic_adapter *adapter) { struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; - int err = 0; - uint32_t i; - unsigned int nwords; - uint32_t drv_size = sizeof(ident->drv.words) / - sizeof(ident->drv.words[0]); - uint32_t cmd_size = sizeof(idev->dev_cmd->data) / - sizeof(idev->dev_cmd->data[0]); - uint32_t dev_size = sizeof(ident->dev.words) / - sizeof(ident->dev.words[0]); + uint32_t drv_size = IONIC_ARRAY_SIZE(ident->drv.words); + uint32_t cmd_size = IONIC_ARRAY_SIZE(idev->dev_cmd->data); + uint32_t dev_size = IONIC_ARRAY_SIZE(ident->dev.words); + uint32_t i, nwords; + int err; memset(ident, 0, sizeof(*ident)); @@ -323,12 +319,9 @@ ionic_port_identify(struct ionic_adapter *adapter) { struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; - unsigned int port_words = sizeof(ident->port.words) / - sizeof(ident->port.words[0]); - unsigned int cmd_words = sizeof(idev->dev_cmd->data) / - sizeof(idev->dev_cmd->data[0]); - unsigned int i; - unsigned int nwords; + uint32_t port_words = IONIC_ARRAY_SIZE(ident->port.words); + uint32_t cmd_words = IONIC_ARRAY_SIZE(idev->dev_cmd->data); + uint32_t i, nwords; int err; ionic_dev_cmd_port_identify(idev); @@ -374,12 +367,9 @@ ionic_port_init(struct ionic_adapter *adapter) struct ionic_dev *idev = &adapter->idev; struct ionic_identity *ident = &adapter->ident; char z_name[RTE_MEMZONE_NAMESIZE]; - unsigned int config_words = sizeof(ident->port.config.words) / - sizeof(ident->port.config.words[0]); - unsigned int cmd_words = sizeof(idev->dev_cmd->data) / - sizeof(idev->dev_cmd->data[0]); - unsigned int nwords; - unsigned int i; + uint32_t config_words = IONIC_ARRAY_SIZE(ident->port.config.words); + uint32_t cmd_words = IONIC_ARRAY_SIZE(idev->dev_cmd->data); + uint32_t i, nwords; int err; if (idev->port_info) diff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/net/ionic/ionic_osdep.h index a55d599184..157b0ca516 100644 --- a/drivers/net/ionic/ionic_osdep.h +++ b/drivers/net/ionic/ionic_osdep.h @@ -20,6 +20,8 @@ #include "ionic_logs.h" +#define IONIC_ARRAY_SIZE(_arr) (sizeof(_arr) / sizeof((_arr)[0])) + #define BIT(nr) (1UL << (nr)) #define BIT_ULL(nr) (1ULL << (nr)) From patchwork Mon Jan 18 20:35:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86825 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 336F8A0A03; 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Mon, 18 Jan 2021 12:35:41 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer , Shannon Nelson Date: Mon, 18 Jan 2021 12:35:00 -0800 Message-Id: <20210118203508.1332-6-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 05/13] net/ionic: query firmware for supported queue versions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This allows the PMD to better support FW changes. Signed-off-by: Andrew Boyer Signed-off-by: Shannon Nelson --- drivers/net/ionic/ionic_dev.c | 15 ++++++ drivers/net/ionic/ionic_dev.h | 3 ++ drivers/net/ionic/ionic_lif.c | 95 +++++++++++++++++++++++++++++++++++ drivers/net/ionic/ionic_lif.h | 15 ++++++ 4 files changed, 128 insertions(+) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index c4e871187d..eef015686f 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -273,6 +273,20 @@ ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode) /* LIF commands */ +void +ionic_dev_cmd_queue_identify(struct ionic_dev *idev, + uint16_t lif_type, uint8_t qtype, uint8_t qver) +{ + union ionic_dev_cmd cmd = { + .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, + .q_identify.lif_type = rte_cpu_to_le_16(lif_type), + .q_identify.type = qtype, + .q_identify.ver = qver, + }; + + ionic_dev_cmd_go(idev, &cmd); +} + void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver) { @@ -329,6 +343,7 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq) union ionic_dev_cmd cmd = { .q_init.opcode = IONIC_CMD_Q_INIT, .q_init.type = q->type, + .q_init.ver = qcq->lif->qtype_info[q->type].version, .q_init.index = rte_cpu_to_le_32(q->index), .q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA), .q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 6ee2918959..6931930543 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -227,6 +227,9 @@ void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode); +void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, + uint16_t lif_type, uint8_t qtype, uint8_t qver); + void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver); void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index df8832f908..0d2b3d56a7 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -12,6 +12,21 @@ #include "ionic_rx_filter.h" #include "ionic_rxtx.h" +/* queuetype support level */ +static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = { + [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ + [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ + [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support + * 1 = ... with EQ + * 2 = ... with CMB + */ + [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support + * 1 = ... with Tx SG version 1 + * 2 = ... with EQ + * 3 = ... with CMB + */ +}; + static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); @@ -818,6 +833,81 @@ ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num) return (void *)&vaddr[page_num << PAGE_SHIFT]; } +static void +ionic_lif_queue_identify(struct ionic_lif *lif) +{ + struct ionic_adapter *adapter = lif->adapter; + struct ionic_dev *idev = &adapter->idev; + union ionic_q_identity *q_ident = &adapter->ident.txq; + uint32_t q_words = IONIC_ARRAY_SIZE(q_ident->words); + uint32_t cmd_words = IONIC_ARRAY_SIZE(idev->dev_cmd->data); + uint32_t i, nwords, qtype; + int err; + + for (qtype = 0; qtype < IONIC_ARRAY_SIZE(ionic_qtype_vers); qtype++) { + struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; + + /* Filter out the types this driver knows about */ + switch (qtype) { + case IONIC_QTYPE_ADMINQ: + case IONIC_QTYPE_NOTIFYQ: + case IONIC_QTYPE_RXQ: + case IONIC_QTYPE_TXQ: + break; + default: + continue; + } + + memset(qti, 0, sizeof(*qti)); + + ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC, + qtype, ionic_qtype_vers[qtype]); + err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); + if (err == -EINVAL) { + IONIC_PRINT(ERR, "qtype %d not supported\n", qtype); + continue; + } else if (err == -EIO) { + IONIC_PRINT(ERR, "q_ident failed, older FW\n"); + return; + } else if (err) { + IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n", + qtype, err); + return; + } + + nwords = RTE_MIN(q_words, cmd_words); + for (i = 0; i < nwords; i++) + q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]); + + qti->version = q_ident->version; + qti->supported = q_ident->supported; + qti->features = rte_le_to_cpu_64(q_ident->features); + qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz); + qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz); + qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz); + qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems); + qti->sg_desc_stride = + rte_le_to_cpu_16(q_ident->sg_desc_stride); + + IONIC_PRINT(DEBUG, " qtype[%d].version = %d", + qtype, qti->version); + IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x", + qtype, qti->supported); + IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx", + qtype, qti->features); + IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d", + qtype, qti->desc_sz); + IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d", + qtype, qti->comp_sz); + IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d", + qtype, qti->sg_desc_sz); + IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d", + qtype, qti->max_sg_elems); + IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d", + qtype, qti->sg_desc_stride); + } +} + int ionic_lif_alloc(struct ionic_lif *lif) { @@ -833,6 +923,8 @@ ionic_lif_alloc(struct ionic_lif *lif) IONIC_PRINT(DEBUG, "LIF: %s", lif->name); + ionic_lif_queue_identify(lif); + IONIC_PRINT(DEBUG, "Allocating Lif Info"); rte_spinlock_init(&lif->adminq_lock); @@ -1261,6 +1353,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = rte_cpu_to_le_32(q->index), .intr_index = rte_cpu_to_le_16(qcq->intr.index), .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | @@ -1365,6 +1458,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = rte_cpu_to_le_32(q->index), .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA), @@ -1411,6 +1505,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq) .cmd.q_init = { .opcode = IONIC_CMD_Q_INIT, .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = rte_cpu_to_le_32(q->index), .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA), diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index d245c6da01..bf5637afce 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -73,6 +73,17 @@ struct ionic_qcq { #define IONIC_Q_TO_TX_STATS(q) (&IONIC_Q_TO_QCQ(q)->stats.tx) #define IONIC_Q_TO_RX_STATS(q) (&IONIC_Q_TO_QCQ(q)->stats.rx) +struct ionic_qtype_info { + uint8_t version; + uint8_t supported; + uint64_t features; + uint16_t desc_sz; + uint16_t comp_sz; + uint16_t sg_desc_sz; + uint16_t max_sg_elems; + uint16_t sg_desc_stride; +}; + #define IONIC_LIF_F_INITED BIT(0) #define IONIC_LIF_F_LINK_CHECK_NEEDED BIT(1) #define IONIC_LIF_F_UP BIT(2) @@ -112,6 +123,10 @@ struct ionic_lif { struct ionic_lif_info *info; rte_iova_t info_pa; const struct rte_memzone *info_z; + + struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; + uint8_t qtype_ver[IONIC_QTYPE_MAX]; + struct rte_eth_stats stats_base; struct ionic_lif_stats lif_stats_base; }; From patchwork Mon Jan 18 20:35:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86826 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3EA4A0A03; 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Mon, 18 Jan 2021 12:35:43 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:35:01 -0800 Message-Id: <20210118203508.1332-7-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 06/13] net/ionic: clean up Tx queue version support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The ionic PMD only supports TX queue version 1 or greater. Version 1 introduced a new SGL format with support for more fragments per descriptor. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.h | 2 +- drivers/net/ionic/ionic_ethdev.c | 8 ++++---- drivers/net/ionic/ionic_lif.c | 7 ++++++- drivers/net/ionic/ionic_rxtx.c | 8 ++++---- 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 6931930543..ea89218662 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -107,7 +107,7 @@ static inline void ionic_struct_size_checks(void) /* I/O */ RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); - RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc) != 128); + RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256); RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index 9238bf7d36..bc9a946ab5 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -70,12 +70,12 @@ static const struct rte_eth_desc_lim rx_desc_lim = { .nb_align = 1, }; -static const struct rte_eth_desc_lim tx_desc_lim = { +static const struct rte_eth_desc_lim tx_desc_lim_v1 = { .nb_max = IONIC_MAX_RING_DESC, .nb_min = IONIC_MIN_RING_DESC, .nb_align = 1, - .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, - .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, + .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1, + .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1, }; static const struct eth_dev_ops ionic_eth_dev_ops = { @@ -440,7 +440,7 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, 0; dev_info->rx_desc_lim = rx_desc_lim; - dev_info->tx_desc_lim = tx_desc_lim; + dev_info->tx_desc_lim = tx_desc_lim_v1; /* Driver-preferred Rx/Tx parameters */ dev_info->default_rxportconf.burst_size = 32; diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 0d2b3d56a7..ec35d81cd5 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -761,7 +761,7 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs, ntxq_descs, sizeof(struct ionic_txq_desc), sizeof(struct ionic_txq_comp), - sizeof(struct ionic_txq_sg_desc), + sizeof(struct ionic_txq_sg_desc_v1), &lif->txqcqs[index]); if (err) return err; @@ -925,6 +925,11 @@ ionic_lif_alloc(struct ionic_lif *lif) ionic_lif_queue_identify(lif); + if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) { + IONIC_PRINT(ERR, "FW too old, please upgrade"); + return -ENXIO; + } + IONIC_PRINT(DEBUG, "Allocating Lif Info"); rte_spinlock_init(&lif->adminq_lock); diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index 5d0e9d5d5a..c3a44faa21 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -311,9 +311,9 @@ static struct ionic_txq_desc * ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem) { struct ionic_txq_desc *desc_base = q->base; - struct ionic_txq_sg_desc *sg_desc_base = q->sg_base; + struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base; struct ionic_txq_desc *desc = &desc_base[q->head_idx]; - struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx]; + struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx]; *elem = sg_desc->elems; return desc; @@ -446,9 +446,9 @@ ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, uint64_t offloads, bool not_xmit_more) { struct ionic_txq_desc *desc_base = q->base; - struct ionic_txq_sg_desc *sg_desc_base = q->sg_base; + struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base; struct ionic_txq_desc *desc = &desc_base[q->head_idx]; - struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx]; + struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx]; struct ionic_txq_sg_elem *elem = sg_desc->elems; struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); struct rte_mbuf *txm_seg; From patchwork Mon Jan 18 20:35:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86827 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0516CA0A03; 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Mon, 18 Jan 2021 12:35:45 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer , Neel Patel Date: Mon, 18 Jan 2021 12:35:02 -0800 Message-Id: <20210118203508.1332-8-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 07/13] net/ionic: inline queue flush function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is hot-path function. Signed-off-by: Andrew Boyer Signed-off-by: Neel Patel --- drivers/net/ionic/ionic_dev.c | 6 ------ drivers/net/ionic/ionic_dev.h | 9 ++++++++- drivers/net/ionic/ionic_osdep.h | 1 - 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index eef015686f..fcb3df482a 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -459,12 +459,6 @@ ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa) q->sg_base_pa = base_pa; } -void -ionic_q_flush(struct ionic_queue *q) -{ - writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db); -} - void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, void *cb_arg) diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index ea89218662..55a56434fd 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -254,7 +254,6 @@ int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, size_t desc_size, size_t sg_desc_size); void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); -void ionic_q_flush(struct ionic_queue *q); void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, void *cb_arg); uint32_t ionic_q_space_avail(struct ionic_queue *q); @@ -262,6 +261,14 @@ bool ionic_q_has_space(struct ionic_queue *q, uint32_t want); void ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index, uint32_t stop_index, void *service_cb_arg); +static inline void +ionic_q_flush(struct ionic_queue *q) +{ + uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; + + rte_write64(val, q->db); +} + int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); #endif /* _IONIC_DEV_H_ */ diff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/net/ionic/ionic_osdep.h index 157b0ca516..d46687b32f 100644 --- a/drivers/net/ionic/ionic_osdep.h +++ b/drivers/net/ionic/ionic_osdep.h @@ -45,6 +45,5 @@ typedef uint64_t __le64; #define ioread32(reg) rte_read32(reg) #define iowrite8(value, reg) rte_write8(value, reg) #define iowrite32(value, reg) rte_write32(value, reg) -#define writeq(value, reg) rte_write64(value, reg) #endif From patchwork Mon Jan 18 20:35:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86828 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2038A0A03; Mon, 18 Jan 2021 21:36:30 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F2D80140E72; Mon, 18 Jan 2021 21:35:49 +0100 (CET) Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by mails.dpdk.org (Postfix) with ESMTP id 7525D140E6B for ; Mon, 18 Jan 2021 21:35:48 +0100 (CET) Received: by mail-pj1-f44.google.com with SMTP id l23so10619146pjg.1 for ; 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Mon, 18 Jan 2021 12:35:47 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:47 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:35:03 -0800 Message-Id: <20210118203508.1332-9-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 08/13] net/ionic: inline queue space function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is a hot-path function. Remove ionic_q_has_space() while here. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.c | 21 +-------------------- drivers/net/ionic/ionic_dev.h | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c index fcb3df482a..e847741632 100644 --- a/drivers/net/ionic/ionic_dev.c +++ b/drivers/net/ionic/ionic_dev.c @@ -474,25 +474,6 @@ ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, ionic_q_flush(q); } -uint32_t -ionic_q_space_avail(struct ionic_queue *q) -{ - uint32_t avail = q->tail_idx; - - if (q->head_idx >= avail) - avail += q->num_descs - q->head_idx - 1; - else - avail -= q->head_idx + 1; - - return avail; -} - -bool -ionic_q_has_space(struct ionic_queue *q, uint32_t want) -{ - return ionic_q_space_avail(q) >= want; -} - void ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index, uint32_t stop_index, void *service_cb_arg) @@ -561,7 +542,7 @@ ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) rte_spinlock_lock(&lif->adminq_lock); - if (!ionic_q_has_space(adminq, 1)) { + if (ionic_q_space_avail(adminq) < 1) { err = -ENOSPC; goto err_out; } diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 55a56434fd..8847d6cad4 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -256,11 +256,22 @@ void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb, void *cb_arg); -uint32_t ionic_q_space_avail(struct ionic_queue *q); -bool ionic_q_has_space(struct ionic_queue *q, uint32_t want); void ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index, uint32_t stop_index, void *service_cb_arg); +static inline uint32_t +ionic_q_space_avail(struct ionic_queue *q) +{ + uint32_t avail = q->tail_idx; + + if (q->head_idx >= avail) + avail += q->num_descs - q->head_idx - 1; + else + avail -= q->head_idx + 1; + + return avail; +} + static inline void ionic_q_flush(struct ionic_queue *q) { From patchwork Mon Jan 18 20:35:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86829 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8ABE6A0A03; Mon, 18 Jan 2021 21:36:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 54ABE140E91; Mon, 18 Jan 2021 21:35:51 +0100 (CET) Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mails.dpdk.org (Postfix) with ESMTP id 283B2140E74 for ; Mon, 18 Jan 2021 21:35:50 +0100 (CET) Received: by mail-pj1-f50.google.com with SMTP id x20so5223128pjh.3 for ; Mon, 18 Jan 2021 12:35:50 -0800 (PST) DKIM-Signature: v=1; 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Mon, 18 Jan 2021 12:35:49 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:48 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:35:04 -0800 Message-Id: <20210118203508.1332-10-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 09/13] net/ionic: observe endiannness in ioread/iowrite X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The IONIC FW is little-endian. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_dev.h | 2 +- drivers/net/ionic/ionic_osdep.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h index 8847d6cad4..bacbe3f053 100644 --- a/drivers/net/ionic/ionic_dev.h +++ b/drivers/net/ionic/ionic_dev.h @@ -277,7 +277,7 @@ ionic_q_flush(struct ionic_queue *q) { uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; - rte_write64(val, q->db); + rte_write64(rte_cpu_to_le_64(val), q->db); } int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); diff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/net/ionic/ionic_osdep.h index d46687b32f..b20c1cc8d5 100644 --- a/drivers/net/ionic/ionic_osdep.h +++ b/drivers/net/ionic/ionic_osdep.h @@ -42,8 +42,8 @@ typedef uint32_t __le32; typedef uint64_t __le64; #define ioread8(reg) rte_read8(reg) -#define ioread32(reg) rte_read32(reg) +#define ioread32(reg) rte_read32(rte_le_to_cpu_32(reg)) #define iowrite8(value, reg) rte_write8(value, reg) -#define iowrite32(value, reg) rte_write32(value, reg) +#define iowrite32(value, reg) rte_write32(rte_cpu_to_le_32(value), reg) #endif From patchwork Mon Jan 18 20:35:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86830 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AEF3A0A03; Mon, 18 Jan 2021 21:36:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 936C9140EAB; Mon, 18 Jan 2021 21:35:54 +0100 (CET) Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) by mails.dpdk.org (Postfix) with ESMTP id 1933E140E9D for ; Mon, 18 Jan 2021 21:35:52 +0100 (CET) Received: by mail-pl1-f180.google.com with SMTP id q4so9242516plr.7 for ; Mon, 18 Jan 2021 12:35:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IeQwsR1SALNR5wPJJmZgHgCcB84YinyMJIeCE8CLDkw=; b=gPAhuQXvyAphp9xzmkXuofl6C13rRb1FdLq/mI4V8IHXfB+5Ljm8+/5laIKHjE1Q4t uzCan69wypZ045C+Lg/HYMUyLB3ukcFiz6h6C6haEyRiBjGeop3ajFWjQpKb7i+bz+7a Eo1xRD1gjFdciTCxfog7DcZOFX60heBp1BxZ6ffWiGkB5kxb0jzzVb/sBRpa88RQWFFa ty1rNObUF3lpngS4BIlXsba4WMz+hW0ZTd0VDaFMug2KuY708ZuBSCVsH5xgVxV4Ju91 U0aTi4/ERh6PhLTbWwMOWr7HqbBHdH1dlO3q4G0Mi+WQbHVBhM9hCneW3oWcJEbpUvcu 8AZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IeQwsR1SALNR5wPJJmZgHgCcB84YinyMJIeCE8CLDkw=; b=frc13BDTd69X652y9R3V9bZEaKf1bVRmx8mtdZRawgEFhdp68n7qr3b/6lXP7yOEAD JXQzVSvhp6EDxpI74fmEG94WoeVRb/yCsUqgvKll7EhInGEM2Ly4BFMMgkUotKQ+J2RA 6DphmHUyffHwsj5ugwhDn+MkTYlyhR6/VuQBLiYafLexKElekUhntnH/5lfwjk8YTQ1+ IVTB7DFg7ZUIQQA+Mx83S1XNg2R6AUNU9JRL5X407AIjMbhE7hcfaUIpghdXmYIJEQXk PXjalu+suiW6m84kfM4w9pqpyiHoYFseArPkPPEr4cRDaQiOadPJDv1l9Av1jBjEuMv1 /3cQ== X-Gm-Message-State: AOAM531l+P5PcEx4a3mZY9I+8cQ+wYURyAl+1dxdM5BpfXeH+e8yuo1w FBe0EAZadsxo/He/D1uT05+fjGeSxqQN4g== X-Google-Smtp-Source: ABdhPJwu+WRMwqUMnFxlIFxQ4gWK3O+aknwbf6ySZ/nrulJIOXJwpyUX5/jnRMcCRjZ/6NflUXli6A== X-Received: by 2002:a17:902:8a88:b029:dc:f3:6db2 with SMTP id p8-20020a1709028a88b02900dc00f36db2mr1222896plo.2.1611002151152; Mon, 18 Jan 2021 12:35:51 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:50 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer , stable@dpdk.org Date: Mon, 18 Jan 2021 12:35:05 -0800 Message-Id: <20210118203508.1332-11-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 10/13] net/ionic: fix to allow separate L3 and L4 csum offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DTS, at least, expects to be able to specify L4 checksum offload without L3 csum offload. Split up the flag checks. Fixes: a27d901331da ("net/ionic: add Rx and Tx handling") Cc: stable@dpdk.org Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_rxtx.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index c3a44faa21..d0f8954753 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -460,18 +460,22 @@ ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, uint8_t flags = 0; if ((ol_flags & PKT_TX_IP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { + (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; - if (((ol_flags & PKT_TX_TCP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || - ((ol_flags & PKT_TX_UDP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) - flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; - } else { - stats->no_csum++; } + if (((ol_flags & PKT_TX_TCP_CKSUM) && + (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + ((ol_flags & PKT_TX_UDP_CKSUM) && + (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) { + opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; + flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; + } + + if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) + stats->no_csum++; + has_vlan = (ol_flags & PKT_TX_VLAN_PKT); encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) && From patchwork Mon Jan 18 20:35:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86831 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 471D9A0A03; Mon, 18 Jan 2021 21:36:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3718140E9B; Mon, 18 Jan 2021 21:35:55 +0100 (CET) Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) by mails.dpdk.org (Postfix) with ESMTP id D7BF8140EA3 for ; Mon, 18 Jan 2021 21:35:53 +0100 (CET) Received: by mail-pg1-f177.google.com with SMTP id n25so11658770pgb.0 for ; Mon, 18 Jan 2021 12:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eZHLIajdEoFA3Nym+Z5BFhCDgWh82946qXblVzvYSvA=; b=x9YCfjcT/W/SWF9m2z/JA+OtaxInk4dJFRZcaWSypXy0A3DTfRviogk/7gqaUMy/Bz Iy2DcZM5j6Dn5gUmQ0Na30cXaDW6U7VG/59V5geLt/DwYPXE8lDSiEaIxD8rbZxCXqn4 zHB2magFPL3tTqXpX6XI+MR/c/HiZYs9r3+TAAQHaqBtM9zxw5M6CuRom8ozd74HOGtU gPqP0PQ1JfITbYS+OjBmOY+PoWNoKzdNwmvNaeCJlajl1snu2CJv6BN+r8Uf0YaaqY/G z1Cz5gZ2s3pX5Gvkro/c/bTiNYZywVlq1zQKucwHiytWaSyJMafvUtdxrFlcMvCiwITJ Trrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eZHLIajdEoFA3Nym+Z5BFhCDgWh82946qXblVzvYSvA=; b=Dl2bcp2eFyg/N70DHuS9uLdD0gjdBKywpRzEHix2H4R0ILMonoO/iDsL90NAodv5FV mph179vj95OiqRB6EGTuorAyBm63doXYJGQgI4rCHllDUKrz5nr7wd/L3QiL/CdbOjOW kMP0cuftM97nJ/HL4Ek8naX4d5hxEKCAJhYt/Y4sLsCw5FZlrH+TorG1UBKjrCh7jSwB eiC3niZmLQTWXk/mpjlOnKkNKjqModyJJioL0go6ef/saeb11aP3iTcZb8wRI4BLKHt3 FKzQIjijEr2dIaHT7YdjPjyqD6nV2tN7ESvq8HDZk9dMHuTuGE4o2rCvU1RZwYFzqKSh Cc3A== X-Gm-Message-State: AOAM530UaGPuUAw/pv+qvra4Cwcbr9BE1Wzam/lhowU8v5IeW36mWnXN AGW3Mih1KPrQIcDFO9psFuZWErBVbD5rvw== X-Google-Smtp-Source: ABdhPJzBX6cu2n6tMwsZOz8w65SsdxnNQmH71sv5H9lStBhB/BGiRBj5DqDAKBtu4nytpuBBLD2UgA== X-Received: by 2002:a62:b60c:0:b029:1ae:6d91:4eb6 with SMTP id j12-20020a62b60c0000b02901ae6d914eb6mr1158160pff.33.1611002152897; Mon, 18 Jan 2021 12:35:52 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:52 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer Date: Mon, 18 Jan 2021 12:35:06 -0800 Message-Id: <20210118203508.1332-12-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 11/13] net/ionic: convert per-queue offloads into queue flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This will conserve resources by reducing struct ionic_qcq. Saving a cacheline or two in the rxq and txq structs helps when running in embedded configurations where CPU cache space is at a premium. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_lif.h | 4 +++- drivers/net/ionic/ionic_rxtx.c | 35 +++++++++++++++++++--------------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index bf5637afce..8f01aefd60 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -49,10 +49,12 @@ struct ionic_rx_stats { #define IONIC_QCQ_F_INITED BIT(0) #define IONIC_QCQ_F_SG BIT(1) #define IONIC_QCQ_F_DEFERRED BIT(4) +#define IONIC_QCQ_F_CSUM_L3 BIT(7) +#define IONIC_QCQ_F_CSUM_UDP BIT(8) +#define IONIC_QCQ_F_CSUM_TCP BIT(9) /* Queue / Completion Queue */ struct ionic_qcq { - uint64_t offloads; struct ionic_queue q; /**< Queue */ struct ionic_cq cq; /**< Completion Queue */ struct ionic_lif *lif; /**< LIF */ diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index d0f8954753..918701f463 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -63,7 +63,7 @@ ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct ionic_queue *q = &txq->q; qinfo->nb_desc = q->num_descs; - qinfo->conf.offloads = txq->offloads; + qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads; qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED; } @@ -200,7 +200,13 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id, if (tx_conf->tx_deferred_start) txq->flags |= IONIC_QCQ_F_DEFERRED; - txq->offloads = offloads; + /* Convert the offload flags into queue flags */ + if (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_L3; + if (offloads & DEV_TX_OFFLOAD_TCP_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_TCP; + if (offloads & DEV_TX_OFFLOAD_UDP_CKSUM) + txq->flags |= IONIC_QCQ_F_CSUM_UDP; eth_dev->data->tx_queues[tx_queue_id] = txq; @@ -320,9 +326,10 @@ ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem) } static int -ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, - uint64_t offloads __rte_unused, bool not_xmit_more) +ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, + bool not_xmit_more) { + struct ionic_queue *q = &txq->q; struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); struct ionic_txq_desc *desc; struct ionic_txq_sg_elem *elem; @@ -442,9 +449,10 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, } static int -ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, - uint64_t offloads, bool not_xmit_more) +ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm, + bool not_xmit_more) { + struct ionic_queue *q = &txq->q; struct ionic_txq_desc *desc_base = q->base; struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base; struct ionic_txq_desc *desc = &desc_base[q->head_idx]; @@ -460,15 +468,15 @@ ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, uint8_t flags = 0; if ((ol_flags & PKT_TX_IP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { + (txq->flags & IONIC_QCQ_F_CSUM_L3)) { opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; } if (((ol_flags & PKT_TX_TCP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + (txq->flags & IONIC_QCQ_F_CSUM_TCP)) || ((ol_flags & PKT_TX_UDP_CKSUM) && - (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) { + (txq->flags & IONIC_QCQ_F_CSUM_UDP))) { opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; } @@ -536,10 +544,9 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG) - err = ionic_tx_tso(q, tx_pkts[nb_tx], txq->offloads, - last); + err = ionic_tx_tso(txq, tx_pkts[nb_tx], last); else - err = ionic_tx(q, tx_pkts[nb_tx], txq->offloads, last); + err = ionic_tx(txq, tx_pkts[nb_tx], last); if (err) { stats->drop += nb_pkts - nb_tx; if (nb_tx > 0) @@ -621,7 +628,7 @@ ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, qinfo->scattered_rx = dev->data->scattered_rx; qinfo->nb_desc = q->num_descs; qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED; - qinfo->conf.offloads = rxq->offloads; + qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; } static void __rte_cold @@ -724,8 +731,6 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, if (rx_conf->rx_deferred_start) rxq->flags |= IONIC_QCQ_F_DEFERRED; - rxq->offloads = offloads; - eth_dev->data->rx_queues[rx_queue_id] = rxq; return 0; From patchwork Mon Jan 18 20:35:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86832 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 55547A0A03; Mon, 18 Jan 2021 21:37:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 61244140EBB; Mon, 18 Jan 2021 21:35:57 +0100 (CET) Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) by mails.dpdk.org (Postfix) with ESMTP id AFCB8140E9B for ; Mon, 18 Jan 2021 21:35:55 +0100 (CET) Received: by mail-pl1-f169.google.com with SMTP id e9so5087501plh.3 for ; Mon, 18 Jan 2021 12:35:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; 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Mon, 18 Jan 2021 12:35:54 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:54 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer , stable@dpdk.org Date: Mon, 18 Jan 2021 12:35:07 -0800 Message-Id: <20210118203508.1332-13-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 12/13] net/ionic: fix up function attribute tags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" One function marked cold is in the hot path. Make sure to always inline hot path functions. Fixes: a27d901331da ("net/ionic: add Rx and Tx handling") Cc: stable@dpdk.org Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_rxtx.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index 918701f463..f49a7cdb0e 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -67,7 +67,7 @@ ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED; } -static inline void __rte_cold +static __rte_always_inline void ionic_tx_flush(struct ionic_cq *cq) { struct ionic_queue *q = cq->bound_q; @@ -448,7 +448,7 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, return 0; } -static int +static __rte_always_inline int ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm, bool not_xmit_more) { @@ -736,7 +736,7 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, return 0; } -static void +static __rte_always_inline void ionic_rx_clean(struct ionic_queue *q, uint32_t q_desc_index, uint32_t cq_desc_index, void *cb_arg, void *service_cb_arg) @@ -897,7 +897,7 @@ ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index, ionic_q_post(q, true, ionic_rx_clean, mbuf); } -static int __rte_cold +static __rte_always_inline int ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len) { struct ionic_queue *q = &rxq->q; @@ -1013,7 +1013,7 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) return 0; } -static inline void __rte_cold +static __rte_always_inline void ionic_rxq_service(struct ionic_cq *cq, uint32_t work_to_do, void *service_cb_arg) { From patchwork Mon Jan 18 20:35:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Boyer X-Patchwork-Id: 86833 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD090A0A03; Mon, 18 Jan 2021 21:37:07 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DDA93140EA6; Mon, 18 Jan 2021 21:36:00 +0100 (CET) Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mails.dpdk.org (Postfix) with ESMTP id 8BC51140EBD for ; Mon, 18 Jan 2021 21:35:57 +0100 (CET) Received: by mail-pj1-f53.google.com with SMTP id cq1so10289568pjb.4 for ; Mon, 18 Jan 2021 12:35:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g3NiWdwLg9vTUwSHmEQgrP78GNOtC7XVo7532k4wI0Y=; b=UBzDW58uqEJtYt1FGcHAUbWd8cMAjRYTkL1boxiYFRRKe6BVPqWxz5A2YX0CVkHgzP pmER+NECaG5siudMOfFFvVOIyukDKuPLfhrFnVSZ7zcQjQIfPs3IpCb+AQXrQJqNAUmx 5w3LpjNlw8FSf51LFim/BFf4GmPRIdVwPWiuvYfcOMIqp2jzduiW8xEYTglrIEhLoqIx tNGD+pBu9ELOtqhkVwBdu2smz9Bn7zIbHYMhtdj6KQpYcr7Bj23FUhQtmYMJuEJgZTB9 8LVglLgiWLUX6wB546Rrck2xT6ZwXl+cL4GhoYVpfFkL5bleB7HVCAX5Rivm0tib3jTH OWoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g3NiWdwLg9vTUwSHmEQgrP78GNOtC7XVo7532k4wI0Y=; b=iDCGqcKzQ4pzVM7e95ClgRE9H4Es3aBRfBq4VP0BoBmV9v/n7f5cdfOnI03dCINyXx nem7fRmNgzOp+RcU/Rb8izCZjsbjyduiNjFvGvU8xS0kWsofeBKwOv3+VmXRzqTv94gS uKQysWBbk4JLQFiXC/O6Ir6cse8x7Zu3abDP0CtjqY4re7mjc8OPJ/F+CQAvsuEc23x9 R1DyiKMPr7+a3FZEAm9xVUEeHEjax6Tx6pMchdVq6f7ZZYMqzv/OD2iWlOL8GyvzK7MQ WKhXXQ7mdqgtXSG1mFB48ycSicsXG6f/jqdGbUIGXREG3Vxyp89UvFztEoWz1C2O4lHe +reg== X-Gm-Message-State: AOAM530HT2WM822WPbs1VQbbtl1k2b2f9lFWCKglsLFbxvL9DSymFH8Z p0J4LxXZ8qXnh68M8boEWQY4Ilut8lwMSg== X-Google-Smtp-Source: ABdhPJw2D8WT5erjx4Xqu8AuhmJgrqFk88X1Bhh6FrNQNg7c8SpaOXWmkC7LCvEeneUUImYIcUFSbA== X-Received: by 2002:a17:90b:513:: with SMTP id r19mr1192547pjz.38.1611002156614; Mon, 18 Jan 2021 12:35:56 -0800 (PST) Received: from driver-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id g201sm795160pfb.81.2021.01.18.12.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 12:35:56 -0800 (PST) From: Andrew Boyer To: dev@dpdk.org Cc: Alfredo Cardigliano , Andrew Boyer , stable@dpdk.org Date: Mon, 18 Jan 2021 12:35:08 -0800 Message-Id: <20210118203508.1332-14-aboyer@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118203508.1332-1-aboyer@pensando.io> References: <20210118203508.1332-1-aboyer@pensando.io> Subject: [dpdk-dev] [PATCH 13/13] net/ionic: fix address handling in transmit code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Don't assume standard headroom. Use helper variables to improve readability. Fixes: a27d901331da ("net/ionic: add Rx and Tx handling") Cc: stable@dpdk.org Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic_rxtx.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index f49a7cdb0e..b8b3364d11 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -334,7 +334,8 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, struct ionic_txq_desc *desc; struct ionic_txq_sg_elem *elem; struct rte_mbuf *txm_seg; - uint64_t desc_addr = 0; + rte_iova_t data_iova; + uint64_t desc_addr = 0, next_addr; uint16_t desc_len = 0; uint8_t desc_nsge; uint32_t hdrlen; @@ -371,6 +372,7 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, seglen = hdrlen + mss; left = txm->data_len; + data_iova = rte_mbuf_data_iova(txm); desc = ionic_tx_tso_next(q, &elem); start = true; @@ -380,7 +382,7 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, while (left > 0) { len = RTE_MIN(seglen, left); frag_left = seglen - len; - desc_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm)); + desc_addr = rte_cpu_to_le_64(data_iova + offset); desc_len = len; desc_nsge = 0; left -= len; @@ -404,24 +406,23 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, txm_seg = txm->next; while (txm_seg != NULL) { offset = 0; + data_iova = rte_mbuf_data_iova(txm_seg); left = txm_seg->data_len; stats->frags++; while (left > 0) { - rte_iova_t data_iova; - data_iova = rte_mbuf_data_iova(txm_seg); - elem->addr = rte_cpu_to_le_64(data_iova) + offset; + next_addr = rte_cpu_to_le_64(data_iova + offset); if (frag_left > 0) { len = RTE_MIN(frag_left, left); frag_left -= len; + elem->addr = next_addr; elem->len = len; elem++; desc_nsge++; } else { len = RTE_MIN(mss, left); frag_left = mss - len; - data_iova = rte_mbuf_data_iova(txm_seg); - desc_addr = rte_cpu_to_le_64(data_iova); + desc_addr = next_addr; desc_len = len; desc_nsge = 0; } @@ -429,6 +430,7 @@ ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm, offset += len; if (txm_seg->next != NULL && frag_left > 0) continue; + done = (txm_seg->next == NULL && left == 0); ionic_tx_tso_post(q, desc, txm_seg, desc_addr, desc_nsge, desc_len, @@ -463,7 +465,7 @@ ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm, bool encap; bool has_vlan; uint64_t ol_flags = txm->ol_flags; - uint64_t addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm)); + uint64_t addr; uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; uint8_t flags = 0; @@ -493,6 +495,8 @@ ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm, flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; + addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm)); + desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr); desc->len = txm->data_len; desc->vlan_tci = txm->vlan_tci;