From patchwork Tue Jan 12 02:57:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86359 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3F38A04B5; Tue, 12 Jan 2021 03:57:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6938140D00; Tue, 12 Jan 2021 03:57:43 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 5F4DD140CAF for ; Tue, 12 Jan 2021 03:57:42 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9E87101E; Mon, 11 Jan 2021 18:57:41 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 96E433F66E; Mon, 11 Jan 2021 18:57:38 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Ruifeng Wang , Jan Viktorin , Bruce Richardson , Vladimir Medvedkin Cc: dev@dpdk.org, pbhagavatula@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com Date: Tue, 12 Jan 2021 02:57:04 +0000 Message-Id: <20210112025709.1121523-2-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 1/5] lpm: add sve support for lookup on Arm platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added new path to do lpm4 lookup by using scalable vector extension. The SVE path will be selected if compiler has flag SVE set. Signed-off-by: Ruifeng Wang --- v2: Fixed tbl8 group index calculation. (Vladimir) lib/librte_eal/arm/include/rte_vect.h | 3 + lib/librte_lpm/meson.build | 2 +- lib/librte_lpm/rte_lpm.h | 4 ++ lib/librte_lpm/rte_lpm_sve.h | 83 +++++++++++++++++++++++++++ 4 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 lib/librte_lpm/rte_lpm_sve.h diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index a739e6e66..093e9122a 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -9,6 +9,9 @@ #include "generic/rte_vect.h" #include "rte_debug.h" #include "arm_neon.h" +#ifdef __ARM_FEATURE_SVE +#include +#endif #ifdef __cplusplus extern "C" { diff --git a/lib/librte_lpm/meson.build b/lib/librte_lpm/meson.build index 6cfc083c5..f93c86640 100644 --- a/lib/librte_lpm/meson.build +++ b/lib/librte_lpm/meson.build @@ -5,6 +5,6 @@ sources = files('rte_lpm.c', 'rte_lpm6.c') headers = files('rte_lpm.h', 'rte_lpm6.h') # since header files have different names, we can install all vector headers # without worrying about which architecture we actually need -headers += files('rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h') +headers += files('rte_lpm_altivec.h', 'rte_lpm_neon.h', 'rte_lpm_sse.h', 'rte_lpm_sve.h') deps += ['hash'] deps += ['rcu'] diff --git a/lib/librte_lpm/rte_lpm.h b/lib/librte_lpm/rte_lpm.h index 1afe55cdc..28b57683b 100644 --- a/lib/librte_lpm/rte_lpm.h +++ b/lib/librte_lpm/rte_lpm.h @@ -402,7 +402,11 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv); #if defined(RTE_ARCH_ARM) +#ifdef __ARM_FEATURE_SVE +#include "rte_lpm_sve.h" +#else #include "rte_lpm_neon.h" +#endif #elif defined(RTE_ARCH_PPC_64) #include "rte_lpm_altivec.h" #else diff --git a/lib/librte_lpm/rte_lpm_sve.h b/lib/librte_lpm/rte_lpm_sve.h new file mode 100644 index 000000000..2e319373e --- /dev/null +++ b/lib/librte_lpm/rte_lpm_sve.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Arm Limited + */ + +#ifndef _RTE_LPM_SVE_H_ +#define _RTE_LPM_SVE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +__rte_internal +static void +__rte_lpm_lookup_vec(const struct rte_lpm *lpm, const uint32_t *ips, + uint32_t *__rte_restrict next_hops, const uint32_t n) +{ + uint32_t i = 0; + svuint32_t v_ip, v_idx, v_tbl24, v_tbl8, v_hop; + svuint32_t v_mask_xv, v_mask_v, v_mask_hop; + svbool_t pg = svwhilelt_b32(i, n); + svbool_t pv; + + do { + v_ip = svld1(pg, &ips[i]); + /* Get indices for tbl24[] */ + v_idx = svlsr_x(pg, v_ip, 8); + /* Extract values from tbl24[] */ + v_tbl24 = svld1_gather_index(pg, (const uint32_t *)lpm->tbl24, + v_idx); + + /* Create mask with valid set */ + v_mask_v = svdup_u32_z(pg, RTE_LPM_LOOKUP_SUCCESS); + /* Create mask with valid and valid_group set */ + v_mask_xv = svdup_u32_z(pg, RTE_LPM_VALID_EXT_ENTRY_BITMASK); + /* Create predicate for tbl24 entries: (valid && !valid_group) */ + pv = svcmpeq(pg, svand_z(pg, v_tbl24, v_mask_xv), v_mask_v); + /* Create mask for next_hop in table entry */ + v_mask_hop = svdup_u32_z(pg, 0x00ffffff); + /* Extract next_hop and write back */ + v_hop = svand_x(pv, v_tbl24, v_mask_hop); + svst1(pv, &next_hops[i], v_hop); + + /* Update predicate for tbl24 entries: (valid && valid_group) */ + pv = svcmpeq(pg, svand_z(pg, v_tbl24, v_mask_xv), v_mask_xv); + /* Compute tbl8 index */ + v_idx = svand_x(pv, v_tbl24, svdup_u32_z(pv, 0xffffff)); + v_idx = svmul_x(pv, v_idx, RTE_LPM_TBL8_GROUP_NUM_ENTRIES); + v_idx = svadd_x(pv, svand_x(pv, v_ip, svdup_u32_z(pv, 0xff)), + v_idx); + /* Extract values from tbl8[] */ + v_tbl8 = svld1_gather_index(pv, (const uint32_t *)lpm->tbl8, + v_idx); + /* Update predicate for tbl8 entries: (valid) */ + pv = svcmpeq(pv, svand_z(pv, v_tbl8, v_mask_v), v_mask_v); + /* Extract next_hop and write back */ + v_hop = svand_x(pv, v_tbl8, v_mask_hop); + svst1(pv, &next_hops[i], v_hop); + + i += svlen(v_ip); + pg = svwhilelt_b32(i, n); + } while (svptest_any(svptrue_b32(), pg)); +} + +static inline void +rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], + uint32_t defv) +{ + uint32_t i, ips[4]; + + vst1q_s32((int32_t *)ips, ip); + for (i = 0; i < 4; i++) + hop[i] = defv; + + __rte_lpm_lookup_vec(lpm, ips, hop, 4); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_SVE_H_ */ From patchwork Tue Jan 12 02:57:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86360 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53F9BA04B5; Tue, 12 Jan 2021 03:57:59 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3B6C8140CFC; Tue, 12 Jan 2021 03:57:59 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id EF7F1140CFC; Tue, 12 Jan 2021 03:57:57 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7754B101E; Mon, 11 Jan 2021 18:57:57 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6CD43F66E; Mon, 11 Jan 2021 18:57:52 -0800 (PST) From: Ruifeng Wang To: "Wei Hu (Xavier)" , "Min Hu (Connor)" , Yisen Zhuang , Lijun Ou , Chengwen Feng , Chengchang Tang , Huisong Li Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, pbhagavatula@marvell.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Tue, 12 Jan 2021 02:57:05 +0000 Message-Id: <20210112025709.1121523-3-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 2/5] net/hns3: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with SVE extension enabled stopped with error: error: ACLE function ‘svwhilelt_b64_s32’ requires ISA extension ‘sve’ 18 | #define PG64_256BIT svwhilelt_b64(0, 4) This is caused by unintentional cflags reset. Fixed the issue by not touching cflags, and using flags defined by compiler. Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli --- v3: Removed extra flag, use compiler flag instead. drivers/net/hns3/hns3_rxtx.c | 4 ++-- drivers/net/hns3/meson.build | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 88d3baba4..5ac36b314 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -10,7 +10,7 @@ #include #include #include -#if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT) +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) #include #endif @@ -2467,7 +2467,7 @@ hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, static bool hns3_check_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT) +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) return true; #endif diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 45cee34d9..5674d986b 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -32,7 +32,6 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' - cflags = ['-DCC_SVE_SUPPORT'] sources += files('hns3_rxtx_vec_sve.c') endif endif From patchwork Tue Jan 12 02:57:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86361 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6706A04B5; Tue, 12 Jan 2021 03:58:13 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4999140CD7; Tue, 12 Jan 2021 03:58:13 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 55085140CD7; Tue, 12 Jan 2021 03:58:12 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1291101E; Mon, 11 Jan 2021 18:58:11 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C8E93F66E; Mon, 11 Jan 2021 18:58:07 -0800 (PST) From: Ruifeng Wang To: Harman Kalra , Santosh Shukla , Jerin Jacob Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, pbhagavatula@marvell.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Tue, 12 Jan 2021 02:57:06 +0000 Message-Id: <20210112025709.1121523-4-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 3/5] net/octeontx: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1' {standard input}:95: Error: selected processor does not support `ptrue p1.d,all' {standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5' {standard input}:137: Error: selected processor does not support `decb x1' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Added SVE to the cpu model specified by inline assembly for SVE support. Not replacing the inline assembly with C atomics because the driver relies on specific LSE instruction to interface to co-processor [1]. Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations") Cc: jerinj@marvell.com Cc: stable@dpdk.org [1] https://mails.dpdk.org/archives/dev/2021-January/196092.html Signed-off-by: Ruifeng Wang Reviewed-by: Jerin Jacob --- v3: Keep inline assembly and add sve extension to fix issue. (Pavan) drivers/net/octeontx/base/octeontx_io.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h index 04b9ce191..d0b9cfbc6 100644 --- a/drivers/net/octeontx/base/octeontx_io.h +++ b/drivers/net/octeontx/base/octeontx_io.h @@ -52,6 +52,11 @@ do { \ #endif #if defined(RTE_ARCH_ARM64) +#if defined(__ARM_FEATURE_SVE) +#define __LSE_PREAMBLE " .cpu generic+lse+sve\n" +#else +#define __LSE_PREAMBLE " .cpu generic+lse\n" +#endif /** * Perform an atomic fetch-and-add operation. */ @@ -61,7 +66,7 @@ octeontx_reg_ldadd_u64(void *addr, int64_t off) uint64_t old_val; __asm__ volatile( - " .cpu generic+lse\n" + __LSE_PREAMBLE " ldadd %1, %0, [%2]\n" : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); @@ -98,12 +103,13 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], /* LDEOR initiates atomic transfer to I/O device */ __asm__ volatile( - " .cpu generic+lse\n" + __LSE_PREAMBLE " ldeor xzr, %0, [%1]\n" : "=r" (result) : "r" (ioreg_va) : "memory"); } while (!result); } +#undef __LSE_PREAMBLE #else static inline uint64_t From patchwork Tue Jan 12 02:57:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86362 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43805A04B5; Tue, 12 Jan 2021 03:58:20 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 302E6140D26; Tue, 12 Jan 2021 03:58:19 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id A7258140D26; Tue, 12 Jan 2021 03:58:17 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37F1B101E; Mon, 11 Jan 2021 18:58:17 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 04B123F66E; Mon, 11 Jan 2021 18:58:13 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Nithin Dabilpuram , Pavan Nikhilesh Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Tue, 12 Jan 2021 02:57:07 +0000 Message-Id: <20210112025709.1121523-5-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 4/5] common/octeontx2: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:4002: Error: selected processor does not support `mov z3.b,#0' {standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7' {standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]' {standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Added SVE to the cpu model specified by inline assembly for SVE support. Not replacing the inline assembly with C atomics because the driver relies on specific LSE instruction to interface to co-processor [1]. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Cc: jerinj@marvell.com Cc: stable@dpdk.org [1] https://mails.dpdk.org/archives/dev/2021-January/196092.html Signed-off-by: Ruifeng Wang Reviewed-by: Jerin Jacob --- v3: Keep inline assembly and add sve extension to fix issue. (Pavan) drivers/common/octeontx2/otx2_io_arm64.h | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h index b5c85d9a6..34268e3af 100644 --- a/drivers/common/octeontx2/otx2_io_arm64.h +++ b/drivers/common/octeontx2/otx2_io_arm64.h @@ -21,6 +21,12 @@ #define otx2_prefetch_store_keep(ptr) ({\ asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (ptr)); }) +#if defined(__ARM_FEATURE_SVE) +#define __LSE_PREAMBLE " .cpu generic+lse+sve\n" +#else +#define __LSE_PREAMBLE " .cpu generic+lse\n" +#endif + static __rte_always_inline uint64_t otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) { @@ -28,7 +34,7 @@ otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) /* Atomic add with no ordering */ asm volatile ( - ".cpu generic+lse\n" + __LSE_PREAMBLE "ldadd %x[i], %x[r], [%[b]]" : [r] "=r" (result), "+m" (*ptr) : [i] "r" (incr), [b] "r" (ptr) @@ -43,7 +49,7 @@ otx2_atomic64_add_sync(int64_t incr, int64_t *ptr) /* Atomic add with ordering */ asm volatile ( - ".cpu generic+lse\n" + __LSE_PREAMBLE "ldadda %x[i], %x[r], [%[b]]" : [r] "=r" (result), "+m" (*ptr) : [i] "r" (incr), [b] "r" (ptr) @@ -57,7 +63,7 @@ otx2_lmt_submit(rte_iova_t io_address) uint64_t result; asm volatile ( - ".cpu generic+lse\n" + __LSE_PREAMBLE "ldeor xzr,%x[rf],[%[rs]]" : [rf] "=r"(result): [rs] "r"(io_address)); return result; @@ -69,7 +75,7 @@ otx2_lmt_submit_release(rte_iova_t io_address) uint64_t result; asm volatile ( - ".cpu generic+lse\n" + __LSE_PREAMBLE "ldeorl xzr,%x[rf],[%[rs]]" : [rf] "=r"(result) : [rs] "r"(io_address)); return result; @@ -104,4 +110,5 @@ otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw) dst128[i] = src128[i]; } +#undef __LSE_PREAMBLE #endif /* _OTX2_IO_ARM64_H_ */ From patchwork Tue Jan 12 02:57:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86363 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D89EA04B5; Tue, 12 Jan 2021 03:58:30 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73D43140CFB; Tue, 12 Jan 2021 03:58:30 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id A84CC140CAF for ; Tue, 12 Jan 2021 03:58:28 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 355F3101E; Mon, 11 Jan 2021 18:58:28 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 029143F66E; Mon, 11 Jan 2021 18:58:24 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Ruifeng Wang , Jan Viktorin , Bruce Richardson Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, pbhagavatula@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com Date: Tue, 12 Jan 2021 02:57:08 +0000 Message-Id: <20210112025709.1121523-6-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 5/5] config: add Arm Neoverse N2 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add Arm Neoverse N2 cpu support. Signed-off-by: Ruifeng Wang Acked-by: Jerin Jacob Reviewed-by: Honnappa Nagarahalli --- v3: Changed arch extension from sve to sve2 as N2 supports sve2. (Honnappa) config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++ config/arm/meson.build | 11 ++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_n2_linux_gcc diff --git a/config/arm/arm64_n2_linux_gcc b/config/arm/arm64_n2_linux_gcc new file mode 100644 index 000000000..78f6f3e2b --- /dev/null +++ b/config/arm/arm64_n2_linux_gcc @@ -0,0 +1,17 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pkgconfig = 'aarch64-linux-gnu-pkg-config' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x41' +implementor_pn = '0xd49' diff --git a/config/arm/meson.build b/config/arm/meson.build index 42b4e43c7..5fd1c40a0 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -89,6 +89,14 @@ flags_n1generic_extra = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], ['RTE_LIBRTE_VHOST_NUMA', false]] +flags_n2generic_extra = [ + ['RTE_MACHINE', '"neoverse-n2"'], + ['RTE_MAX_LCORE', 64], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], + ['RTE_LIBRTE_VHOST_NUMA', false]] machine_args_generic = [ ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7 +108,8 @@ machine_args_generic = [ ['0xd09', ['-mcpu=cortex-a73']], ['0xd0a', ['-mcpu=cortex-a75']], ['0xd0b', ['-mcpu=cortex-a76']], - ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]] + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra], + ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_n2generic_extra]] machine_args_cavium = [ ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],