From patchwork Mon Jan 11 18:21:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86334 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9693AA09FF; Mon, 11 Jan 2021 19:22:10 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E1177140FD5; Mon, 11 Jan 2021 19:22:09 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id DEEF5140FD3 for ; Mon, 11 Jan 2021 19:22:07 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:02 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fS011077; Mon, 11 Jan 2021 20:22:02 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:48 +0200 Message-Id: <20210111182153.9972-2-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 1/6] ethdev: update GTP headers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko This patch introduces the GTP header individual flag bit fields and the header optional word with N-PDU number, Sequence Number and Next Extension Header type. Signed-off-by: Viacheslav Ovsiienko Acked-by: Ori Kam Reviewed-by: Ferruh Yigit --- lib/librte_net/rte_gtp.h | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/lib/librte_net/rte_gtp.h b/lib/librte_net/rte_gtp.h index 104384cc53..6a6f9b238d 100644 --- a/lib/librte_net/rte_gtp.h +++ b/lib/librte_net/rte_gtp.h @@ -27,13 +27,40 @@ extern "C" { * 16-bit payload length after mandatory header, 32-bit TEID. * No optional fields and next extension header. */ +__extension__ struct rte_gtp_hdr { - uint8_t gtp_hdr_info; /**< GTP header info */ + union { + uint8_t gtp_hdr_info; /**< GTP header info */ + struct { +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint8_t pn:1; /**< N-PDU Number present bit */ + uint8_t s:1; /**< Sequence Number Present bit */ + uint8_t e:1; /**< Extension Present bit */ + uint8_t res1:1; /**< Reserved */ + uint8_t pt:1; /**< Protocol Type bit */ + uint8_t ver:3; /**< Version Number */ +#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint8_t ver:3; /**< Version Number */ + uint8_t pt:1; /**< Protocol Type bit */ + uint8_t res1:1; /**< Reserved */ + uint8_t e:1; /**< Extension Present bit */ + uint8_t s:1; /**< Sequence Number Present bit */ + uint8_t pn:1; /**< N-PDU Number present bit */ +#endif + }; + }; uint8_t msg_type; /**< GTP message type */ - uint16_t plen; /**< Total payload length */ - uint32_t teid; /**< Tunnel endpoint ID */ + rte_be16_t plen; /**< Total payload length */ + rte_be32_t teid; /**< Tunnel endpoint ID */ } __rte_packed; +/* Optional word of GTP header, present if any of E, S, PN is set. */ +struct rte_gtp_hdr_ext_word { + rte_be16_t sqn; /**< Sequence Number. */ + uint8_t npdu; /**< N-PDU number. */ + uint8_t next_ext; /**< Next Extension Header Type. */ +} __rte_packed; + /** GTP header length */ #define RTE_ETHER_GTP_HLEN \ (sizeof(struct rte_udp_hdr) + sizeof(struct rte_gtp_hdr)) From patchwork Mon Jan 11 18:21:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86335 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41E6DA09FF; Mon, 11 Jan 2021 19:22:17 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19218140FDB; Mon, 11 Jan 2021 19:22:11 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id E7C53140FD4 for ; Mon, 11 Jan 2021 19:22:07 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:04 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fT011077; Mon, 11 Jan 2021 20:22:04 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:49 +0200 Message-Id: <20210111182153.9972-3-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/6] app/testpmd: add GTP PSC option support in raw sets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko This patch add support for generating GTP PDU container session option for the raw encap and raw decap sets. The generated options is single 32-bit word with minimal length specified as 4, no extra fields in the option are supported. The option item must be preceded with the GTP item itself, and GTP item flags must be set accordingly: - E flag must be set, we are going to provide extension - S flag must be reset, because GTP item does not provide the value for SQN field, we can't fill this one - PN flag must be reset, no N-PDU value provided by GTP item either The raw set example: set raw_encap 2 eth / ipv4 / udp / gtp v_pt_rsv_flags is 0x34 / gtp_psc / end_set Please, note - value 0x34 provides the required flag combination. Signed-off-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- app/test-pmd/cmdline_flow.c | 66 +++++++++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 585cab98b4..37b10e61bf 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -7581,6 +7581,7 @@ cmd_set_raw_parsed(const struct buffer *in) uint16_t upper_layer = 0; uint16_t proto = 0; uint16_t idx = in->port; /* We borrow port field as index */ + int gtp_psc = -1; /* GTP PSC option index. */ if (in->command == SET_SAMPLE_ACTIONS) return cmd_set_raw_parsed_sample(in); @@ -7598,6 +7599,8 @@ cmd_set_raw_parsed(const struct buffer *in) /* process hdr from upper layer to low layer (L3/L4 -> L2). */ data_tail = data + ACTION_RAW_ENCAP_MAX_DATA; for (i = n - 1 ; i >= 0; --i) { + const struct rte_flow_item_gtp *gtp; + item = in->args.vc.pattern + i; if (item->spec == NULL) item->spec = flow_item_default_mask(item); @@ -7663,16 +7666,68 @@ cmd_set_raw_parsed(const struct buffer *in) proto = 0x33; break; case RTE_FLOW_ITEM_TYPE_GTP: + if (gtp_psc < 0) { + size = sizeof(struct rte_gtp_hdr); + break; + } + if (gtp_psc != i + 1) { + printf("Error - GTP PSC does not follow GTP\n"); + goto error; + } + gtp = item->spec; + if ((gtp->v_pt_rsv_flags & 0x07) != 0x04) { + /* Only E flag should be set. */ + printf("Error - GTP unsupported flags\n"); + goto error; + } else { + struct rte_gtp_hdr_ext_word ext_word = { + .next_ext = 0x85 + }; + + /* We have to add GTP header extra word. */ + *total_size += sizeof(ext_word); + rte_memcpy(data_tail - (*total_size), + &ext_word, sizeof(ext_word)); + } size = sizeof(struct rte_gtp_hdr); break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + if (gtp_psc >= 0) { + printf("Error - Multiple GTP PSC items\n"); + goto error; + } else { + const struct rte_flow_item_gtp_psc + *opt = item->spec; + struct { + uint8_t len; + uint8_t pdu_type; + uint8_t qfi; + uint8_t next; + } psc; + + if (opt->pdu_type & 0x0F) { + /* Support the minimal option only. */ + printf("Error - GTP PSC option with " + "extra fields not supported\n"); + goto error; + } + psc.len = sizeof(psc); + psc.pdu_type = opt->pdu_type; + psc.qfi = opt->qfi; + psc.next = 0; + *total_size += sizeof(psc); + rte_memcpy(data_tail - (*total_size), + &psc, sizeof(psc)); + gtp_psc = i; + size = 0; + } + break; case RTE_FLOW_ITEM_TYPE_PFCP: size = sizeof(struct rte_flow_item_pfcp); break; default: printf("Error - Not supported item\n"); - *total_size = 0; - memset(data, 0x00, ACTION_RAW_ENCAP_MAX_DATA); - return; + goto error; } *total_size += size; rte_memcpy(data_tail - (*total_size), item->spec, size); @@ -7685,6 +7740,11 @@ cmd_set_raw_parsed(const struct buffer *in) printf("total data size is %zu\n", (*total_size)); RTE_ASSERT((*total_size) <= ACTION_RAW_ENCAP_MAX_DATA); memmove(data, (data_tail - (*total_size)), *total_size); + return; + +error: + *total_size = 0; + memset(data, 0x00, ACTION_RAW_ENCAP_MAX_DATA); } /** Populate help strings for current token (cmdline API). */ From patchwork Mon Jan 11 18:21:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86336 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF893A09FF; Mon, 11 Jan 2021 19:22:24 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 469B6140FE0; Mon, 11 Jan 2021 19:22:12 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id EADD4140FD5 for ; Mon, 11 Jan 2021 19:22:07 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:07 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fU011077; Mon, 11 Jan 2021 20:22:06 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:50 +0200 Message-Id: <20210111182153.9972-4-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 3/6] common/mlx5: add matcher fields for GTP extensions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is a preparation step to support GTP extension header. In this patch we add the matcher fields that will be used to match on the GTP extension header. Signed-off-by: Shiri Kuzin Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_prm.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 8c9b53ce10..8a82c4f5ec 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -793,7 +793,12 @@ struct mlx5_ifc_fte_match_set_misc3_bits { u8 gtpu_teid[0x20]; u8 gtpu_msg_type[0x08]; u8 gtpu_msg_flags[0x08]; - u8 reserved_at_170[0x90]; + u8 reserved_at_170[0x10]; + u8 gtpu_dw_2[0x20]; + u8 gtpu_first_ext_dw_0[0x20]; + u8 gtpu_dw_0[0x20]; + u8 reserved_at_240[0x20]; + }; struct mlx5_ifc_fte_match_set_misc4_bits { From patchwork Mon Jan 11 18:21:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86337 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C6B6A09FF; Mon, 11 Jan 2021 19:22:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 79324140FE8; Mon, 11 Jan 2021 19:22:14 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id EE2C8140FE5 for ; Mon, 11 Jan 2021 19:22:12 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:08 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fV011077; Mon, 11 Jan 2021 20:22:08 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:51 +0200 Message-Id: <20210111182153.9972-5-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 4/6] net/mlx5: add GTP PSC flow validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In this patch we add validation routine for GTP PSC extension header. The GTP PSC extension header must follow the GTP item. Signed-off-by: Shiri Kuzin Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 8 ++++ drivers/net/mlx5/mlx5_flow_dv.c | 76 +++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index ee85c9d8a5..e54412e07b 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -138,6 +138,9 @@ enum mlx5_feature_name { #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30) #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31) +/* Pattern tunnel Layer bits (continued). */ +#define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -348,6 +351,11 @@ enum mlx5_feature_name { #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \ sizeof(struct rte_ipv4_hdr)) +/* GTP extension header flag. */ +#define MLX5_GTP_EXT_HEADER_FLAG 4 + +/* GTP extension header max PDU type value. */ +#define MLX5_GTP_EXT_MAX_PDU_TYPE 15 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ #define MLX5_IPV4_FRAG_OFFSET_MASK \ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index e4736ee9b5..d11f4eb4b8 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1759,6 +1759,72 @@ flow_dv_validate_item_gtp(struct rte_eth_dev *dev, MLX5_ITEM_RANGE_NOT_ACCEPTED, error); } +/** + * Validate GTP PSC item. + * + * @param[in] item + * Item specification. + * @param[in] last_item + * Previous validated item in the pattern items. + * @param[in] gtp_item + * Previous GTP item specification. + * @param[in] attr + * Pointer to flow attributes. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item, + uint64_t last_item, + const struct rte_flow_item *gtp_item, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + const struct rte_flow_item_gtp *gtp_spec; + const struct rte_flow_item_gtp *gtp_mask; + const struct rte_flow_item_gtp_psc *spec; + const struct rte_flow_item_gtp_psc *mask; + const struct rte_flow_item_gtp_psc nic_mask = { + .pdu_type = 0xFF, + .qfi = 0xFF, + }; + + if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP)) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, + "GTP PSC item must be preceded with GTP item"); + gtp_spec = gtp_item->spec; + gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask; + /* GTP spec and E flag is requested to match zero. */ + if (gtp_spec && + (gtp_mask->v_pt_rsv_flags & + ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG)) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, + "GTP E flag must be 1 to match GTP PSC"); + /* Check the flow is not created in group zero. */ + if (!attr->transfer && !attr->group) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "GTP PSC is not supported for group 0"); + /* GTP spec is here and E flag is requested to match zero. */ + if (!item->spec) + return 0; + spec = item->spec; + mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask; + if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE) + return rte_flow_error_set + (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, + "PDU type should be smaller than 16"); + return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, + (const uint8_t *)&nic_mask, + sizeof(struct rte_flow_item_gtp_psc), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); +} + /** * Validate IPV4 item. * Use existing validation function mlx5_flow_validate_item_ipv4(), and @@ -5238,6 +5304,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, int actions_n = 0; uint8_t item_ipv6_proto = 0; const struct rte_flow_item *gre_item = NULL; + const struct rte_flow_item *gtp_item = NULL; const struct rte_flow_action_raw_decap *decap; const struct rte_flow_action_raw_encap *encap; const struct rte_flow_action_rss *rss; @@ -5575,8 +5642,17 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, error); if (ret < 0) return ret; + gtp_item = items; last_item = MLX5_FLOW_LAYER_GTP; break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + ret = flow_dv_validate_item_gtp_psc(items, last_item, + gtp_item, attr, + error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_LAYER_GTP_PSC; + break; case RTE_FLOW_ITEM_TYPE_ECPRI: /* Capacity will be checked in the translate stage. */ ret = mlx5_flow_validate_item_ecpri(items, item_flags, From patchwork Mon Jan 11 18:21:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86338 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6563A09FF; Mon, 11 Jan 2021 19:22:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B34D7140FED; Mon, 11 Jan 2021 19:22:15 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id EF329140FE6 for ; Mon, 11 Jan 2021 19:22:12 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:10 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fW011077; Mon, 11 Jan 2021 20:22:10 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:52 +0200 Message-Id: <20210111182153.9972-6-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 5/6] net/mlx5: add GTP PSC item translation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the translation function which sets the qfi, PDU type. The next extension header which indicates the following extension header type is set to 0x85 - a PDU session container. Signed-off-by: Shiri Kuzin Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 3 ++ drivers/net/mlx5/mlx5_flow_dv.c | 86 +++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e54412e07b..c25b100945 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -357,6 +357,9 @@ enum mlx5_feature_name { /* GTP extension header max PDU type value. */ #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 +/* GTP extension header PDU type shift. */ +#define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) + /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ #define MLX5_IPV4_FRAG_OFFSET_MASK \ (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index d11f4eb4b8..860ef9aa01 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7930,6 +7930,82 @@ flow_dv_translate_item_gtp(void *matcher, void *key, rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid)); } +/** + * Add GTP PSC item to matcher. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + */ +static int +flow_dv_translate_item_gtp_psc(void *matcher, void *key, + const struct rte_flow_item *item) +{ + const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask; + const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec; + void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, + misc_parameters_3); + void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); + union { + uint32_t w32; + struct { + uint16_t seq_num; + uint8_t npdu_num; + uint8_t next_ext_header_type; + }; + } dw_2; + uint8_t gtp_flags; + + /* Always set E-flag match on one, regardless of GTP item settings. */ + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags); + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags); + /*Set next extension header type. */ + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0xff; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0x85; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + if (gtp_psc_v) { + union { + uint32_t w32; + struct { + uint8_t len; + uint8_t type_flags; + uint8_t qfi; + uint8_t reserved; + }; + } dw_0; + + /*Set extension header PDU type and Qos. */ + if (!gtp_psc_m) + gtp_psc_m = &rte_flow_item_gtp_psc_mask; + dw_0.w32 = 0; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type); + dw_0.qfi = gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + dw_0.w32 = 0; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type & + gtp_psc_m->pdu_type); + dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + } + return 0; +} + /** * Add eCPRI item to matcher and to the value. * @@ -10615,6 +10691,16 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GTP; break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + ret = flow_dv_translate_item_gtp_psc(match_mask, + match_value, + items); + if (ret) + return rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "cannot create GTP PSC item"); + last_item = MLX5_FLOW_LAYER_GTP_PSC; + break; case RTE_FLOW_ITEM_TYPE_ECPRI: if (!mlx5_flex_parser_ecpri_exist(dev)) { /* Create it only the first time to be used. */ From patchwork Mon Jan 11 18:21:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86339 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4FE02A09FF; Mon, 11 Jan 2021 19:22:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48FA0140FF6; Mon, 11 Jan 2021 19:22:20 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 01901140FE7 for ; Mon, 11 Jan 2021 19:22:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:12 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fX011077; Mon, 11 Jan 2021 20:22:12 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:53 +0200 Message-Id: <20210111182153.9972-7-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 6/6] doc: update GTP extension header support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" added GTP extension header support to mlx5 PMD. The limitations and support were updated in documentation. Signed-off-by: Shiri Kuzin Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 10 ++++++++++ doc/guides/rel_notes/release_21_02.rst | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 3bda0f8417..b025eb7bc9 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -98,6 +98,7 @@ Features - Hardware LRO. - Hairpin. - Multiple-thread flow insertion. +- Matching on GTP extension header with raw encap/decap action. Limitations ----------- @@ -186,6 +187,10 @@ Limitations - msg_type - teid +- Match on GTP extension header only for GTP PDU session container (next + extension header type = 0x85). +- Match on GTP extension header is not supported in group 0. + - No Tx metadata go to the E-Switch steering domain for the Flow group 0. The flows within group 0 and set metadata action are rejected by hardware. @@ -1501,6 +1506,11 @@ Supported hardware offloads | | | rdma-core 32 | | rdma-core 32 | | | | ConnectX-6 Dx| | ConnectX-6 Dx | +-----------------------+-----------------+-----------------+ + | Encapsulation | | DPDK 21.02 | | DPDK 21.02 | + | GTP PSC | | OFED 5.2 | | OFED 5.2 | + | | | rdma-core 35 | | rdma-core 35 | + | | | ConnectX-6 Dx| | ConnectX-6 Dx | + +-----------------------+-----------------+-----------------+ Notes for metadata ------------------ diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst index 638f98168b..61961aab2b 100644 --- a/doc/guides/rel_notes/release_21_02.rst +++ b/doc/guides/rel_notes/release_21_02.rst @@ -55,6 +55,11 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Mellanox mlx5 driver.** + + Updated the Mellanox mlx5 driver with new features and improvements, including: + + * Added GTP PDU session container matching and raw encap/decap. Removed Items -------------