From patchwork Fri Dec 11 15:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Malov X-Patchwork-Id: 85014 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06BA7A09E0; Fri, 11 Dec 2020 16:34:57 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 789E6AC9C; Fri, 11 Dec 2020 16:34:55 +0100 (CET) Received: from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113]) by dpdk.org (Postfix) with ESMTP id 68046AC9A; Fri, 11 Dec 2020 16:34:53 +0100 (CET) Received: from localhost.localdomain (unknown [5.144.123.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by shelob.oktetlabs.ru (Postfix) with ESMTPSA id C9DCC7F521; Fri, 11 Dec 2020 18:34:51 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru C9DCC7F521 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=oktetlabs.ru; s=default; t=1607700891; bh=dYEn72l2Ke+cyITf7w4M7UF4+b4U9ty8GJKqY8zzX8Y=; h=From:To:Cc:Subject:Date; b=tI54A3JyKy9BkPINt261IDTxtfBrlXJDm4bZHWijfVwLI5HxrrLg23zA5DqffXi3V zBVnaxXDm+vy9aPF7XoSbm/mkF5e3SqglxrXJdQqTqQzKJjUOZD+z7h7LUHrixxoly rhveY1pz3YkICm+z2muTcRBfQlYvYklPJSQGQHq8= From: Ivan Malov To: dev@dpdk.org Cc: stable@dpdk.org, Andrew Rybchenko Date: Fri, 11 Dec 2020 18:34:20 +0300 Message-Id: <20201211153421.28382-1-ivan.malov@oktetlabs.ru> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/2] common/sfc_efx/base: update MCDI headers for MAE privilege X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" VFs and unprivileged PFs should not be able to control MAE. Add MAE privilege to MCDI headers in order to reflect that. Fixes: 84d3fb7d7e1e ("common/sfc_efx/base: add MAE definitions to MCDI") Cc: stable@dpdk.org Signed-off-by: Ivan Malov Reviewed-by: Andrew Rybchenko --- drivers/common/sfc_efx/base/efx_regs_mcdi.h | 54 +++++++++++++-------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/drivers/common/sfc_efx/base/efx_regs_mcdi.h index 0388acf72..689a491d0 100644 --- a/drivers/common/sfc_efx/base/efx_regs_mcdi.h +++ b/drivers/common/sfc_efx/base/efx_regs_mcdi.h @@ -20349,6 +20349,8 @@ * SF-117064-DG for background). */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000 +/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000 /* enum: Set this bit to indicate that a new privilege mask is to be set, * otherwise the command will only read the existing mask. */ @@ -26823,7 +26825,7 @@ #define MC_CMD_MAE_GET_AR_CAPS 0x141 #undef MC_CMD_0x141_PRIVILEGE_CTG -#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_GET_AR_CAPS_IN msgrequest */ #define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0 @@ -26855,7 +26857,7 @@ #define MC_CMD_MAE_GET_OR_CAPS 0x142 #undef MC_CMD_0x142_PRIVILEGE_CTG -#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_GET_OR_CAPS_IN msgrequest */ #define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0 @@ -26885,7 +26887,7 @@ #define MC_CMD_MAE_COUNTER_ALLOC 0x143 #undef MC_CMD_0x143_PRIVILEGE_CTG -#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_COUNTER_ALLOC_IN msgrequest */ #define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4 @@ -26928,7 +26930,7 @@ #define MC_CMD_MAE_COUNTER_FREE 0x144 #undef MC_CMD_0x144_PRIVILEGE_CTG -#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_COUNTER_FREE_IN msgrequest */ #define MC_CMD_MAE_COUNTER_FREE_IN_LENMIN 8 @@ -26993,6 +26995,9 @@ * delivering packets to the current queue first. */ #define MC_CMD_MAE_COUNTERS_STREAM_START 0x151 +#undef MC_CMD_0x151_PRIVILEGE_CTG + +#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_COUNTERS_STREAM_START_IN msgrequest */ #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN 8 @@ -27026,6 +27031,9 @@ * Stop streaming counter values to the specified RxQ. */ #define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152 +#undef MC_CMD_0x152_PRIVILEGE_CTG + +#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_COUNTERS_STREAM_STOP_IN msgrequest */ #define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN 2 @@ -27052,6 +27060,9 @@ * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell. */ #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153 +#undef MC_CMD_0x153_PRIVILEGE_CTG + +#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN msgrequest */ #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4 @@ -27070,7 +27081,7 @@ #define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148 #undef MC_CMD_0x148_PRIVILEGE_CTG -#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN msgrequest */ #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4 @@ -27103,7 +27114,7 @@ #define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149 #undef MC_CMD_0x149_PRIVILEGE_CTG -#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN msgrequest */ #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMIN 8 @@ -27132,7 +27143,7 @@ #define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a #undef MC_CMD_0x14a_PRIVILEGE_CTG -#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ENCAP_HEADER_FREE_IN msgrequest */ #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4 @@ -27170,7 +27181,7 @@ #define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e #undef MC_CMD_0x15e_PRIVILEGE_CTG -#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_MAC_ADDR_ALLOC_IN msgrequest */ #define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_LEN 6 @@ -27195,7 +27206,7 @@ #define MC_CMD_MAE_MAC_ADDR_FREE 0x15f #undef MC_CMD_0x15f_PRIVILEGE_CTG -#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_MAC_ADDR_FREE_IN msgrequest */ #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4 @@ -27232,7 +27243,7 @@ #define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d #undef MC_CMD_0x14d_PRIVILEGE_CTG -#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_SET_ALLOC_IN msgrequest */ #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN 44 @@ -27317,7 +27328,7 @@ #define MC_CMD_MAE_ACTION_SET_FREE 0x14e #undef MC_CMD_0x14e_PRIVILEGE_CTG -#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_SET_FREE_IN msgrequest */ #define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4 @@ -27355,7 +27366,7 @@ #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f #undef MC_CMD_0x14f_PRIVILEGE_CTG -#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN msgrequest */ #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMIN 8 @@ -27398,7 +27409,7 @@ #define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150 #undef MC_CMD_0x150_PRIVILEGE_CTG -#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_SET_LIST_FREE_IN msgrequest */ #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4 @@ -27435,7 +27446,7 @@ #define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a #undef MC_CMD_0x15a_PRIVILEGE_CTG -#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_ADMIN +#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_OUTER_RULE_INSERT_IN msgrequest */ #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMIN 16 @@ -27495,7 +27506,7 @@ #define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b #undef MC_CMD_0x15b_PRIVILEGE_CTG -#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_ADMIN +#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_OUTER_RULE_REMOVE_IN msgrequest */ #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4 @@ -27577,7 +27588,7 @@ #define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c #undef MC_CMD_0x15c_PRIVILEGE_CTG -#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_RULE_INSERT_IN msgrequest */ #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMIN 28 @@ -27618,7 +27629,7 @@ #define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d #undef MC_CMD_0x15d_PRIVILEGE_CTG -#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_RULE_UPDATE_IN msgrequest */ #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_LEN 24 @@ -27639,7 +27650,7 @@ #define MC_CMD_MAE_ACTION_RULE_DELETE 0x155 #undef MC_CMD_0x155_PRIVILEGE_CTG -#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_ACTION_RULE_DELETE_IN msgrequest */ #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4 @@ -27696,7 +27707,7 @@ #define MC_CMD_MAE_MPORT_ALLOC 0x163 #undef MC_CMD_0x163_PRIVILEGE_CTG -#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_MPORT_ALLOC_IN msgrequest */ #define MC_CMD_MAE_MPORT_ALLOC_IN_LEN 20 @@ -27803,7 +27814,7 @@ #define MC_CMD_MAE_MPORT_FREE 0x164 #undef MC_CMD_0x164_PRIVILEGE_CTG -#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_GENERAL +#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE /* MC_CMD_MAE_MPORT_FREE_IN msgrequest */ #define MC_CMD_MAE_MPORT_FREE_IN_LEN 4 @@ -27907,6 +27918,9 @@ /* MC_CMD_MAE_MPORT_ENUMERATE */ #define MC_CMD_MAE_MPORT_ENUMERATE 0x17c +#undef MC_CMD_0x17c_PRIVILEGE_CTG + +#define MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL /* MC_CMD_MAE_MPORT_ENUMERATE_IN msgrequest */ #define MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0 From patchwork Fri Dec 11 15:34:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Malov X-Patchwork-Id: 85015 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA3A3A09E0; Fri, 11 Dec 2020 16:35:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0E73EC96E; Fri, 11 Dec 2020 16:34:57 +0100 (CET) Received: from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113]) by dpdk.org (Postfix) with ESMTP id 6B3D5AC9C; Fri, 11 Dec 2020 16:34:53 +0100 (CET) Received: from localhost.localdomain (unknown [5.144.123.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by shelob.oktetlabs.ru (Postfix) with ESMTPSA id 15BD07F541; Fri, 11 Dec 2020 18:34:52 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru 15BD07F541 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=oktetlabs.ru; s=default; t=1607700892; bh=655OchNYp6tq0oamsoELebDGDGxQPYvwF0CwTSxkdRs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=t5JqQsq3mP+y8F4TyXn76uvm79qfb7SqA4P+jB7IOZURgr65vmSa6YM4F303KrQBw wIycUswEWWZkGJ1XcbB9fuWI2gB+3LwpxzhPB1Vu/CxgdLvWgATuHNsQ1n6D1VJbBO fQOTvpnU5HuE9gEWJE5NzA4vyWcfEeI/cRpe/T+s= From: Ivan Malov To: dev@dpdk.org Cc: stable@dpdk.org, Andy Moreton , Andrew Rybchenko Date: Fri, 11 Dec 2020 18:34:21 +0300 Message-Id: <20201211153421.28382-2-ivan.malov@oktetlabs.ru> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201211153421.28382-1-ivan.malov@oktetlabs.ru> References: <20201211153421.28382-1-ivan.malov@oktetlabs.ru> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/2] common/sfc_efx/base: check for MAE privilege X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" VFs can't control MAE, so it's important to override the general MAE capability bit by taking MAE privilege into account. Reorder the code slightly to have the privileges queried before datapath capabilities are discovered and add required MAE privilege check. Fixes: eb4e80085fae ("common/sfc_efx/base: indicate support for MAE") Cc: stable@dpdk.org Signed-off-by: Ivan Malov Reviewed-by: Andy Moreton Reviewed-by: Andrew Rybchenko --- drivers/common/sfc_efx/base/ef10_nic.c | 48 ++++++++++++++++---------- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c index 68414d9fa..9dccde957 100644 --- a/drivers/common/sfc_efx/base/ef10_nic.c +++ b/drivers/common/sfc_efx/base/ef10_nic.c @@ -1423,11 +1423,19 @@ ef10_get_datapath_caps( #if EFSYS_OPT_MAE /* - * Indicate support for MAE. - * MAE is supported by Riverhead boards starting with R2, - * and it is required that FW is built with MAE support, too. + * Check support for EF100 Match Action Engine (MAE). + * MAE hardware is present on Riverhead boards (from R2), + * and on Keystone, and requires support in firmware. + * + * MAE control operations require MAE control privilege, + * which is not available for VFs. + * + * Privileges can change dynamically at runtime: we assume + * MAE support requires the privilege is granted initially, + * and ignore later dynamic changes. */ - if (CAP_FLAGS3(req, MAE_SUPPORTED)) + if (CAP_FLAGS3(req, MAE_SUPPORTED) && + EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE)) encp->enc_mae_supported = B_TRUE; else encp->enc_mae_supported = B_FALSE; @@ -1896,6 +1904,18 @@ efx_mcdi_nic_board_cfg( EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); + /* + * Get the current privilege mask. Note that this may be modified + * dynamically, so for most cases the value is informational only. + * If the privilege being discovered can't be granted dynamically, + * it's fine to rely on the value. In all other cases, DO NOT use + * the privilege mask to check for sufficient privileges, as that + * can result in time-of-check/time-of-use bugs. + */ + if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) + goto fail6; + encp->enc_privilege_mask = mask; + /* Board configuration (legacy) */ rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); if (rc != 0) { @@ -1903,14 +1923,14 @@ efx_mcdi_nic_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail6; + goto fail7; } encp->enc_board_type = board_type; /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail7; + goto fail8; /* * Firmware with support for *_FEC capability bits does not @@ -1929,18 +1949,18 @@ efx_mcdi_nic_board_cfg( /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail8; + goto fail9; epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask; epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask; /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail9; + goto fail10; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail10; + goto fail11; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -1949,16 +1969,6 @@ efx_mcdi_nic_board_cfg( encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - /* - * Get the current privilege mask. Note that this may be modified - * dynamically, so this value is informational only. DO NOT use - * the privilege mask to check for sufficient privileges, as that - * can result in time-of-check/time-of-use bugs. - */ - if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail11; - encp->enc_privilege_mask = mask; - return (0); fail11: