From patchwork Thu Oct 15 15:22:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80944 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EDEAA04DB; Thu, 15 Oct 2020 17:23:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 10A4D1EA21; Thu, 15 Oct 2020 17:23:26 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 609FE1EA16 for ; Thu, 15 Oct 2020 17:23:24 +0200 (CEST) IronPort-SDR: YhBu1r3wtdu/0Kgnn/VuXD26Z5JPMFKTMdP1KBWH4jFg+WQUMViy2bfybxa7lIFQ+Wic2TxIV1 y9kr3OeHjHcQ== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909106" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909106" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:19 -0700 IronPort-SDR: MfcEu2QN+eOKNtpdxUqmwxn0Vj9pyEnxzk7CC1k1b8Kopmk0540DrMb/nIWCrol+Re3KcT0vxD EwUzf0JyeYZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151680" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:13 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Honnappa Nagarahalli , Dmitry Kozlyuk , Narcisa Ana Maria Vasile , Dmitry Malloy , Pallavi Kadam , Ray Kinsella , Neil Horman Date: Thu, 15 Oct 2020 16:22:42 +0100 Message-Id: <20201015152259.97562-2-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 01/18] eal: add max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a max SIMD bitwidth EAL configuration. The API allows for an app to set this value. It can also be set using EAL argument --force-max-simd-bitwidth, which will lock the value and override any modifications made by the app. Each arch has a define for the default SIMD bitwidth value, this is used on EAL init to set the config max SIMD bitwidth. Cc: Ruifeng Wang Cc: Jerin Jacob Cc: Honnappa Nagarahalli Cc: David Christensen Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev Reviewed-by: Ruifeng Wang --- v7: Reordered entries in the symbol .map file. v4: - Used RTE_SIMD_MAX instead of UINT16_MAX. - Renamed enums to better reflect usage. - Added functions to windows symbol export file. - Modified Doxygen comments. - Modified enum name. - Changed RTE_SIMD_MAX value to a power of 2. - Merged patch 2 into this patch. - Enum now used for default value defines. - Fixed some small comments on v3. v3: - Added enum value to essentially disable using max SIMD to choose paths, intended for use by ARM SVE. - Fixed parsing bitwidth argument to return an error for values greater than uint16_t. - Removed unnecessary define in generic rte_vect.h - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. v2: - Added to Doxygen comment for API. - Changed default bitwidth for Arm to 128. --- lib/librte_eal/arm/include/rte_vect.h | 2 + lib/librte_eal/common/eal_common_options.c | 66 ++++++++++++++++++++++ lib/librte_eal/common/eal_internal_cfg.h | 8 +++ lib/librte_eal/common/eal_options.h | 2 + lib/librte_eal/include/rte_eal.h | 40 +++++++++++++ lib/librte_eal/ppc/include/rte_vect.h | 2 + lib/librte_eal/rte_eal_exports.def | 2 + lib/librte_eal/rte_eal_version.map | 2 + lib/librte_eal/x86/include/rte_vect.h | 2 + 9 files changed, 126 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index f6a455b4e7..df8fb8b670 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -14,6 +14,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_MAX + typedef int32x4_t xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c index a5426e1234..8c79f1b2fc 100644 --- a/lib/librte_eal/common/eal_common_options.c +++ b/lib/librte_eal/common/eal_common_options.c @@ -35,6 +35,7 @@ #ifndef RTE_EXEC_ENV_WINDOWS #include #endif +#include #include "eal_internal_cfg.h" #include "eal_options.h" @@ -102,6 +103,7 @@ eal_long_options[] = { {OPT_MATCH_ALLOCATIONS, 0, NULL, OPT_MATCH_ALLOCATIONS_NUM}, {OPT_TELEMETRY, 0, NULL, OPT_TELEMETRY_NUM }, {OPT_NO_TELEMETRY, 0, NULL, OPT_NO_TELEMETRY_NUM }, + {OPT_FORCE_MAX_SIMD_BITWIDTH, 1, NULL, OPT_FORCE_MAX_SIMD_BITWIDTH_NUM}, {0, 0, NULL, 0 } }; @@ -343,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg) internal_cfg->user_mbuf_pool_ops_name = NULL; CPU_ZERO(&internal_cfg->ctrl_cpuset); internal_cfg->init_complete = 0; + internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH; + internal_cfg->max_simd_bitwidth.forced = 0; } static int @@ -1309,6 +1313,34 @@ eal_parse_iova_mode(const char *name) return 0; } +static int +eal_parse_simd_bitwidth(const char *arg) +{ + char *end; + unsigned long bitwidth; + int ret; + struct internal_config *internal_conf = + eal_get_internal_configuration(); + + if (arg == NULL || arg[0] == '\0') + return -1; + + errno = 0; + bitwidth = strtoul(arg, &end, 0); + + /* check for errors */ + if (errno != 0 || end == NULL || *end != '\0' || bitwidth > RTE_SIMD_MAX) + return -1; + + if (bitwidth == 0) + bitwidth = (unsigned long) RTE_SIMD_MAX; + ret = rte_set_max_simd_bitwidth(bitwidth); + if (ret < 0) + return -1; + internal_conf->max_simd_bitwidth.forced = 1; + return 0; +} + static int eal_parse_base_virtaddr(const char *arg) { @@ -1707,6 +1739,13 @@ eal_parse_common_option(int opt, const char *optarg, case OPT_NO_TELEMETRY_NUM: conf->no_telemetry = 1; break; + case OPT_FORCE_MAX_SIMD_BITWIDTH_NUM: + if (eal_parse_simd_bitwidth(optarg) < 0) { + RTE_LOG(ERR, EAL, "invalid parameter for --" + OPT_FORCE_MAX_SIMD_BITWIDTH "\n"); + return -1; + } + break; /* don't know what to do, leave this to caller */ default: @@ -1903,6 +1942,32 @@ eal_check_common_options(struct internal_config *internal_cfg) return 0; } +uint16_t +rte_get_max_simd_bitwidth(void) +{ + const struct internal_config *internal_conf = + eal_get_internal_configuration(); + return internal_conf->max_simd_bitwidth.bitwidth; +} + +int +rte_set_max_simd_bitwidth(uint16_t bitwidth) +{ + struct internal_config *internal_conf = + eal_get_internal_configuration(); + if (internal_conf->max_simd_bitwidth.forced) { + RTE_LOG(NOTICE, EAL, "Cannot set max SIMD bitwidth - user runtime override enabled"); + return -EPERM; + } + + if (bitwidth < RTE_SIMD_DISABLED || !rte_is_power_of_2(bitwidth)) { + RTE_LOG(ERR, EAL, "Invalid bitwidth value!\n"); + return -EINVAL; + } + internal_conf->max_simd_bitwidth.bitwidth = bitwidth; + return 0; +} + void eal_common_usage(void) { @@ -1981,6 +2046,7 @@ eal_common_usage(void) " --"OPT_BASE_VIRTADDR" Base virtual address\n" " --"OPT_TELEMETRY" Enable telemetry support (on by default)\n" " --"OPT_NO_TELEMETRY" Disable telemetry support\n" + " --"OPT_FORCE_MAX_SIMD_BITWIDTH" Force the max SIMD bitwidth\n" "\nEAL options for DEBUG use only:\n" " --"OPT_HUGE_UNLINK" Unlink hugepage files after init\n" " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n" diff --git a/lib/librte_eal/common/eal_internal_cfg.h b/lib/librte_eal/common/eal_internal_cfg.h index de627c7627..51dbe86e2b 100644 --- a/lib/librte_eal/common/eal_internal_cfg.h +++ b/lib/librte_eal/common/eal_internal_cfg.h @@ -33,6 +33,12 @@ struct hugepage_info { int lock_descriptor; /**< file descriptor for hugepage dir */ }; +struct simd_bitwidth { + bool forced; + /**< flag indicating if bitwidth is forced and can't be modified */ + uint16_t bitwidth; /**< bitwidth value */ +}; + /** * internal configuration */ @@ -85,6 +91,8 @@ struct internal_config { volatile unsigned int init_complete; /**< indicates whether EAL has completed initialization */ unsigned int no_telemetry; /**< true to disable Telemetry */ + struct simd_bitwidth max_simd_bitwidth; + /**< max simd bitwidth path to use */ }; void eal_reset_internal_config(struct internal_config *internal_cfg); diff --git a/lib/librte_eal/common/eal_options.h b/lib/librte_eal/common/eal_options.h index 89769d48b4..ef33979664 100644 --- a/lib/librte_eal/common/eal_options.h +++ b/lib/librte_eal/common/eal_options.h @@ -85,6 +85,8 @@ enum { OPT_TELEMETRY_NUM, #define OPT_NO_TELEMETRY "no-telemetry" OPT_NO_TELEMETRY_NUM, +#define OPT_FORCE_MAX_SIMD_BITWIDTH "force-max-simd-bitwidth" + OPT_FORCE_MAX_SIMD_BITWIDTH_NUM, OPT_LONG_MAX_NUM }; diff --git a/lib/librte_eal/include/rte_eal.h b/lib/librte_eal/include/rte_eal.h index e3c2ef185e..706d3cca5a 100644 --- a/lib/librte_eal/include/rte_eal.h +++ b/lib/librte_eal/include/rte_eal.h @@ -43,6 +43,23 @@ enum rte_proc_type_t { RTE_PROC_INVALID }; +/** + * The max SIMD bitwidth value to limit vector path selection. + */ +enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + /**< Limits path selection to scalar, disables all vector paths. */ + RTE_SIMD_128 = 128, + /**< Limits path selection to SSE/NEON/Altivec or below. */ + RTE_SIMD_256 = 256, /**< Limits path selection to AVX2 or below. */ + RTE_SIMD_512 = 512, /**< Limits path selection to AVX512 or below. */ + RTE_SIMD_MAX = INT16_MAX + 1, + /**< + * Disables limiting by max SIMD bitwidth, allows all suitable paths. + * This value is used as it is a large number and a power of 2. + */ +}; + /** * Get the process type in a multi-process setup * @@ -51,6 +68,29 @@ enum rte_proc_type_t { */ enum rte_proc_type_t rte_eal_process_type(void); +/** + * Get the supported SIMD bitwidth. + * + * @return + * uint16_t bitwidth. + */ +__rte_experimental +uint16_t rte_get_max_simd_bitwidth(void); + +/** + * Set the supported SIMD bitwidth. + * This API should only be called once at initialization, before EAL init. + * + * @param bitwidth + * uint16_t bitwidth. + * @return + * - 0 on success. + * - -EINVAL on invalid bitwidth parameter. + * - -EPERM if bitwidth is forced. + */ +__rte_experimental +int rte_set_max_simd_bitwidth(uint16_t bitwidth); + /** * Request iopl privilege for all RPL. * diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h index b0545c878c..a69aabc568 100644 --- a/lib/librte_eal/ppc/include/rte_vect.h +++ b/lib/librte_eal/ppc/include/rte_vect.h @@ -15,6 +15,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef vector signed int xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/rte_eal_exports.def b/lib/librte_eal/rte_eal_exports.def index 16f8e33874..3516aacfe4 100644 --- a/lib/librte_eal/rte_eal_exports.def +++ b/lib/librte_eal/rte_eal_exports.def @@ -60,6 +60,7 @@ EXPORTS rte_exit rte_free rte_get_master_lcore + rte_get_max_simd_bitwidth rte_get_next_lcore rte_get_tsc_hz rte_hexdump @@ -148,6 +149,7 @@ EXPORTS rte_service_set_stats_enable rte_service_start_with_defaults rte_set_application_usage_hook + rte_set_max_simd_bitwidth rte_socket_count rte_socket_id rte_socket_id_by_idx diff --git a/lib/librte_eal/rte_eal_version.map b/lib/librte_eal/rte_eal_version.map index a93dea9fe6..c1fc1b0783 100644 --- a/lib/librte_eal/rte_eal_version.map +++ b/lib/librte_eal/rte_eal_version.map @@ -399,7 +399,9 @@ EXPERIMENTAL { # added in 20.11 __rte_eal_trace_generic_size_t; + rte_get_max_simd_bitwidth; rte_service_lcore_may_be_active; + rte_set_max_simd_bitwidth; }; INTERNAL { diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h index 64383c3606..f0aad9615e 100644 --- a/lib/librte_eal/x86/include/rte_vect.h +++ b/lib/librte_eal/x86/include/rte_vect.h @@ -36,6 +36,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef __m128i xmm_t; #define XMM_SIZE (sizeof(xmm_t)) From patchwork Thu Oct 15 15:22:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80945 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FFA6A04DB; Thu, 15 Oct 2020 17:23:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E51EA1EA4D; Thu, 15 Oct 2020 17:23:28 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 500441EA32 for ; Thu, 15 Oct 2020 17:23:25 +0200 (CEST) IronPort-SDR: zWp+Il5pkr0xGKk1zLHAjePd/N9SBUxaZyBtr2IA2IAer0egCv5Lx3D1FeGcSopJWkb7lPTTGW uGWylO7snjiQ== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909112" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909112" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:23 -0700 IronPort-SDR: TOdJ7R3SuZMT6ZMmWfQAKWRpwPgz2whUukSm5MkpPQGdQhE94D+2/NMyFLMTczebPBp76Murhw fbmL4tnyv9jg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151724" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:19 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Anatoly Burakov , John McNamara , Marko Kovacevic , Kevin Laatz Date: Thu, 15 Oct 2020 16:22:43 +0100 Message-Id: <20201015152259.97562-3-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 02/18] doc: add detail on using max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds documentation on the usage of the max SIMD bitwidth EAL setting, and how to use it to enable AVX-512 at runtime. Cc: Anatoly Burakov Cc: John McNamara Cc: Marko Kovacevic Signed-off-by: Ciara Power Acked-by: Kevin Laatz --- v6: Updated enum value. v4: Updated docs to reflect renamed enum. v3: - Added enum value for disabling use of max SIMD to doc. - Added entry to HowTo index. --- doc/guides/howto/avx512.rst | 36 +++++++++++++++++++ doc/guides/howto/index.rst | 1 + doc/guides/linux_gsg/eal_args.include.rst | 16 +++++++++ .../prog_guide/env_abstraction_layer.rst | 32 +++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 doc/guides/howto/avx512.rst diff --git a/doc/guides/howto/avx512.rst b/doc/guides/howto/avx512.rst new file mode 100644 index 0000000000..6eb3755775 --- /dev/null +++ b/doc/guides/howto/avx512.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 Intel Corporation. + + +Using AVX-512 with DPDK +======================= + +AVX-512 is not used by default in DPDK, but it can be selected at runtime by apps through the use of EAL API, +and by the user with a commandline argument. DPDK has a setting for max SIMD bitwidth, +which can be modified and will then limit the vector path taken by the code. + + +Using the API in apps +--------------------- + +Apps can request DPDK uses AVX-512 at runtime, if it provides improved application performance. +This can be done by modifying the EAL setting for max SIMD bitwidth to 512, as by default it is 256, +which does not allow for AVX-512. + +.. code-block:: c + + rte_set_max_simd_bitwidth(RTE_SIMD_512); + +This API should only be called once at initialization, before EAL init. +For more information on the possible enum values to use as a parameter, go to :ref:`max_simd_bitwidth`: + + +Using the command-line argument +--------------------------------------------- + +The user can select to use AVX-512 at runtime, using the following argument to set the max bitwidth:: + + ./app/dpdk-testpmd --force-max-simd-bitwidth=512 + +This will override any further changes to the max SIMD bitwidth in DPDK, +which is useful for testing purposes. diff --git a/doc/guides/howto/index.rst b/doc/guides/howto/index.rst index 5a97ea508c..c2a2c60ddb 100644 --- a/doc/guides/howto/index.rst +++ b/doc/guides/howto/index.rst @@ -20,3 +20,4 @@ HowTo Guides telemetry debug_troubleshoot openwrt + avx512 diff --git a/doc/guides/linux_gsg/eal_args.include.rst b/doc/guides/linux_gsg/eal_args.include.rst index 0fe4457968..a0bfbd1a98 100644 --- a/doc/guides/linux_gsg/eal_args.include.rst +++ b/doc/guides/linux_gsg/eal_args.include.rst @@ -210,3 +210,19 @@ Other options * ``--no-telemetry``: Disable telemetry. + +* ``--force-max-simd-bitwidth=``: + + Specify the maximum SIMD bitwidth size to handle. This limits which vector paths, + if any, are taken, as any paths taken must use a bitwidth below the max bitwidth limit. + For example, to allow all SIMD bitwidths up to and including AVX-512:: + + --force-max-simd-bitwidth=512 + + The following example shows limiting the bitwidth to 64-bits to disable all vector code:: + + --force-max-simd-bitwidth=64 + + To disable use of max SIMD bitwidth limit:: + + --force-max-simd-bitwidth=0 diff --git a/doc/guides/prog_guide/env_abstraction_layer.rst b/doc/guides/prog_guide/env_abstraction_layer.rst index 936c885081..90e43d2c1f 100644 --- a/doc/guides/prog_guide/env_abstraction_layer.rst +++ b/doc/guides/prog_guide/env_abstraction_layer.rst @@ -486,6 +486,38 @@ the desired addressing mode when virtual devices that are not directly attached To facilitate forcing the IOVA mode to a specific value the EAL command line option ``--iova-mode`` can be used to select either physical addressing('pa') or virtual addressing('va'). +.. _max_simd_bitwidth: + + +Max SIMD bitwidth +~~~~~~~~~~~~~~~~~ + +The EAL provides a single setting to limit the max SIMD bitwidth used by DPDK, +which is used in determining the vector path, if any, chosen by a component. +The value can be set at runtime by an application using the 'rte_set_max_simd_bitwidth(uint16_t bitwidth)' function, +which should only be called once at initialization, before EAL init. +The value can be overridden by the user using the EAL command-line option '--force-max-simd-bitwidth'. + +When choosing a vector path, along with checking the CPU feature support, +the value of the max SIMD bitwidth must also be checked, and can be retrieved using the 'rte_get_max_simd_bitwidth()' function. +The value should be compared against the enum values for accepted max SIMD bitwidths: + +.. code-block:: c + + enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + RTE_SIMD_128 = 128, + RTE_SIMD_256 = 256, + RTE_SIMD_512 = 512, + RTE_SIMD_MAX = INT16_MAX + 1, + }; + + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_512) + /* Take AVX-512 vector path */ + else if (rte_get_max_simd_bitwidth() >= RTE_SIMD_256) + /* Take AVX2 vector path */ + + Memory Segments and Memory Zones (memzone) ------------------------------------------ From patchwork Thu Oct 15 15:22:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80946 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AF58A04DB; Thu, 15 Oct 2020 17:24:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 87C6A1EA61; Thu, 15 Oct 2020 17:23:31 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id B355C1EA5D for ; Thu, 15 Oct 2020 17:23:28 +0200 (CEST) IronPort-SDR: KHHPjhEAdpNWZT+LwQ/So/et5yKMtaerhHL9C1rAqF9PoBN7vIGGMgDWKfVHOH5vcmgFGql9H7 sh9diunSXq/w== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909121" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909121" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:27 -0700 IronPort-SDR: UyYAaDC2OTsmk0nux3Q/O282HqBGwWaUHOmdsbgvkh+75c7uvl+vZujU8ij6A8Nw+2F7HGI7Op FyJt/SKI+T2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151752" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:23 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Beilei Xing , Jeff Guo Date: Thu, 15 Oct 2020 16:22:44 +0100 Message-Id: <20201015152259.97562-4-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 03/18] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Beilei Xing Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- v4: Updated enum names. --- drivers/net/i40e/i40e_rxtx.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index f2844d3f74..925fa9cc69 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -3098,7 +3098,8 @@ static eth_rx_burst_t i40e_get_latest_rx_vec(bool scatter) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) } } - if (ad->rx_vec_allowed) { + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { /* Vec Rx path */ PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.", dev->data->port_id); @@ -3268,7 +3271,8 @@ static eth_tx_burst_t i40e_get_latest_tx_vec(void) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3311,7 +3316,8 @@ i40e_set_tx_function(struct rte_eth_dev *dev) } if (ad->tx_simple_allowed) { - if (ad->tx_vec_allowed) { + if (ad->tx_vec_allowed && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); if (ad->use_latest_vec) dev->tx_pkt_burst = From patchwork Thu Oct 15 15:22:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80947 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04F98A04DB; Thu, 15 Oct 2020 17:24:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BDC8A1EA85; Thu, 15 Oct 2020 17:23:33 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id C16C51EA6D for ; Thu, 15 Oct 2020 17:23:31 +0200 (CEST) IronPort-SDR: kjSNphd+F/JpTYMluth/Ai8k26z40Lg3SPBd0y2dm2KvO1vcMpsuaThDeW3mFOLrmWxxz7AZLh wIXfNnPc104A== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909132" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909132" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:31 -0700 IronPort-SDR: e2a1DkVp3LfU1CnWyEvCa/eCbL65Endgc3r/aE/3Xjyp0qqJrg1aqX2nrrVXEpIdR/sFXZ7yef P1T2wsopjIeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151770" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:28 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Somalapuram Amaranath Date: Thu, 15 Oct 2020 16:22:45 +0100 Message-Id: <20201015152259.97562-5-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 04/18] net/axgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Somalapuram Amaranath Signed-off-by: Ciara Power Acked-by: Amaranath Somalapuram Signed-off-by: Ciara Power Acked-by: Amaranath Somalapuram Acked-by: Amaranath Somalapuram --- v4: Updated enum name. --- drivers/net/axgbe/axgbe_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index bc93becaa5..5386bd86f8 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -557,7 +557,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (!pdata->tx_queues) pdata->tx_queues = dev->data->tx_queues; - if (txq->vector_disable) + if (txq->vector_disable || rte_get_max_simd_bitwidth() + < RTE_SIMD_128) dev->tx_pkt_burst = &axgbe_xmit_pkts; else #ifdef RTE_ARCH_X86 From patchwork Thu Oct 15 15:22:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80948 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A07CA04DB; Thu, 15 Oct 2020 17:25:03 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 50BB21EA92; Thu, 15 Oct 2020 17:23:37 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id C191F1EA8E for ; Thu, 15 Oct 2020 17:23:35 +0200 (CEST) IronPort-SDR: otbecYFzu3eYkYhE+YNnvKxUhSaKM1MYf13PklnRQJI6KzRTJIuIrM5XILzzOQLjU/8Tx5SGT+ lfsxyBG7iblQ== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909144" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909144" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:35 -0700 IronPort-SDR: ELVdQUIVGt9i3zBKrhnoW7EkK+LRv/wp0SJjy1kNkzCY7Gj1hsPAcN73n+FRs4LxNPUly2FioL hMiaX9kP9w/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151793" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:31 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Ajit Khaparde , Somnath Kotur Date: Thu, 15 Oct 2020 16:22:46 +0100 Message-Id: <20201015152259.97562-6-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 05/18] net/bnxt: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Ajit Khaparde Cc: Somnath Kotur Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/bnxt/bnxt_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 8b63134c39..07d1a1a6ab 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1169,7 +1169,8 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_VLAN_FILTER)) && - !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) { + !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", eth_dev->data->port_id); bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -1202,7 +1203,8 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) */ if (!eth_dev->data->scattered_rx && !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && - !BNXT_TRUFLOW_EN(bp)) { + !BNXT_TRUFLOW_EN(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", eth_dev->data->port_id); return bnxt_xmit_pkts_vec; From patchwork Thu Oct 15 15:22:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80949 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7DA9A04DB; Thu, 15 Oct 2020 17:25:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5EB301EAA2; Thu, 15 Oct 2020 17:23:45 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 9305E1EA9D for ; Thu, 15 Oct 2020 17:23:43 +0200 (CEST) IronPort-SDR: Ab8zCyAb3F0gxb2oSFyOj/MiLmqcf567R3PaWAdlvfeluLm+VIz9lgPpxfkztg9pEbwzRwuBQM 8Ua6oEDO+emg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909153" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909153" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:39 -0700 IronPort-SDR: mdBmuVRSiArR7vQc0uVX8nDDWax1194wwVJc1EzYkqGKhEAmnp5qaye6eXEqWkq0masVaZYU8v Go4ob4IUTz9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151818" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:35 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , John Daley , Hyong Youb Kim Date: Thu, 15 Oct 2020 16:22:47 +0100 Message-Id: <20201015152259.97562-7-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 06/18] net/enic: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: John Daley Cc: Hyong Youb Kim Acked-by: Hyong Youb Kim Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c b/drivers/net/enic/enic_rxtx_vec_avx2.c index 676b9f5fdb..75e9172177 100644 --- a/drivers/net/enic/enic_rxtx_vec_avx2.c +++ b/drivers/net/enic/enic_rxtx_vec_avx2.c @@ -821,7 +821,8 @@ enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev) fconf = ð_dev->data->dev_conf.fdir_conf; if (fconf->mode != RTE_FDIR_MODE_NONE) return false; - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) { ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx handler"); eth_dev->rx_pkt_burst = &enic_noscatter_vec_recv_pkts; enic->use_noscatter_vec_rx_handler = 1; From patchwork Thu Oct 15 15:22:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80950 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E56FA04DB; Thu, 15 Oct 2020 17:25:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 024BA1EAAD; Thu, 15 Oct 2020 17:23:48 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 33E7F1EA75 for ; Thu, 15 Oct 2020 17:23:45 +0200 (CEST) IronPort-SDR: UabbpFiEy4YyypwNiv+4Xg4pgYouKMn3dwXf0dolMiwPiMmpXVGgF0W1UA/6SKqPhZozWy7fEk kFvwz6fERK1A== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909169" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909169" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:43 -0700 IronPort-SDR: GB5WCnpZ6eCAUz9J14qeZYNyvC2etW+sNQ0seEEA/3KvmTw0uHle5pokVWwItqb/LQ+WAkgKb7 kwH+ESYiOahg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151852" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:39 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Qi Zhang , Xiao Wang Date: Thu, 15 Oct 2020 16:22:48 +0100 Message-Id: <20201015152259.97562-8-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 07/18] net/fm10k: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qi Zhang Cc: Xiao Wang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- v4: Updated enum name. --- drivers/net/fm10k/fm10k_ethdev.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index c4a6fdf7f0..78c81bf35b 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -2937,7 +2937,9 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) { /* primary process has set the ftag flag and offloads */ txq = dev->data->tx_queues[0]; - if (fm10k_tx_vec_condition_check(txq)) { + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() + < RTE_SIMD_128) { dev->tx_pkt_burst = fm10k_xmit_pkts; dev->tx_pkt_prepare = fm10k_prep_pkts; PMD_INIT_LOG(DEBUG, "Use regular Tx func"); @@ -2956,7 +2958,8 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) txq = dev->data->tx_queues[i]; txq->tx_ftag_en = tx_ftag_en; /* Check if Vector Tx is satisfied */ - if (fm10k_tx_vec_condition_check(txq)) + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) use_sse = 0; } @@ -2990,7 +2993,9 @@ fm10k_set_rx_function(struct rte_eth_dev *dev) * conditions to be met. */ if (!fm10k_rx_vec_condition_check(dev) && - dev_info->rx_vec_allowed && !rx_ftag_en) { + dev_info->rx_vec_allowed && !rx_ftag_en && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { if (dev->data->scattered_rx) dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec; else From patchwork Thu Oct 15 15:22:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80952 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24414A04DB; Thu, 15 Oct 2020 17:26:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7DE391EACD; Thu, 15 Oct 2020 17:23:53 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 9FE421EAB5 for ; Thu, 15 Oct 2020 17:23:49 +0200 (CEST) IronPort-SDR: tVST1ALhAAk7vTwBDaphHpVbjpsoQ1PM/f6tSF/amhPZxcTrbVadvNenWg7iJ1tbP2ZrKXhhpj EGtNBQ1cipog== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909178" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909178" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:47 -0700 IronPort-SDR: iscl1OPjqNLD5+Ptq34YpgCe8G6I3otPZ1NBlV1HjaBWCPxsqYq+t1e26VgpDzNjDe14uitfHc YubIejnObLEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151876" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:44 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Jingjing Wu , Beilei Xing Date: Thu, 15 Oct 2020 16:22:49 +0100 Message-Id: <20201015152259.97562-9-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 08/18] net/iavf: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Jingjing Wu Cc: Beilei Xing Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/iavf/iavf_rxtx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 1b0efe0433..7c27d5beec 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -2104,14 +2104,16 @@ iavf_set_rx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_rx_vec_dev_check(dev)) { + if (!iavf_rx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; (void)iavf_rxq_vec_setup(rxq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; if (dev->data->scattered_rx) { @@ -2177,7 +2179,8 @@ iavf_set_tx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_tx_vec_dev_check(dev)) { + if (!iavf_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; if (!txq) @@ -2185,8 +2188,9 @@ iavf_set_tx_function(struct rte_eth_dev *dev) iavf_txq_vec_setup(txq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", From patchwork Thu Oct 15 15:22:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80953 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB820A04DB; Thu, 15 Oct 2020 17:27:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C666C1EAD9; Thu, 15 Oct 2020 17:23:56 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id C6F871EACD for ; Thu, 15 Oct 2020 17:23:51 +0200 (CEST) IronPort-SDR: zmuTIosc9NihUmVZGyq6rxkDWPM4qNMSf3RmF+ZMk5zMundN6rWepl0HAHovzeLjIQ35QL8rwy ZJh9ZBY++XEA== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909184" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909184" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:51 -0700 IronPort-SDR: Vb6wbnalLHjXlj9n+xa2J2F2Pyb52MR3BvKHPcGhmA+3HEpOdu//AAMRWe/9LlgeKofglCcG7r 28jc93xT5A6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151897" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:48 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Qiming Yang , Qi Zhang Date: Thu, 15 Oct 2020 16:22:50 +0100 Message-Id: <20201015152259.97562-10-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 09/18] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- v4: Updated enum name. --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 79e6df11f4..a1a6d4ac56 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2989,7 +2989,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2999,8 +3001,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { @@ -3167,7 +3171,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3177,8 +3183,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { From patchwork Thu Oct 15 15:22:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80954 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD56CA04DB; Thu, 15 Oct 2020 17:27:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 006A01EAE5; Thu, 15 Oct 2020 17:23:58 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 15F3E1EAD5 for ; Thu, 15 Oct 2020 17:23:55 +0200 (CEST) IronPort-SDR: NbUW7o/qFO6NnxSeouZCOrLfUR6ePT9CFWMSHrJppjvCEwtjp6Js6jP5xWdluzb3kAcWe/2t1F +bwl3fTLyPCw== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909192" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909192" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:23:55 -0700 IronPort-SDR: n8V0sbcQHuGOtoofuhzZVtIGBw7TJCzvx56b7IIseC11BFoRt6RjhLTUiGSyziC7VqFYqBQ4Vt LdRTlczTlBpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151921" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:51 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Wei Zhao , Jeff Guo , Haiyue Wang Date: Thu, 15 Oct 2020 16:22:51 +0100 Message-Id: <20201015152259.97562-11-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 10/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Wei Zhao Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev Reviewed-by: Haiyue Wang --- v4: - Updated enum name. - Moved placement of condition check. - Added condition check to tx cleanup path selection. --- drivers/net/ixgbe/ixgbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 29d385c062..3141398e10 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2405,6 +2405,7 @@ ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) #endif txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) { if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || txq->sw_ring_v != NULL)) { return ixgbe_tx_done_cleanup_vec(txq, free_cnt); @@ -2503,6 +2504,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq) PMD_INIT_LOG(DEBUG, "Using simple tx code path"); dev->tx_pkt_prepare = NULL; if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || ixgbe_txq_vec_setup(txq) == 0)) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); @@ -4744,7 +4746,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) * conditions to be met and Rx Bulk Allocation should be allowed. */ if (ixgbe_rx_vec_dev_conf_condition_check(dev) || - !adapter->rx_bulk_alloc_allowed) { + !adapter->rx_bulk_alloc_allowed || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " "preconditions", dev->data->port_id); From patchwork Thu Oct 15 15:22:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80955 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57D9FA04DB; Thu, 15 Oct 2020 17:27:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 53F1A1EAF1; Thu, 15 Oct 2020 17:24:02 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id B30FF1EAEE for ; Thu, 15 Oct 2020 17:24:00 +0200 (CEST) IronPort-SDR: wEA7xikE0kXXdCcaGID+Ro675uYxtyoSXTMVVJVxlylcz8ySc2o4g/wPFV7b4n4j8HgrMGKvrr 4D26+labRpBQ== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909206" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909206" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:00 -0700 IronPort-SDR: mYqlCrCnnVRO7Ia9BRKAiHfGKSo1v77nUscMq8iQ+DYURM80R9U3RTrBWs4ZfVYStitBZnvuzv RvxwSIjiN2IQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346151944" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:56 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko , Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler Date: Thu, 15 Oct 2020 16:22:52 +0100 Message-Id: <20201015152259.97562-12-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 11/18] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power Acked-by: Viacheslav Ovsiienko --- v4: Updated enum name. v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..49f1b61ff8 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) From patchwork Thu Oct 15 15:22:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80956 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 185F9A04DB; Thu, 15 Oct 2020 17:28:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DF9F21EAFA; Thu, 15 Oct 2020 17:24:06 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 080511EAC5 for ; Thu, 15 Oct 2020 17:24:04 +0200 (CEST) IronPort-SDR: JJJN0pLml06Ei/E5mhEyaV/SDPM+sU8L8fe6W/D/khdEkp8gUQrbt5vnXT/G/l0+OHF4RWfOjs gjaDtBQ5fL2g== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909230" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909230" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:04 -0700 IronPort-SDR: suCzz71V/DM15OXoNGHxCli13XoRGq4jOw+guAnc/F+QVmr7g7ba1z4YHl7XFRjcjTapytpGVB VkHTH6+hStKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152012" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:00 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Maxime Coquelin , Chenbo Xia , Zhihong Wang Date: Thu, 15 Oct 2020 16:22:53 +0100 Message-Id: <20201015152259.97562-13-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 12/18] net/virtio: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Maxime Coquelin Cc: Chenbo Xia Cc: Zhihong Wang Signed-off-by: Ciara Power Reviewed-by: Chenbo Xia Acked-by: Maxime Coquelin --- v4: Updated enum name. v3: Moved max SIMD bitwidth check to configure function with other vec support checks. --- drivers/net/virtio/virtio_ethdev.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c index 65eefa2a31..8560c406de 100644 --- a/drivers/net/virtio/virtio_ethdev.c +++ b/drivers/net/virtio/virtio_ethdev.c @@ -2313,7 +2313,8 @@ virtio_dev_configure(struct rte_eth_dev *dev) if ((hw->use_vec_rx || hw->use_vec_tx) && (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) || !vtpci_with_feature(hw, VIRTIO_F_IN_ORDER) || - !vtpci_with_feature(hw, VIRTIO_F_VERSION_1))) { + !vtpci_with_feature(hw, VIRTIO_F_VERSION_1) || + rte_get_max_simd_bitwidth() < RTE_SIMD_512)) { PMD_DRV_LOG(INFO, "disabled packed ring vectorized path for requirements not met"); hw->use_vec_rx = 0; @@ -2366,6 +2367,12 @@ virtio_dev_configure(struct rte_eth_dev *dev) "disabled split ring vectorized rx for offloading enabled"); hw->use_vec_rx = 0; } + + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) { + PMD_DRV_LOG(INFO, + "disabled split ring vectorized rx, max SIMD bitwidth too low"); + hw->use_vec_rx = 0; + } } } From patchwork Thu Oct 15 15:22:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80957 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB3B7A04DB; Thu, 15 Oct 2020 17:28:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 79CAF1EB09; Thu, 15 Oct 2020 17:24:10 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 63FD71EB06 for ; Thu, 15 Oct 2020 17:24:08 +0200 (CEST) IronPort-SDR: NPN0cbWNAwM+PZRuHCWHpwK7HI7pVxMf3+ilPFVTPmg9Ski9la6VWu2MsNL/iGxLy5CyF5e1V4 UURVEVVa93fw== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909241" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909241" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:08 -0700 IronPort-SDR: V+MT0HfYBc+wUPrGb5P9ZnBFrE2XwnE7nJFci9dshRHRF6abwwDdo9u4JxtlV2xXz3qWfDJU2v HPysgjOPpP4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152029" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:05 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , David Hunt Date: Thu, 15 Oct 2020 16:22:54 +0100 Message-Id: <20201015152259.97562-14-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 13/18] distributor: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: David Hunt Signed-off-by: Ciara Power Acked-by: David Hunt --- v4: Updated enum name. --- lib/librte_distributor/rte_distributor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c index 1c047f065a..05e61dddfc 100644 --- a/lib/librte_distributor/rte_distributor.c +++ b/lib/librte_distributor/rte_distributor.c @@ -636,7 +636,8 @@ rte_distributor_create(const char *name, d->dist_match_fn = RTE_DIST_MATCH_SCALAR; #if defined(RTE_ARCH_X86) - d->dist_match_fn = RTE_DIST_MATCH_VECTOR; + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + d->dist_match_fn = RTE_DIST_MATCH_VECTOR; #endif /* From patchwork Thu Oct 15 15:22:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80958 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81175A04DB; Thu, 15 Oct 2020 17:29:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E781D1EB21; Thu, 15 Oct 2020 17:24:13 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 400F81EB0E for ; Thu, 15 Oct 2020 17:24:12 +0200 (CEST) IronPort-SDR: E6rzuWuyxVoxmyJurNkeYM4JawTCpEj3hf3MVzlZDQ1DD6pZuNnJWxFwYefN6JLlZb5Tm85k8z 8GkWlAXPWYmg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909256" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909256" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:11 -0700 IronPort-SDR: S9NGOG9ehHzvKHw8HhQah2b/wExqGKo41ANXDrbr/5HbheRAhiViyGaR8Lic1EsY3i1hMXvFHn jrYWEG1c28Ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152069" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:08 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Yipeng Wang , Sameh Gobriel Date: Thu, 15 Oct 2020 16:22:55 +0100 Message-Id: <20201015152259.97562-15-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 14/18] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Yipeng Wang Cc: Sameh Gobriel Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_member/rte_member_ht.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_member/rte_member_ht.c b/lib/librte_member/rte_member_ht.c index 3ea293a094..98c8aac248 100644 --- a/lib/librte_member/rte_member_ht.c +++ b/lib/librte_member/rte_member_ht.c @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum *ss, } #if defined(RTE_ARCH_X86) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && - RTE_MEMBER_BUCKET_ENTRIES == 16) + RTE_MEMBER_BUCKET_ENTRIES == 16 && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) ss->sig_cmp_fn = RTE_MEMBER_COMPARE_AVX2; else #endif From patchwork Thu Oct 15 15:22:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80959 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1562DA04DB; Thu, 15 Oct 2020 17:29:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 340B31EB26; Thu, 15 Oct 2020 17:24:19 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 03ABC1EB26 for ; Thu, 15 Oct 2020 17:24:15 +0200 (CEST) IronPort-SDR: 2teXusVT1WWzJPDNEmfBNVRu+FfuxFNtIf5BP0TR78zclT6jjCkHPW9i1V9YRscTPsvoEGniXR rW4RVSO3cTJQ== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909265" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909265" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:15 -0700 IronPort-SDR: ETP0HH1DsA8HxvpKZwDJBG4ZtXwbK5HIBVs6ehLYqGSrNE3Rz/1bzArR4zcD4Loy/p3WzKwi6V 0t6Gi47mv3DQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152119" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:12 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Byron Marohn , Yipeng Wang Date: Thu, 15 Oct 2020 16:22:56 +0100 Message-Id: <20201015152259.97562-16-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 15/18] efd: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Byron Marohn Cc: Yipeng Wang Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_efd/rte_efd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/librte_efd/rte_efd.c b/lib/librte_efd/rte_efd.c index 6a799556d4..e925b73a9c 100644 --- a/lib/librte_efd/rte_efd.c +++ b/lib/librte_efd/rte_efd.c @@ -645,7 +645,9 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * For less than 4 bits, scalar function performs better * than vectorised version */ - if (RTE_EFD_VALUE_NUM_BITS > 3 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (RTE_EFD_VALUE_NUM_BITS > 3 + && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) + && rte_get_max_simd_bitwidth() >= RTE_SIMD_256) table->lookup_fn = EFD_LOOKUP_AVX2; else #endif @@ -655,7 +657,8 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * than vectorised version */ if (RTE_EFD_VALUE_NUM_BITS > 16 && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) table->lookup_fn = EFD_LOOKUP_NEON; else #endif From patchwork Thu Oct 15 15:22:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80960 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01E05A04DB; Thu, 15 Oct 2020 17:29:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8A82E1EB19; Thu, 15 Oct 2020 17:24:23 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id DEC331EB16 for ; Thu, 15 Oct 2020 17:24:19 +0200 (CEST) IronPort-SDR: tWyEv4CpxT8AsW746lUIE0iKhaNYG+W7i/mmvUavDcRz53F8sCU+vxGXlr8ucoiL+u0/QNxpvT ort45GV7DR2w== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909274" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909274" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:19 -0700 IronPort-SDR: gfWeAQUKEexDIoOCW/dRKgZ/+a+bYj1xqe3b0H7Uh+xetG9L1+h3JnefLM3e8Rk+X6akfzy2yX qPHedJhDlMZw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152155" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:16 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Jasvinder Singh , Olivier Matz Date: Thu, 15 Oct 2020 16:22:57 +0100 Message-Id: <20201015152259.97562-17-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 16/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. The vector path was initially chosen in RTE_INIT, however this is no longer suitable as we cannot check the max SIMD bitwidth at that time. Default handlers are now chosen on initialisation, these default handlers are used the first time the crc calc is called, and they set the suitable handlers to be used going forward. Suggested-by: Jasvinder Singh Suggested-by: Olivier Matz Signed-off-by: Ciara Power Acked-by: Jasvinder Singh --- v7: Removed unnecessary log variable. v6: - Moved log variable and macro to c file instead of public header. - Added the max_simd_bitwidth condition check to the recently added handler helper functions. - Modified default handlers to follow the approach of the set alg function. v4: - Added default handlers to be set at RTE_INIT time, rather than choosing scalar handlers. - Modified logging. - Updated enum name. v3: - Moved choosing vector paths out of RTE_INIT. - Moved checking max_simd_bitwidth into the set_alg function. --- lib/librte_net/rte_net_crc.c | 116 +++++++++++++++++++++++++---------- 1 file changed, 85 insertions(+), 31 deletions(-) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 32a3665908..c2ff82bbd6 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include "net_crc.h" @@ -22,6 +24,12 @@ static uint32_t crc32_eth_lut[CRC_LUT_SIZE]; static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE]; +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len); + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len); + static uint32_t rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len); @@ -31,7 +39,12 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len); typedef uint32_t (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len); -static const rte_net_crc_handler *handlers; +static rte_net_crc_handler handlers_default[] = { + [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler, + [RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler, +}; + +static const rte_net_crc_handler *handlers = handlers_default; static const rte_net_crc_handler handlers_scalar[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler, @@ -56,6 +69,14 @@ static const rte_net_crc_handler handlers_neon[] = { }; #endif +static uint16_t max_simd_bitwidth; + +#define NET_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, libnet_logtype, "%s(): " fmt "\n", \ + __func__, ## args) + +RTE_LOG_REGISTER(libnet_logtype, lib.net, INFO); + /* Scalar handling */ /** @@ -155,22 +176,21 @@ static const rte_net_crc_handler * avx512_vpclmulqdq_get_handlers(void) { #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_512) return handlers_avx512; #endif + NET_LOG(INFO, "Requirements not met, can't use AVX512\n"); return NULL; } -static uint8_t +static void avx512_vpclmulqdq_init(void) { #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) { + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) rte_net_crc_avx512_init(); - return 1; - } #endif - return 0; } /* SSE4.2/PCLMULQDQ handling */ @@ -182,22 +202,21 @@ static const rte_net_crc_handler * sse42_pclmulqdq_get_handlers(void) { #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) + if (SSE42_PCLMULQDQ_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_128) return handlers_sse42; #endif + NET_LOG(INFO, "Requirements not met, can't use SSE\n"); return NULL; } -static uint8_t +static void sse42_pclmulqdq_init(void) { #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) { + if (SSE42_PCLMULQDQ_CPU_SUPPORTED) rte_net_crc_sse42_init(); - return 1; - } #endif - return 0; } /* NEON/PMULL handling */ @@ -209,22 +228,63 @@ static const rte_net_crc_handler * neon_pmull_get_handlers(void) { #ifdef CC_ARM64_NEON_PMULL_SUPPORT - if (NEON_PMULL_CPU_SUPPORTED) + if (NEON_PMULL_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_128) return handlers_neon; #endif + NET_LOG(INFO, "Requirements not met, can't use NEON\n"); return NULL; } -static uint8_t +static void neon_pmull_init(void) { #ifdef CC_ARM64_NEON_PMULL_SUPPORT - if (NEON_PMULL_CPU_SUPPORTED) { + if (NEON_PMULL_CPU_SUPPORTED) rte_net_crc_neon_init(); - return 1; - } #endif - return 0; +} + +/* Default handling */ + +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len) +{ + handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + + handlers = avx512_vpclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = sse42_pclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = neon_pmull_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = handlers_scalar; + return handlers[RTE_NET_CRC16_CCITT](data, data_len); +} + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len) +{ + handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + + handlers = avx512_vpclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = sse42_pclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = neon_pmull_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = handlers_scalar; + return handlers[RTE_NET_CRC32_ETH](data, data_len); } /* Public API */ @@ -233,6 +293,8 @@ void rte_net_crc_set_alg(enum rte_net_crc_alg alg) { handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); switch (alg) { case RTE_NET_CRC_AVX512: @@ -270,19 +332,11 @@ rte_net_crc_calc(const void *data, return ret; } -/* Select highest available crc algorithm as default one */ +/* Call initialisation helpers for all crc algorithm handlers */ RTE_INIT(rte_net_crc_init) { - enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR; - rte_net_crc_scalar_init(); - - if (sse42_pclmulqdq_init()) - alg = RTE_NET_CRC_SSE42; - if (avx512_vpclmulqdq_init()) - alg = RTE_NET_CRC_AVX512; - if (neon_pmull_init()) - alg = RTE_NET_CRC_NEON; - - rte_net_crc_set_alg(alg); + sse42_pclmulqdq_init(); + avx512_vpclmulqdq_init(); + neon_pmull_init(); } From patchwork Thu Oct 15 15:22:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80961 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30561A04DB; Thu, 15 Oct 2020 17:30:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 26AA61EB30; Thu, 15 Oct 2020 17:24:26 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id E65C41EB30 for ; Thu, 15 Oct 2020 17:24:23 +0200 (CEST) IronPort-SDR: kwEkylXS1j0sfBjdFrLGv+hOnAJIx2jZeYYMIaUFSD5Oy2yTrj1tT39jWzDlOxquMPedthNjGs EspgolqNxTQA== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909287" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909287" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:23 -0700 IronPort-SDR: yBNFEaeGREMgmDQoCw16eJsFKwVk9BsDeC9et4D/4QpbIT1U2ldLHcn0Mh1Rf9/ocJTgdAhql4 Qkf9Hgu/1lQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152196" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:19 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power , Nithin Dabilpuram , Pavan Nikhilesh , Kiran Kumar K Date: Thu, 15 Oct 2020 16:22:58 +0100 Message-Id: <20201015152259.97562-18-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 17/18] node: choose vector path at runtime X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing the vector path, max SIMD bitwidth is now checked to ensure the vector path is suitable. To do this, the scalar function is chosen by default in the struct, but at node initialisation time, this function pointer is updated to the vector version if supported, and if it is within the max SIMD bitwidth limit. Cc: Nithin Dabilpuram Cc: Pavan Nikhilesh Cc: Jerin Jacob Cc: Kiran Kumar K Signed-off-by: Ciara Power Acked-by: Nithin Dabilpuram --- v6: - Removed generic process function. - Change the process function pointer at node init time to vector function if suitable. --- lib/librte_node/ip4_lookup.c | 14 +++++++++----- lib/librte_node/ip4_lookup_neon.h | 2 +- lib/librte_node/ip4_lookup_sse.h | 2 +- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/lib/librte_node/ip4_lookup.c b/lib/librte_node/ip4_lookup.c index 293c77f39e..934a6d7eab 100644 --- a/lib/librte_node/ip4_lookup.c +++ b/lib/librte_node/ip4_lookup.c @@ -34,10 +34,10 @@ static struct ip4_lookup_node_main ip4_lookup_nm; #include "ip4_lookup_neon.h" #elif defined(RTE_ARCH_X86) #include "ip4_lookup_sse.h" -#else +#endif static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_scalar(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_ipv4_hdr *ipv4_hdr; @@ -109,8 +109,6 @@ ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, return nb_objs; } -#endif - int rte_node_ip4_route_add(uint32_t ip, uint8_t depth, uint16_t next_hop, enum rte_node_ip4_lookup_next next_node) @@ -194,13 +192,19 @@ ip4_lookup_node_init(const struct rte_graph *graph, struct rte_node *node) init_once = 1; } *lpm_p = ip4_lookup_nm.lpm_tbl[graph->socket]; + +#if defined(__ARM_NEON) || defined(RTE_ARCH_X86) + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + node->process = ip4_lookup_node_process_vec; +#endif + node_dbg("ip4_lookup", "Initialized ip4_lookup node"); return 0; } static struct rte_node_register ip4_lookup_node = { - .process = ip4_lookup_node_process, + .process = ip4_lookup_node_process_scalar, .name = "ip4_lookup", .init = ip4_lookup_node_init, diff --git a/lib/librte_node/ip4_lookup_neon.h b/lib/librte_node/ip4_lookup_neon.h index 5e5a7d87be..0ad2763b82 100644 --- a/lib/librte_node/ip4_lookup_neon.h +++ b/lib/librte_node/ip4_lookup_neon.h @@ -7,7 +7,7 @@ /* ARM64 NEON */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts; diff --git a/lib/librte_node/ip4_lookup_sse.h b/lib/librte_node/ip4_lookup_sse.h index a071cc5919..264c986071 100644 --- a/lib/librte_node/ip4_lookup_sse.h +++ b/lib/librte_node/ip4_lookup_sse.h @@ -7,7 +7,7 @@ /* X86 SSE */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts; From patchwork Thu Oct 15 15:22:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80962 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88829A04DB; Thu, 15 Oct 2020 17:30:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 99D4E1EB50; Thu, 15 Oct 2020 17:24:31 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D128E1EB2A for ; Thu, 15 Oct 2020 17:24:27 +0200 (CEST) IronPort-SDR: +uVZshg3/YR/e/yBT3mxy5YHBakvOYvjMKxbmeHplyuheyfUYoj064oz9rMKA8EjJmHVKtEpJA 5epor9fiYWZg== X-IronPort-AV: E=McAfee;i="6000,8403,9775"; a="162909291" X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="162909291" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 08:24:26 -0700 IronPort-SDR: QEFX4Nl0msUtXOoY7YW2b5EkhZMfGkJX18hasLW7NQPGezFGn/g3kCrIIYHAoDYE4YcSXqCZuA ZyJFCJXdXkRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,379,1596524400"; d="scan'208";a="346152215" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:23 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power Date: Thu, 15 Oct 2020 16:22:59 +0100 Message-Id: <20201015152259.97562-19-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015152259.97562-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v7 18/18] acl: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. These checks are added in the check alg helper functions. Cc: Konstantin Ananyev Signed-off-by: Ciara Power --- v7: - Removed global variable for max SIMD bitwidth. - Added helper function for checking AVX512 cpu flags. - Separated condition checking for the AVX512 algorithms to allow for checking 256/512 max SIMD bitwidth, respectively. - Added to docs to reflect the added changes in algorithm selection. --- .../prog_guide/packet_classif_access_ctrl.rst | 14 ++++-- lib/librte_acl/rte_acl.c | 48 ++++++++++++++----- lib/librte_acl/rte_acl.h | 1 + 3 files changed, 48 insertions(+), 15 deletions(-) diff --git a/doc/guides/prog_guide/packet_classif_access_ctrl.rst b/doc/guides/prog_guide/packet_classif_access_ctrl.rst index 7659af8eb5..72c193b17f 100644 --- a/doc/guides/prog_guide/packet_classif_access_ctrl.rst +++ b/doc/guides/prog_guide/packet_classif_access_ctrl.rst @@ -368,34 +368,40 @@ After rte_acl_build() over given AC context has finished successfully, it can be There are several implementations of classify algorithm: * **RTE_ACL_CLASSIFY_SCALAR**: generic implementation, doesn't require any specific HW support. + Requires max SIMD bitwidth to be at least 64. * **RTE_ACL_CLASSIFY_SSE**: vector implementation, can process up to 8 flows in parallel. Requires SSE 4.1 support. + Requires max SIMD bitwidth to be at least 128. * **RTE_ACL_CLASSIFY_AVX2**: vector implementation, can process up to 16 flows in parallel. Requires AVX2 support. + Requires max SIMD bitwidth to be at least 256. * **RTE_ACL_CLASSIFY_NEON**: vector implementation, can process up to 8 flows - in parallel. Requires NEON support. + in parallel. Requires NEON support. Requires max SIMD bitwidth to be at least 128. * **RTE_ACL_CLASSIFY_ALTIVEC**: vector implementation, can process up to 8 - flows in parallel. Requires ALTIVEC support. + flows in parallel. Requires ALTIVEC support. Requires max SIMD bitwidth to be at least 128. * **RTE_ACL_CLASSIFY_AVX512X16**: vector implementation, can process up to 16 flows in parallel. Uses 256-bit width SIMD registers. - Requires AVX512 support. + Requires AVX512 support. Requires max SIMD bitwidth to be at least 256. * **RTE_ACL_CLASSIFY_AVX512X32**: vector implementation, can process up to 32 flows in parallel. Uses 512-bit width SIMD registers. - Requires AVX512 support. + Requires AVX512 support. Requires max SIMD bitwidth to be at least 512. It is purely a runtime decision which method to choose, there is no build-time difference. All implementations operates over the same internal RT structures and use similar principles. The main difference is that vector implementations can manually exploit IA SIMD instructions and process several input data flows in parallel. At startup ACL library determines the highest available classify method for the given platform and sets it as default one. Though the user has an ability to override the default classifier function for a given ACL context or perform particular search using non-default classify method. In that case it is user responsibility to make sure that given platform supports selected classify implementation. +The max SIMD bitwidth value set in EAL is also taken into consideration when determining if a classify method is supported, see :ref:`max_simd_bitwidth` for more information. .. note:: Right now ``RTE_ACL_CLASSIFY_AVX512X32`` is not selected by default (due to possible frequency level change), but it can be selected at runtime by apps through the use of ACL API: ``rte_acl_set_ctx_classify``. + The max SIMD bitwidth value will also need to be set to 512 to enable this classify method. + See :doc:`../howto/avx512` for more information about setting this value. Application Programming Interface (API) Usage --------------------------------------------- diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index 7c2f60b2d6..026d2e7430 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -114,9 +114,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_NEON) { #if defined(RTE_ARCH_ARM64) - return 0; + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #elif defined(RTE_ARCH_ARM) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) return 0; return -ENOTSUP; #else @@ -136,7 +140,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_ALTIVEC) { #if defined(RTE_ARCH_PPC_64) - return 0; + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #else return -ENOTSUP; #endif @@ -145,6 +152,17 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) return -EINVAL; } +#ifdef CC_AVX512_SUPPORT +static int +acl_check_avx512_cpu_flags(void) +{ + return (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)); +} +#endif + /* * Helper function for acl_check_alg. * Check support for x86 specific classify methods. @@ -152,13 +170,19 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) static int acl_check_alg_x86(enum rte_acl_classify_alg alg) { - if (alg == RTE_ACL_CLASSIFY_AVX512X16 || - alg == RTE_ACL_CLASSIFY_AVX512X32) { + if (alg == RTE_ACL_CLASSIFY_AVX512X32) { #ifdef CC_AVX512_SUPPORT - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)) + if (acl_check_avx512_cpu_flags() != 0 && + rte_get_max_simd_bitwidth() >= RTE_SIMD_512) + return 0; +#endif + return -ENOTSUP; + } + + if (alg == RTE_ACL_CLASSIFY_AVX512X16) { +#ifdef CC_AVX512_SUPPORT + if (acl_check_avx512_cpu_flags() != 0 && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return 0; #endif return -ENOTSUP; @@ -166,7 +190,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_AVX2) { #ifdef CC_AVX2_SUPPORT - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return 0; #endif return -ENOTSUP; @@ -174,7 +199,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_SSE) { #ifdef RTE_ARCH_X86 - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) return 0; #endif return -ENOTSUP; diff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h index 1bfed00743..f7f5f08701 100644 --- a/lib/librte_acl/rte_acl.h +++ b/lib/librte_acl/rte_acl.h @@ -329,6 +329,7 @@ rte_acl_classify_alg(const struct rte_acl_ctx *ctx, * New default classify algorithm for given ACL context. * It is the caller responsibility to ensure that the value refers to the * existing algorithm, and that it could be run on the given CPU. + * The max SIMD bitwidth value in EAL must also allow for the chosen algorithm. * @return * - -EINVAL if the parameters are invalid. * - -ENOTSUP requested algorithm is not supported by given platform.