From patchwork Tue Oct 13 10:38:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80454 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DF73A04B7; Tue, 13 Oct 2020 12:38:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 947E41DA32; Tue, 13 Oct 2020 12:38:29 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id BA6C61DA08 for ; Tue, 13 Oct 2020 12:38:26 +0200 (CEST) IronPort-SDR: cWqjlkSst9V2E2syMlAzTuSp54hz5Ch0Tpbduwp27LIASFwIN/eQV4lQgHyOcCR94Uqx0cZeCD HPuTcaWjcYnA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998189" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998189" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:26 -0700 IronPort-SDR: XzFPbWy/qZ4Zb0b5Vfn99e6iaZSCKUo/20yrhNfeFzzOC3fT6np96A+OqO9ao9X0jUJG6CULNZ igA83L3W6n3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442925" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:22 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Honnappa Nagarahalli , Dmitry Kozlyuk , Narcisa Ana Maria Vasile , Dmitry Malloy , Pallavi Kadam , Ray Kinsella , Neil Horman Date: Tue, 13 Oct 2020 11:38:01 +0100 Message-Id: <20201013103817.305423-2-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 01/17] eal: add max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a max SIMD bitwidth EAL configuration. The API allows for an app to set this value. It can also be set using EAL argument --force-max-simd-bitwidth, which will lock the value and override any modifications made by the app. Each arch has a define for the default SIMD bitwidth value, this is used on EAL init to set the config max SIMD bitwidth. Cc: Ruifeng Wang Cc: Jerin Jacob Cc: Honnappa Nagarahalli Cc: David Christensen Signed-off-by: Ciara Power --- v4: - Used RTE_SIMD_MAX instead of UINT16_MAX. - Renamed enums to better reflect usage. - Added functions to windows symbol export file. - Modified Doxygen comments. - Modified enum name. - Changed RTE_SIMD_MAX value to a power of 2. - Merged patch 2 into this patch. - Enum now used for default value defines. - Fixed some small comments on v3. v3: - Added enum value to essentially disable using max SIMD to choose paths, intended for use by ARM SVE. - Fixed parsing bitwidth argument to return an error for values greater than uint16_t. - Removed unnecessary define in generic rte_vect.h - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. v2: - Added to Doxygen comment for API. - Changed default bitwidth for Arm to 128. --- lib/librte_eal/arm/include/rte_vect.h | 2 + lib/librte_eal/common/eal_common_options.c | 66 ++++++++++++++++++++++ lib/librte_eal/common/eal_internal_cfg.h | 8 +++ lib/librte_eal/common/eal_options.h | 2 + lib/librte_eal/include/rte_eal.h | 40 +++++++++++++ lib/librte_eal/ppc/include/rte_vect.h | 2 + lib/librte_eal/rte_eal_exports.def | 2 + lib/librte_eal/rte_eal_version.map | 2 + lib/librte_eal/x86/include/rte_vect.h | 2 + 9 files changed, 126 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index 01c51712a1..f53c89be97 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -14,6 +14,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_MAX + typedef int32x4_t xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c index a5426e1234..8c79f1b2fc 100644 --- a/lib/librte_eal/common/eal_common_options.c +++ b/lib/librte_eal/common/eal_common_options.c @@ -35,6 +35,7 @@ #ifndef RTE_EXEC_ENV_WINDOWS #include #endif +#include #include "eal_internal_cfg.h" #include "eal_options.h" @@ -102,6 +103,7 @@ eal_long_options[] = { {OPT_MATCH_ALLOCATIONS, 0, NULL, OPT_MATCH_ALLOCATIONS_NUM}, {OPT_TELEMETRY, 0, NULL, OPT_TELEMETRY_NUM }, {OPT_NO_TELEMETRY, 0, NULL, OPT_NO_TELEMETRY_NUM }, + {OPT_FORCE_MAX_SIMD_BITWIDTH, 1, NULL, OPT_FORCE_MAX_SIMD_BITWIDTH_NUM}, {0, 0, NULL, 0 } }; @@ -343,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg) internal_cfg->user_mbuf_pool_ops_name = NULL; CPU_ZERO(&internal_cfg->ctrl_cpuset); internal_cfg->init_complete = 0; + internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH; + internal_cfg->max_simd_bitwidth.forced = 0; } static int @@ -1309,6 +1313,34 @@ eal_parse_iova_mode(const char *name) return 0; } +static int +eal_parse_simd_bitwidth(const char *arg) +{ + char *end; + unsigned long bitwidth; + int ret; + struct internal_config *internal_conf = + eal_get_internal_configuration(); + + if (arg == NULL || arg[0] == '\0') + return -1; + + errno = 0; + bitwidth = strtoul(arg, &end, 0); + + /* check for errors */ + if (errno != 0 || end == NULL || *end != '\0' || bitwidth > RTE_SIMD_MAX) + return -1; + + if (bitwidth == 0) + bitwidth = (unsigned long) RTE_SIMD_MAX; + ret = rte_set_max_simd_bitwidth(bitwidth); + if (ret < 0) + return -1; + internal_conf->max_simd_bitwidth.forced = 1; + return 0; +} + static int eal_parse_base_virtaddr(const char *arg) { @@ -1707,6 +1739,13 @@ eal_parse_common_option(int opt, const char *optarg, case OPT_NO_TELEMETRY_NUM: conf->no_telemetry = 1; break; + case OPT_FORCE_MAX_SIMD_BITWIDTH_NUM: + if (eal_parse_simd_bitwidth(optarg) < 0) { + RTE_LOG(ERR, EAL, "invalid parameter for --" + OPT_FORCE_MAX_SIMD_BITWIDTH "\n"); + return -1; + } + break; /* don't know what to do, leave this to caller */ default: @@ -1903,6 +1942,32 @@ eal_check_common_options(struct internal_config *internal_cfg) return 0; } +uint16_t +rte_get_max_simd_bitwidth(void) +{ + const struct internal_config *internal_conf = + eal_get_internal_configuration(); + return internal_conf->max_simd_bitwidth.bitwidth; +} + +int +rte_set_max_simd_bitwidth(uint16_t bitwidth) +{ + struct internal_config *internal_conf = + eal_get_internal_configuration(); + if (internal_conf->max_simd_bitwidth.forced) { + RTE_LOG(NOTICE, EAL, "Cannot set max SIMD bitwidth - user runtime override enabled"); + return -EPERM; + } + + if (bitwidth < RTE_SIMD_DISABLED || !rte_is_power_of_2(bitwidth)) { + RTE_LOG(ERR, EAL, "Invalid bitwidth value!\n"); + return -EINVAL; + } + internal_conf->max_simd_bitwidth.bitwidth = bitwidth; + return 0; +} + void eal_common_usage(void) { @@ -1981,6 +2046,7 @@ eal_common_usage(void) " --"OPT_BASE_VIRTADDR" Base virtual address\n" " --"OPT_TELEMETRY" Enable telemetry support (on by default)\n" " --"OPT_NO_TELEMETRY" Disable telemetry support\n" + " --"OPT_FORCE_MAX_SIMD_BITWIDTH" Force the max SIMD bitwidth\n" "\nEAL options for DEBUG use only:\n" " --"OPT_HUGE_UNLINK" Unlink hugepage files after init\n" " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n" diff --git a/lib/librte_eal/common/eal_internal_cfg.h b/lib/librte_eal/common/eal_internal_cfg.h index 13f93388a7..0c880cbe17 100644 --- a/lib/librte_eal/common/eal_internal_cfg.h +++ b/lib/librte_eal/common/eal_internal_cfg.h @@ -33,6 +33,12 @@ struct hugepage_info { int lock_descriptor; /**< file descriptor for hugepage dir */ }; +struct simd_bitwidth { + bool forced; + /**< flag indicating if bitwidth is forced and can't be modified */ + uint16_t bitwidth; /**< bitwidth value */ +}; + /** * internal configuration */ @@ -85,6 +91,8 @@ struct internal_config { volatile unsigned int init_complete; /**< indicates whether EAL has completed initialization */ unsigned int no_telemetry; /**< true to disable Telemetry */ + struct simd_bitwidth max_simd_bitwidth; + /**< max simd bitwidth path to use */ }; void eal_reset_internal_config(struct internal_config *internal_cfg); diff --git a/lib/librte_eal/common/eal_options.h b/lib/librte_eal/common/eal_options.h index 89769d48b4..ef33979664 100644 --- a/lib/librte_eal/common/eal_options.h +++ b/lib/librte_eal/common/eal_options.h @@ -85,6 +85,8 @@ enum { OPT_TELEMETRY_NUM, #define OPT_NO_TELEMETRY "no-telemetry" OPT_NO_TELEMETRY_NUM, +#define OPT_FORCE_MAX_SIMD_BITWIDTH "force-max-simd-bitwidth" + OPT_FORCE_MAX_SIMD_BITWIDTH_NUM, OPT_LONG_MAX_NUM }; diff --git a/lib/librte_eal/include/rte_eal.h b/lib/librte_eal/include/rte_eal.h index e3c2ef185e..706d3cca5a 100644 --- a/lib/librte_eal/include/rte_eal.h +++ b/lib/librte_eal/include/rte_eal.h @@ -43,6 +43,23 @@ enum rte_proc_type_t { RTE_PROC_INVALID }; +/** + * The max SIMD bitwidth value to limit vector path selection. + */ +enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + /**< Limits path selection to scalar, disables all vector paths. */ + RTE_SIMD_128 = 128, + /**< Limits path selection to SSE/NEON/Altivec or below. */ + RTE_SIMD_256 = 256, /**< Limits path selection to AVX2 or below. */ + RTE_SIMD_512 = 512, /**< Limits path selection to AVX512 or below. */ + RTE_SIMD_MAX = INT16_MAX + 1, + /**< + * Disables limiting by max SIMD bitwidth, allows all suitable paths. + * This value is used as it is a large number and a power of 2. + */ +}; + /** * Get the process type in a multi-process setup * @@ -51,6 +68,29 @@ enum rte_proc_type_t { */ enum rte_proc_type_t rte_eal_process_type(void); +/** + * Get the supported SIMD bitwidth. + * + * @return + * uint16_t bitwidth. + */ +__rte_experimental +uint16_t rte_get_max_simd_bitwidth(void); + +/** + * Set the supported SIMD bitwidth. + * This API should only be called once at initialization, before EAL init. + * + * @param bitwidth + * uint16_t bitwidth. + * @return + * - 0 on success. + * - -EINVAL on invalid bitwidth parameter. + * - -EPERM if bitwidth is forced. + */ +__rte_experimental +int rte_set_max_simd_bitwidth(uint16_t bitwidth); + /** * Request iopl privilege for all RPL. * diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h index b0545c878c..a69aabc568 100644 --- a/lib/librte_eal/ppc/include/rte_vect.h +++ b/lib/librte_eal/ppc/include/rte_vect.h @@ -15,6 +15,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef vector signed int xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/rte_eal_exports.def b/lib/librte_eal/rte_eal_exports.def index 7b35beb702..81e99b00d9 100644 --- a/lib/librte_eal/rte_eal_exports.def +++ b/lib/librte_eal/rte_eal_exports.def @@ -26,6 +26,7 @@ EXPORTS rte_eal_tailq_register rte_eal_using_phys_addrs rte_free + rte_get_max_simd_bitwidth rte_get_tsc_hz rte_hexdump rte_intr_rx_ctl @@ -62,6 +63,7 @@ EXPORTS rte_memzone_reserve_aligned rte_memzone_reserve_bounded rte_memzone_walk + rte_set_max_simd_bitwidth rte_socket_id rte_strerror rte_strsplit diff --git a/lib/librte_eal/rte_eal_version.map b/lib/librte_eal/rte_eal_version.map index a93dea9fe6..714be49377 100644 --- a/lib/librte_eal/rte_eal_version.map +++ b/lib/librte_eal/rte_eal_version.map @@ -400,6 +400,8 @@ EXPERIMENTAL { # added in 20.11 __rte_eal_trace_generic_size_t; rte_service_lcore_may_be_active; + rte_get_max_simd_bitwidth; + rte_set_max_simd_bitwidth; }; INTERNAL { diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h index df5a607623..a00d3d5a62 100644 --- a/lib/librte_eal/x86/include/rte_vect.h +++ b/lib/librte_eal/x86/include/rte_vect.h @@ -35,6 +35,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef __m128i xmm_t; #define XMM_SIZE (sizeof(xmm_t)) From patchwork Tue Oct 13 10:38:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80455 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56015A04B7; Tue, 13 Oct 2020 12:39:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EE0121DA5D; Tue, 13 Oct 2020 12:38:31 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 579C91DA21 for ; Tue, 13 Oct 2020 12:38:29 +0200 (CEST) IronPort-SDR: ygSIdUUNiG69ucxdptZD0TEtyuzH/Pyz6675HVtaQebZqoewtarDEPUe8A4Mtzhgf6UwehddRu o+4TEh9Vkj9g== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998208" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998208" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:29 -0700 IronPort-SDR: AtM1J+sZXrF7RsujDBM3Ze3qnoQCUPt3m0A+g1+Z+4ygBDpm4K53jat223oa1MBOzKzhdtGgWV /GORgLj1fnqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442933" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:26 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Anatoly Burakov , John McNamara , Marko Kovacevic Date: Tue, 13 Oct 2020 11:38:02 +0100 Message-Id: <20201013103817.305423-3-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 02/17] doc: add detail on using max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds documentation on the usage of the max SIMD bitwidth EAL setting, and how to use it to enable AVX-512 at runtime. Cc: Anatoly Burakov Cc: John McNamara Cc: Marko Kovacevic Signed-off-by: Ciara Power --- v4: Updated docs to reflect renamed enum. v3: - Added enum value for disabling use of max SIMD to doc. - Added entry to HowTo index. --- doc/guides/howto/avx512.rst | 36 +++++++++++++++++++ doc/guides/howto/index.rst | 1 + doc/guides/linux_gsg/eal_args.include.rst | 16 +++++++++ .../prog_guide/env_abstraction_layer.rst | 32 +++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 doc/guides/howto/avx512.rst diff --git a/doc/guides/howto/avx512.rst b/doc/guides/howto/avx512.rst new file mode 100644 index 0000000000..6eb3755775 --- /dev/null +++ b/doc/guides/howto/avx512.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 Intel Corporation. + + +Using AVX-512 with DPDK +======================= + +AVX-512 is not used by default in DPDK, but it can be selected at runtime by apps through the use of EAL API, +and by the user with a commandline argument. DPDK has a setting for max SIMD bitwidth, +which can be modified and will then limit the vector path taken by the code. + + +Using the API in apps +--------------------- + +Apps can request DPDK uses AVX-512 at runtime, if it provides improved application performance. +This can be done by modifying the EAL setting for max SIMD bitwidth to 512, as by default it is 256, +which does not allow for AVX-512. + +.. code-block:: c + + rte_set_max_simd_bitwidth(RTE_SIMD_512); + +This API should only be called once at initialization, before EAL init. +For more information on the possible enum values to use as a parameter, go to :ref:`max_simd_bitwidth`: + + +Using the command-line argument +--------------------------------------------- + +The user can select to use AVX-512 at runtime, using the following argument to set the max bitwidth:: + + ./app/dpdk-testpmd --force-max-simd-bitwidth=512 + +This will override any further changes to the max SIMD bitwidth in DPDK, +which is useful for testing purposes. diff --git a/doc/guides/howto/index.rst b/doc/guides/howto/index.rst index 5a97ea508c..c2a2c60ddb 100644 --- a/doc/guides/howto/index.rst +++ b/doc/guides/howto/index.rst @@ -20,3 +20,4 @@ HowTo Guides telemetry debug_troubleshoot openwrt + avx512 diff --git a/doc/guides/linux_gsg/eal_args.include.rst b/doc/guides/linux_gsg/eal_args.include.rst index 0fe4457968..a0bfbd1a98 100644 --- a/doc/guides/linux_gsg/eal_args.include.rst +++ b/doc/guides/linux_gsg/eal_args.include.rst @@ -210,3 +210,19 @@ Other options * ``--no-telemetry``: Disable telemetry. + +* ``--force-max-simd-bitwidth=``: + + Specify the maximum SIMD bitwidth size to handle. This limits which vector paths, + if any, are taken, as any paths taken must use a bitwidth below the max bitwidth limit. + For example, to allow all SIMD bitwidths up to and including AVX-512:: + + --force-max-simd-bitwidth=512 + + The following example shows limiting the bitwidth to 64-bits to disable all vector code:: + + --force-max-simd-bitwidth=64 + + To disable use of max SIMD bitwidth limit:: + + --force-max-simd-bitwidth=0 diff --git a/doc/guides/prog_guide/env_abstraction_layer.rst b/doc/guides/prog_guide/env_abstraction_layer.rst index 936c885081..04bb910386 100644 --- a/doc/guides/prog_guide/env_abstraction_layer.rst +++ b/doc/guides/prog_guide/env_abstraction_layer.rst @@ -486,6 +486,38 @@ the desired addressing mode when virtual devices that are not directly attached To facilitate forcing the IOVA mode to a specific value the EAL command line option ``--iova-mode`` can be used to select either physical addressing('pa') or virtual addressing('va'). +.. _max_simd_bitwidth: + + +Max SIMD bitwidth +~~~~~~~~~~~~~~~~~ + +The EAL provides a single setting to limit the max SIMD bitwidth used by DPDK, +which is used in determining the vector path, if any, chosen by a component. +The value can be set at runtime by an application using the 'rte_set_max_simd_bitwidth(uint16_t bitwidth)' function, +which should only be called once at initialization, before EAL init. +The value can be overridden by the user using the EAL command-line option '--force-max-simd-bitwidth'. + +When choosing a vector path, along with checking the CPU feature support, +the value of the max SIMD bitwidth must also be checked, and can be retrieved using the 'rte_get_max_simd_bitwidth()' function. +The value should be compared against the enum values for accepted max SIMD bitwidths: + +.. code-block:: c + + enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + RTE_SIMD_128 = 128, + RTE_SIMD_256 = 256, + RTE_SIMD_512 = 512, + RTE_SIMD_MAX = UINT16_MAX, + }; + + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_512) + /* Take AVX-512 vector path */ + else if (rte_get_max_simd_bitwidth() >= RTE_SIMD_256) + /* Take AVX2 vector path */ + + Memory Segments and Memory Zones (memzone) ------------------------------------------ From patchwork Tue Oct 13 10:38:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80456 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2674DA04B7; Tue, 13 Oct 2020 12:39:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7BFE61DA82; Tue, 13 Oct 2020 12:38:34 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 177DA1DA7C for ; Tue, 13 Oct 2020 12:38:31 +0200 (CEST) IronPort-SDR: IOm9MKnEsjItsqka/WMS6AIPDPVA/sef27/ebW/7yX4AMl3ESHzpFMxlLeTz1Z+mEk6uuoSctQ I373ndUlXtnw== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998228" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998228" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:31 -0700 IronPort-SDR: F9XCCKlan85Jn7VwMjmGL4fCTIEmehtj2+FDuFSbldJE2DGZjDrpMPiGRHSh8955G40ibTARv5 X4ck6ZLtwXJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442941" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:29 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Beilei Xing , Jeff Guo Date: Tue, 13 Oct 2020 11:38:03 +0100 Message-Id: <20201013103817.305423-4-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 03/17] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Beilei Xing Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- v4: Updated enum names. --- drivers/net/i40e/i40e_rxtx.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 322fc1ed75..a6644b3efa 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -3098,7 +3098,8 @@ static eth_rx_burst_t i40e_get_latest_rx_vec(bool scatter) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) } } - if (ad->rx_vec_allowed) { + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { /* Vec Rx path */ PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.", dev->data->port_id); @@ -3268,7 +3271,8 @@ static eth_tx_burst_t i40e_get_latest_tx_vec(void) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3311,7 +3316,8 @@ i40e_set_tx_function(struct rte_eth_dev *dev) } if (ad->tx_simple_allowed) { - if (ad->tx_vec_allowed) { + if (ad->tx_vec_allowed && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); if (ad->use_latest_vec) dev->tx_pkt_burst = From patchwork Tue Oct 13 10:38:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80457 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04640A04B7; Tue, 13 Oct 2020 12:39:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 139381DAA4; Tue, 13 Oct 2020 12:38:36 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 0076F1DA92 for ; Tue, 13 Oct 2020 12:38:34 +0200 (CEST) IronPort-SDR: b/5CqZN1RbLHwkb3CMyuJzvib397U2R3xKTo8XZ+FsiEBDoLJfwkaGn1U2QFZVuYnyBjaz5U1Z mnrQJ7jhTIiA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998242" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998242" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:34 -0700 IronPort-SDR: W3tnYpp/LHOyDZVB60BMPcIuJq3kzcTnzXYaqnTb6AFYY+iQu7Ys7l/2qU5tZirBEkdwroo/eo s0KklmT6dIeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442961" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:32 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Somalapuram Amaranath Date: Tue, 13 Oct 2020 11:38:04 +0100 Message-Id: <20201013103817.305423-5-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 04/17] net/axgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Somalapuram Amaranath Signed-off-by: Ciara Power Acked-by: Amaranath Somalapuram --- v4: Updated enum name. --- drivers/net/axgbe/axgbe_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index bc93becaa5..5386bd86f8 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -557,7 +557,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (!pdata->tx_queues) pdata->tx_queues = dev->data->tx_queues; - if (txq->vector_disable) + if (txq->vector_disable || rte_get_max_simd_bitwidth() + < RTE_SIMD_128) dev->tx_pkt_burst = &axgbe_xmit_pkts; else #ifdef RTE_ARCH_X86 From patchwork Tue Oct 13 10:38:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80458 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0099A04B7; Tue, 13 Oct 2020 12:40:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8D7C91DAB9; Tue, 13 Oct 2020 12:38:38 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 1F95C1DAB4 for ; Tue, 13 Oct 2020 12:38:36 +0200 (CEST) IronPort-SDR: 7X8uNU6GreN0VAoIqsbHIYgqixJZE9cCT4Y7J50zp1hGfFjmWYbZti42SFPU2zfSIHWD27kOP6 4FDezOppJngQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998261" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998261" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:36 -0700 IronPort-SDR: V2LRmknnFE2aPWqlbbH6+HC1nuA05BdbHdUtksBVTCGKc0XCvVM+4RzpWY15/0shaLoUfVYvCb 7Mm0WqEMts+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442969" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:34 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Ajit Khaparde , Somnath Kotur Date: Tue, 13 Oct 2020 11:38:05 +0100 Message-Id: <20201013103817.305423-6-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 05/17] net/bnxt: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Ajit Khaparde Cc: Somnath Kotur Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/bnxt/bnxt_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 8b63134c39..07d1a1a6ab 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1169,7 +1169,8 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_VLAN_FILTER)) && - !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) { + !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", eth_dev->data->port_id); bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -1202,7 +1203,8 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) */ if (!eth_dev->data->scattered_rx && !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && - !BNXT_TRUFLOW_EN(bp)) { + !BNXT_TRUFLOW_EN(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", eth_dev->data->port_id); return bnxt_xmit_pkts_vec; From patchwork Tue Oct 13 10:38:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80459 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16422A04B7; Tue, 13 Oct 2020 12:40:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 18F481DAC1; Tue, 13 Oct 2020 12:38:43 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id AEB741DABF for ; Tue, 13 Oct 2020 12:38:39 +0200 (CEST) IronPort-SDR: XN65iYRFn+dtgrSR4f9pqz/WhANKgpK+oMjq5FPBYi17bO57z5Hg+SWYY6C+YVEXskSwttakSD 2DO7kJiWHzTg== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998278" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998278" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:39 -0700 IronPort-SDR: zqdbrVZCoupNpjAmNAMWw7Bz8kYAD25dEwE7E0qbHK3E44VbDlKV6lwodwiGU+56L3ueJ2ygUk ElOOAVNrEYbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463442991" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:37 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , John Daley , Hyong Youb Kim Date: Tue, 13 Oct 2020 11:38:06 +0100 Message-Id: <20201013103817.305423-7-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 06/17] net/enic: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: John Daley Cc: Hyong Youb Kim Acked-by: Hyong Youb Kim Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c b/drivers/net/enic/enic_rxtx_vec_avx2.c index 676b9f5fdb..75e9172177 100644 --- a/drivers/net/enic/enic_rxtx_vec_avx2.c +++ b/drivers/net/enic/enic_rxtx_vec_avx2.c @@ -821,7 +821,8 @@ enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev) fconf = ð_dev->data->dev_conf.fdir_conf; if (fconf->mode != RTE_FDIR_MODE_NONE) return false; - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) { ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx handler"); eth_dev->rx_pkt_burst = &enic_noscatter_vec_recv_pkts; enic->use_noscatter_vec_rx_handler = 1; From patchwork Tue Oct 13 10:38:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80460 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24681A04B7; Tue, 13 Oct 2020 12:40:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9DA661DAC8; Tue, 13 Oct 2020 12:38:46 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 9B1BB1DAC0 for ; Tue, 13 Oct 2020 12:38:42 +0200 (CEST) IronPort-SDR: IDP0fvGnC6Iw6aQ2vpD35d3AcOlsIuPCCnl+0D0B1fvY9f3WVM22VZABb7u7ENIXx3r2qmONnR 6IaaWzE7e/1A== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998299" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998299" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:42 -0700 IronPort-SDR: jjnfXJmYQCRboRXqB1yYqT5z6RT245l4dy9Sqnq7m4XT1w+Qblw73UtY9R90uDns6izpVyPXGJ gmPPNqaWdjyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443008" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:39 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Qi Zhang , Xiao Wang Date: Tue, 13 Oct 2020 11:38:07 +0100 Message-Id: <20201013103817.305423-8-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 07/17] net/fm10k: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qi Zhang Cc: Xiao Wang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- v4: Updated enum name. --- drivers/net/fm10k/fm10k_ethdev.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index c4a6fdf7f0..78c81bf35b 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -2937,7 +2937,9 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) { /* primary process has set the ftag flag and offloads */ txq = dev->data->tx_queues[0]; - if (fm10k_tx_vec_condition_check(txq)) { + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() + < RTE_SIMD_128) { dev->tx_pkt_burst = fm10k_xmit_pkts; dev->tx_pkt_prepare = fm10k_prep_pkts; PMD_INIT_LOG(DEBUG, "Use regular Tx func"); @@ -2956,7 +2958,8 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) txq = dev->data->tx_queues[i]; txq->tx_ftag_en = tx_ftag_en; /* Check if Vector Tx is satisfied */ - if (fm10k_tx_vec_condition_check(txq)) + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) use_sse = 0; } @@ -2990,7 +2993,9 @@ fm10k_set_rx_function(struct rte_eth_dev *dev) * conditions to be met. */ if (!fm10k_rx_vec_condition_check(dev) && - dev_info->rx_vec_allowed && !rx_ftag_en) { + dev_info->rx_vec_allowed && !rx_ftag_en && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { if (dev->data->scattered_rx) dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec; else From patchwork Tue Oct 13 10:38:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80461 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C85CBA04B7; Tue, 13 Oct 2020 12:41:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 344DA1DACD; Tue, 13 Oct 2020 12:38:48 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 19F631DAC7 for ; Tue, 13 Oct 2020 12:38:44 +0200 (CEST) IronPort-SDR: 0c57BvOxXbl4KfoNS0IpcWP6ml5rinXhuoDjMag60vbmlMeuuI20GLYKgE1fL3AI0rZR+vlZn3 mi5MKjy8lFYQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998319" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998319" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:44 -0700 IronPort-SDR: 1u6ygWUQpKDIlPPOo977nrfFnH0Kxqz3TqUZ4pAqM+8i2s6UsWsKUo/TDSLRL5WW8boGoWDKwt QE0P++8ach0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443017" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:42 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Jingjing Wu , Beilei Xing Date: Tue, 13 Oct 2020 11:38:08 +0100 Message-Id: <20201013103817.305423-9-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 08/17] net/iavf: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Jingjing Wu Cc: Beilei Xing Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/iavf/iavf_rxtx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 1b0efe0433..7c27d5beec 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -2104,14 +2104,16 @@ iavf_set_rx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_rx_vec_dev_check(dev)) { + if (!iavf_rx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; (void)iavf_rxq_vec_setup(rxq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; if (dev->data->scattered_rx) { @@ -2177,7 +2179,8 @@ iavf_set_tx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_tx_vec_dev_check(dev)) { + if (!iavf_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; if (!txq) @@ -2185,8 +2188,9 @@ iavf_set_tx_function(struct rte_eth_dev *dev) iavf_txq_vec_setup(txq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", From patchwork Tue Oct 13 10:38:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80462 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46D13A04B7; Tue, 13 Oct 2020 12:41:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CBEE1DADC; Tue, 13 Oct 2020 12:38:51 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id A45F31DAD1 for ; Tue, 13 Oct 2020 12:38:47 +0200 (CEST) IronPort-SDR: BlgFGhu9zM6DfOtvtXrKey1xHJMg5l2wQMtrETCCQ0iFrGkINRy6mLP3tG4Z+a/J+XGcUYRg7C JG2Ui9EtmSrA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998339" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998339" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:47 -0700 IronPort-SDR: iCXSoiIb0/JT3W1DYF4hPHIjnHDDodfmFE9A6dGpGwirQLrpHzsEtK9aRtHW4K0faXWYQlM+ia SWZyly4pytrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443033" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:45 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Qiming Yang , Qi Zhang Date: Tue, 13 Oct 2020 11:38:09 +0100 Message-Id: <20201013103817.305423-10-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 09/17] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 93a0ac6918..0003ce2afe 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2989,7 +2989,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2999,8 +3001,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { @@ -3167,7 +3171,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3177,8 +3183,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { From patchwork Tue Oct 13 10:38:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80463 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E5C5A04B7; Tue, 13 Oct 2020 12:42:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AFEC11DAE3; Tue, 13 Oct 2020 12:38:52 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 9025D1DADA for ; Tue, 13 Oct 2020 12:38:50 +0200 (CEST) IronPort-SDR: 8qYQjJ1Fdjr5yvT+vPBx0Y5wMKwpO2GFt5/LBj9ymS7fte/IkVFJGpJJSnBaS+jhwXGMYhoPbI HM8tUgo1SlXg== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998358" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998358" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:50 -0700 IronPort-SDR: n+s0eBuw806EhBxKiVr6Y1hCSr+I76EEQgRJMv9EmtWK7rLFdtQ/h/mdhvcZVvMpfkpCDs3j8V uiBsfo27PAFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443059" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:47 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Wei Zhao , Jeff Guo , Haiyue Wang Date: Tue, 13 Oct 2020 11:38:10 +0100 Message-Id: <20201013103817.305423-11-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 10/17] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Wei Zhao Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- v4: - Updated enum name. - Moved placement of condition check. - Added condition check to tx cleanup path selection. --- drivers/net/ixgbe/ixgbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 977ecf5137..d371647c0e 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2404,6 +2404,7 @@ ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) #endif txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) { if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || txq->sw_ring_v != NULL)) { return ixgbe_tx_done_cleanup_vec(txq, free_cnt); @@ -2502,6 +2503,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq) PMD_INIT_LOG(DEBUG, "Using simple tx code path"); dev->tx_pkt_prepare = NULL; if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || ixgbe_txq_vec_setup(txq) == 0)) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); @@ -4743,7 +4745,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) * conditions to be met and Rx Bulk Allocation should be allowed. */ if (ixgbe_rx_vec_dev_conf_condition_check(dev) || - !adapter->rx_bulk_alloc_allowed) { + !adapter->rx_bulk_alloc_allowed || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " "preconditions", dev->data->port_id); From patchwork Tue Oct 13 10:38:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80464 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8E4EA04B7; Tue, 13 Oct 2020 12:42:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 396561DAE7; Tue, 13 Oct 2020 12:38:56 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id D20891DAE7 for ; Tue, 13 Oct 2020 12:38:53 +0200 (CEST) IronPort-SDR: bT1IXJFc1ZU523yqoVN8h02iz+TUdmkYXAYHF0MaNF2E+iUcAi+HRg22CJIXog6fhXS6L6RV51 R6D88BmO9iMQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998378" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998378" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:53 -0700 IronPort-SDR: ZgfxvTL2bPRlA2kmvJ14do8of+R4hJoXa3BDMgWVkkwM7U0kCgdAV+Imip+0iERRn76SMOgKVd FnsW/PS7h6ow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443077" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:50 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko , Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler Date: Tue, 13 Oct 2020 11:38:11 +0100 Message-Id: <20201013103817.305423-12-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 11/17] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power Acked-by: Viacheslav Ovsiienko --- v4: Updated enum name. v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..49f1b61ff8 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) From patchwork Tue Oct 13 10:38:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80465 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 760E1A04B7; Tue, 13 Oct 2020 12:42:50 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E81E61DAEE; Tue, 13 Oct 2020 12:38:59 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id C4F2E1DAED for ; Tue, 13 Oct 2020 12:38:56 +0200 (CEST) IronPort-SDR: XTJiU0hQ2zfqWgwzC6a/n8vCwUMIKtJFJjnlgQKCZs0YZDtXc+TzqdMRL5oWc9vPAOMvVW1kQ2 7kt+J6y9pC+w== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998398" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998398" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:56 -0700 IronPort-SDR: 9iywd3dYB4p7962F9rV6as5lpDDJcVAQ2DOLD83MmW9WDMPfCYOCQALrP6DE4joeshzrH1kO88 4jt6A/XHiPOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443088" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:53 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Maxime Coquelin , Chenbo Xia , Zhihong Wang Date: Tue, 13 Oct 2020 11:38:12 +0100 Message-Id: <20201013103817.305423-13-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 12/17] net/virtio: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Maxime Coquelin Cc: Chenbo Xia Cc: Zhihong Wang Signed-off-by: Ciara Power --- v4: Updated enum name. v3: Moved max SIMD bitwidth check to configure function with other vec support checks. --- drivers/net/virtio/virtio_ethdev.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c index 0236c756dc..70955e5cc0 100644 --- a/drivers/net/virtio/virtio_ethdev.c +++ b/drivers/net/virtio/virtio_ethdev.c @@ -2313,7 +2313,8 @@ virtio_dev_configure(struct rte_eth_dev *dev) if ((hw->use_vec_rx || hw->use_vec_tx) && (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) || !vtpci_with_feature(hw, VIRTIO_F_IN_ORDER) || - !vtpci_with_feature(hw, VIRTIO_F_VERSION_1))) { + !vtpci_with_feature(hw, VIRTIO_F_VERSION_1) || + rte_get_max_simd_bitwidth() < RTE_SIMD_512)) { PMD_DRV_LOG(INFO, "disabled packed ring vectorized path for requirements not met"); hw->use_vec_rx = 0; @@ -2366,6 +2367,12 @@ virtio_dev_configure(struct rte_eth_dev *dev) "disabled split ring vectorized rx for offloading enabled"); hw->use_vec_rx = 0; } + + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) { + PMD_DRV_LOG(INFO, + "disabled split ring vectorized rx, max SIMD bitwidth too low"); + hw->use_vec_rx = 0; + } } } From patchwork Tue Oct 13 10:38:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80466 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5E08CA04B7; Tue, 13 Oct 2020 12:43:11 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5D3861DAF1; Tue, 13 Oct 2020 12:39:02 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 45E501DAED for ; Tue, 13 Oct 2020 12:38:59 +0200 (CEST) IronPort-SDR: QX+ttVbKct4044/7BD4rXc9z0Qoad+1Z/Wbe5Cc2zEocNVXgtJejVctE42XXm/4G6hNY5navbe uItMk7pz8Hcw== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998414" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998414" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:59 -0700 IronPort-SDR: r3f4dH6LNtoOy8B1pTRrCTi0DNrYs/s4x2vajQbcy8jK/F8Vwl4eDFitYUR19snFcB/Jjaa4rq hdggFqfgXaww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443107" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:56 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , David Hunt Date: Tue, 13 Oct 2020 11:38:13 +0100 Message-Id: <20201013103817.305423-14-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 13/17] distributor: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: David Hunt Signed-off-by: Ciara Power Acked-by: David Hunt --- v4: Updated enum name. --- lib/librte_distributor/rte_distributor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c index 1c047f065a..05e61dddfc 100644 --- a/lib/librte_distributor/rte_distributor.c +++ b/lib/librte_distributor/rte_distributor.c @@ -636,7 +636,8 @@ rte_distributor_create(const char *name, d->dist_match_fn = RTE_DIST_MATCH_SCALAR; #if defined(RTE_ARCH_X86) - d->dist_match_fn = RTE_DIST_MATCH_VECTOR; + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + d->dist_match_fn = RTE_DIST_MATCH_VECTOR; #endif /* From patchwork Tue Oct 13 10:38:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80467 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 044DFA04B7; Tue, 13 Oct 2020 12:43:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1317F1DAF8; Tue, 13 Oct 2020 12:39:06 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id D8E621DAF1 for ; Tue, 13 Oct 2020 12:39:01 +0200 (CEST) IronPort-SDR: RqBD3q3PknAKhZ4k5gjr0mLvM9T12Dn0i6903jkGCzqrZEFtMuKzAzuDgRVCbyCtJ/ncSnCD8q pNlUqVRW1Y0Q== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998427" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998427" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:39:01 -0700 IronPort-SDR: q/opQFyy+SZppp/tdG10hCxOMlDsfC5kudOELNWg6qtdJb3nxBrjz+KVnKauIlpncL8tODWkpq rmvLLCeKww5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443137" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:59 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Yipeng Wang , Sameh Gobriel Date: Tue, 13 Oct 2020 11:38:14 +0100 Message-Id: <20201013103817.305423-15-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 14/17] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Yipeng Wang Cc: Sameh Gobriel Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_member/rte_member_ht.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_member/rte_member_ht.c b/lib/librte_member/rte_member_ht.c index 3ea293a094..98c8aac248 100644 --- a/lib/librte_member/rte_member_ht.c +++ b/lib/librte_member/rte_member_ht.c @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum *ss, } #if defined(RTE_ARCH_X86) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && - RTE_MEMBER_BUCKET_ENTRIES == 16) + RTE_MEMBER_BUCKET_ENTRIES == 16 && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) ss->sig_cmp_fn = RTE_MEMBER_COMPARE_AVX2; else #endif From patchwork Tue Oct 13 10:38:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80468 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 595B6A04B7; Tue, 13 Oct 2020 12:43:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9E0171DAFD; Tue, 13 Oct 2020 12:39:07 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 781B81DAD5 for ; Tue, 13 Oct 2020 12:39:04 +0200 (CEST) IronPort-SDR: K1Vb9K0BTkk4YwqBaGLcnSEFXLD78UUeOLmmJKdvQ2ajzkLIZpPCozUZqXQV48MpX3mlIXZfx/ AA6lHfE35g4A== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998429" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998429" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:39:04 -0700 IronPort-SDR: Dsxdqi9igJg8H8aRf2WNNk9bPdV05k9yOqtN5LEey8t5xkdqaYNRU9CZzFaOb6jS8HcKKJKWVz ZSP29Jzddm7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443154" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:39:01 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Byron Marohn , Yipeng Wang Date: Tue, 13 Oct 2020 11:38:15 +0100 Message-Id: <20201013103817.305423-16-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 15/17] efd: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Byron Marohn Cc: Yipeng Wang Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_efd/rte_efd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/librte_efd/rte_efd.c b/lib/librte_efd/rte_efd.c index 6a799556d4..e925b73a9c 100644 --- a/lib/librte_efd/rte_efd.c +++ b/lib/librte_efd/rte_efd.c @@ -645,7 +645,9 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * For less than 4 bits, scalar function performs better * than vectorised version */ - if (RTE_EFD_VALUE_NUM_BITS > 3 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (RTE_EFD_VALUE_NUM_BITS > 3 + && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) + && rte_get_max_simd_bitwidth() >= RTE_SIMD_256) table->lookup_fn = EFD_LOOKUP_AVX2; else #endif @@ -655,7 +657,8 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * than vectorised version */ if (RTE_EFD_VALUE_NUM_BITS > 16 && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) table->lookup_fn = EFD_LOOKUP_NEON; else #endif From patchwork Tue Oct 13 10:38:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80469 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC88FA04B7; Tue, 13 Oct 2020 12:44:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E655C1DB03; Tue, 13 Oct 2020 12:39:10 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 1F1A31DB02 for ; Tue, 13 Oct 2020 12:39:08 +0200 (CEST) IronPort-SDR: E9hDNmJKs2yY9Fi76QJugR3M5/dHjsnD0GJBY5Rfb18jFjkDcAjM/I9pCtOw6V2PrlG3V3YLm8 6qSBW8uDmRnQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998432" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998432" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:39:07 -0700 IronPort-SDR: YsrXsWm9c2voXrfH9NUH6qjvO3//Gm8H0B4M/fy0fHQgOR+ltow96lwq6Q9L9nXC2e162S80o3 O1mbEO9TTDOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443165" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:39:04 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Jasvinder Singh , Olivier Matz Date: Tue, 13 Oct 2020 11:38:16 +0100 Message-Id: <20201013103817.305423-17-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 16/17] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. The vector path was initially chosen in RTE_INIT, however this is no longer suitable as we cannot check the max SIMD bitwidth at that time. Default handlers are now chosen in RTE_INIT, these default handlers are used the first time the crc calc is called, and they set the suitable handlers to be used going forward. Suggested-by: Jasvinder Singh Suggested-by: Olivier Matz Signed-off-by: Ciara Power --- v4: - Added default handlers to be set at RTE_INIT time, rather than choosing scalar handlers. - Modified logging. - Updated enum name. v3: - Moved choosing vector paths out of RTE_INIT. - Moved checking max_simd_bitwidth into the set_alg function. --- lib/librte_net/rte_net_crc.c | 75 ++++++++++++++++++++++++++++++------ lib/librte_net/rte_net_crc.h | 8 ++++ 2 files changed, 72 insertions(+), 11 deletions(-) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 4f5b9e8286..11d0161a32 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -9,6 +9,7 @@ #include #include #include +#include #if defined(RTE_ARCH_X86_64) && defined(__PCLMUL__) #define X86_64_SSE42_PCLMULQDQ 1 @@ -32,6 +33,12 @@ static uint32_t crc32_eth_lut[CRC_LUT_SIZE]; static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE]; +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len); + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len); + static uint32_t rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len); @@ -41,7 +48,12 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len); typedef uint32_t (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len); -static rte_net_crc_handler *handlers; +static rte_net_crc_handler handlers_default[] = { + [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler, + [RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler, +}; + +static rte_net_crc_handler *handlers = handlers_default; static rte_net_crc_handler handlers_scalar[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler, @@ -60,6 +72,9 @@ static rte_net_crc_handler handlers_neon[] = { }; #endif +static uint16_t max_simd_bitwidth; +RTE_LOG_REGISTER(libnet_logtype, lib.net, INFO); + /** * Reflect the bits about the middle * @@ -112,6 +127,42 @@ crc32_eth_calc_lut(const uint8_t *data, return crc; } +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len) +{ + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + handlers = handlers_scalar; +#ifdef X86_64_SSE42_PCLMULQDQ + if (max_simd_bitwidth >= RTE_SIMD_128) + handlers = handlers_sse42; +#endif +#ifdef ARM64_NEON_PMULL + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL) && + max_simd_bitwidth >= RTE_SIMD_128) { + handlers = handlers_neon; +#endif + return handlers[RTE_NET_CRC16_CCITT](data, data_len); +} + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len) +{ + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + handlers = handlers_scalar; +#ifdef X86_64_SSE42_PCLMULQDQ + if (max_simd_bitwidth >= RTE_SIMD_128) + handlers = handlers_sse42; +#endif +#ifdef ARM64_NEON_PMULL + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL) && + max_simd_bitwidth >= RTE_SIMD_128) { + handlers = handlers_neon; +#endif + return handlers[RTE_NET_CRC32_ETH](data, data_len); +} + static void rte_net_crc_scalar_init(void) { @@ -145,18 +196,26 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len) void rte_net_crc_set_alg(enum rte_net_crc_alg alg) { + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + switch (alg) { #ifdef X86_64_SSE42_PCLMULQDQ case RTE_NET_CRC_SSE42: - handlers = handlers_sse42; - break; + if (max_simd_bitwidth >= RTE_SIMD_128) { + handlers = handlers_sse42; + return; + } + NET_LOG(INFO, "Max SIMD Bitwidth too low, can't use SSE\n"); #elif defined ARM64_NEON_PMULL /* fall-through */ case RTE_NET_CRC_NEON: - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL) && + max_simd_bitwidth >= RTE_SIMD_128) { handlers = handlers_neon; - break; + return; } + NET_LOG(INFO, "Max SIMD Bitwidth too low or CPU flag not enabled, can't use NEON\n"); #endif /* fall-through */ case RTE_NET_CRC_SCALAR: @@ -184,19 +243,13 @@ rte_net_crc_calc(const void *data, /* Select highest available crc algorithm as default one */ RTE_INIT(rte_net_crc_init) { - enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR; - rte_net_crc_scalar_init(); #ifdef X86_64_SSE42_PCLMULQDQ - alg = RTE_NET_CRC_SSE42; rte_net_crc_sse42_init(); #elif defined ARM64_NEON_PMULL if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { - alg = RTE_NET_CRC_NEON; rte_net_crc_neon_init(); } #endif - - rte_net_crc_set_alg(alg); } diff --git a/lib/librte_net/rte_net_crc.h b/lib/librte_net/rte_net_crc.h index 16e85ca970..c942865ecf 100644 --- a/lib/librte_net/rte_net_crc.h +++ b/lib/librte_net/rte_net_crc.h @@ -7,6 +7,8 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -25,6 +27,12 @@ enum rte_net_crc_alg { RTE_NET_CRC_NEON, }; +extern int libnet_logtype; + +#define NET_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, libnet_logtype, "%s(): " fmt "\n", \ + __func__, ## args) + /** * This API set the CRC computation algorithm (i.e. scalar version, * x86 64-bit sse4.2 intrinsic version, etc.) and internal data From patchwork Tue Oct 13 10:38:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80470 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9DA6A04B7; Tue, 13 Oct 2020 12:44:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9C0851DB08; Tue, 13 Oct 2020 12:39:12 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 602C01DB02 for ; Tue, 13 Oct 2020 12:39:10 +0200 (CEST) IronPort-SDR: aUPkxuJji/n91+4PZ5FmqZwC5yOmPEGKsfTXgNUQdH+ZXfLb13c0zlWrA/qwezF1kKUicMoEI9 4QYqmwCBqJvA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998435" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998435" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:39:10 -0700 IronPort-SDR: QKsAsjUgOtAjiq2tANM7CR00lN/dhRLnlj2YqgPleiJRqm0I+y2+50sP44jgixA2MjxNWYOWRV ZjSJSsxmzYXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443180" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:39:07 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Nithin Dabilpuram , Pavan Nikhilesh , Kiran Kumar K Date: Tue, 13 Oct 2020 11:38:17 +0100 Message-Id: <20201013103817.305423-18-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 17/17] node: choose vector path at runtime X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing the vector path, max SIMD bitwidth is now checked to ensure the vector path is suitable. To do this, rather than the scalar/vector lookup functions being called directly from the apps, a generic function is called which will then call the scalar or vector lookup function. Cc: Nithin Dabilpuram Cc: Pavan Nikhilesh Cc: Jerin Jacob Cc: Kiran Kumar K Signed-off-by: Ciara Power --- lib/librte_node/ip4_lookup.c | 13 +++++++++++-- lib/librte_node/ip4_lookup_neon.h | 2 +- lib/librte_node/ip4_lookup_sse.h | 2 +- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/lib/librte_node/ip4_lookup.c b/lib/librte_node/ip4_lookup.c index 293c77f39e..b3edbc1f4d 100644 --- a/lib/librte_node/ip4_lookup.c +++ b/lib/librte_node/ip4_lookup.c @@ -34,10 +34,10 @@ static struct ip4_lookup_node_main ip4_lookup_nm; #include "ip4_lookup_neon.h" #elif defined(RTE_ARCH_X86) #include "ip4_lookup_sse.h" -#else +#endif static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_scalar(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_ipv4_hdr *ipv4_hdr; @@ -109,7 +109,16 @@ ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, return nb_objs; } +static uint16_t +ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, + void **objs, uint16_t nb_objs) +{ +#if defined(RTE_MACHINE_CPUFLAG_NEON) || defined(RTE_ARCH_X86) + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + return ip4_lookup_node_process_vec(graph, node, objs, nb_objs); #endif + return ip4_lookup_node_process_scalar(graph, node, objs, nb_objs); +} int rte_node_ip4_route_add(uint32_t ip, uint8_t depth, uint16_t next_hop, diff --git a/lib/librte_node/ip4_lookup_neon.h b/lib/librte_node/ip4_lookup_neon.h index 5e5a7d87be..0ad2763b82 100644 --- a/lib/librte_node/ip4_lookup_neon.h +++ b/lib/librte_node/ip4_lookup_neon.h @@ -7,7 +7,7 @@ /* ARM64 NEON */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts; diff --git a/lib/librte_node/ip4_lookup_sse.h b/lib/librte_node/ip4_lookup_sse.h index a071cc5919..264c986071 100644 --- a/lib/librte_node/ip4_lookup_sse.h +++ b/lib/librte_node/ip4_lookup_sse.h @@ -7,7 +7,7 @@ /* X86 SSE */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts;