From patchwork Mon Oct 12 10:19:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omkar Maslekar X-Patchwork-Id: 80392 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 259A7A04B6; Mon, 12 Oct 2020 19:23:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 439E61D97E; Mon, 12 Oct 2020 19:23:09 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id E47681D954 for ; Mon, 12 Oct 2020 19:23:04 +0200 (CEST) IronPort-SDR: zILVjRLUYBRwYPGwbJzVlRLfrf4XssJPNTwCLaYsjSxdRcFRMMuVPga6ovGR54HtH953jA64dc ppaNB4Ra178Q== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="152704666" X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="152704666" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 10:23:04 -0700 IronPort-SDR: tK1Y+iAnoifx2Pl2zcE1J/dUJyRfvNorAG5RGwwh5ggXiio59DdTivUPzXkKlV8/G8jex5M/e8 4//txS5hJxcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="299349973" Received: from unknown (HELO localhost.ch.intel.com) ([143.182.137.102]) by fmsmga008.fm.intel.com with ESMTP; 12 Oct 2020 10:23:02 -0700 From: Omkar Maslekar To: dev@dpdk.org Cc: bruce.richardson@intel.com, ciara.loftus@intel.com, omkar.maslekar@intel.com, drc@linux.vnet.ibm.com, jerinj@marvell.com, ruifeng.wang@arm.com, honnappa.nagarahalli@arm.com Date: Mon, 12 Oct 2020 03:19:40 -0700 Message-Id: <1602497980-20680-2-git-send-email-omkar.maslekar@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1602497980-20680-1-git-send-email-omkar.maslekar@intel.com> References: <1599700614-22809-1-git-send-email-omkar.maslekar@intel.com> <1602497980-20680-1-git-send-email-omkar.maslekar@intel.com> Subject: [dpdk-dev] [PATCH v6] eal: add cache-line demote support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" rte_cldemote is similar to a prefetch hint - in reverse. cldemote(addr) enables software to hint to hardware that line is likely to be shared. Useful in core-to-core communications where cache-line is likely to be shared. ARM and PPC implementation is provided with NOP and can be added if any equivalent instructions could be used for implementation on those architectures. Signed-off-by: Omkar Maslekar Acked-by: Bruce Richardson Acked-by: David Christensen --- v6: marked rte_cldemote as experimental added rte_cldemote call in existing app/test_prefetch.c v5: documentation updated fixed formatting issue in release notes added Acked-by: Bruce Richardson * v4: updated bold text for title and fixed margin in release notes * v3: fixed warning regarding whitespace * v2: documentation updated --- --- app/test/test_prefetch.c | 4 ++++ doc/guides/rel_notes/release_20_11.rst | 7 +++++++ lib/librte_eal/arm/include/rte_prefetch_32.h | 8 ++++++++ lib/librte_eal/arm/include/rte_prefetch_64.h | 8 ++++++++ lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ lib/librte_eal/ppc/include/rte_prefetch.h | 8 ++++++++ lib/librte_eal/x86/include/rte_prefetch.h | 12 ++++++++++++ 7 files changed, 63 insertions(+) diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c index 41f219a..5c58d0c 100644 --- a/app/test/test_prefetch.c +++ b/app/test/test_prefetch.c @@ -26,7 +26,11 @@ rte_prefetch1(&a); rte_prefetch2(&a); +/* test for marking a line as shared to test cldemote functionality */ + rte_cldemote(&a); + return 0; } + REGISTER_TEST_COMMAND(prefetch_autotest, test_prefetch); diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index df227a1..dc402ab 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -55,6 +55,13 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Added new function rte_cldemote in rte_prefetch.h.** + + Added a hardware hint CLDEMOTE, which is similar to prefetch in reverse. + CLDEMOTE moves the cache line to the more remote cache, where it expects + sharing to be efficient. Moving the cache line to a level more distant from + the processor helps to accelerate core-to-core communication. + Removed Items ------------- diff --git a/lib/librte_eal/arm/include/rte_prefetch_32.h b/lib/librte_eal/arm/include/rte_prefetch_32.h index e53420a..062ed27 100644 --- a/lib/librte_eal/arm/include/rte_prefetch_32.h +++ b/lib/librte_eal/arm/include/rte_prefetch_32.h @@ -10,6 +10,7 @@ #endif #include +#include #include "generic/rte_prefetch.h" static inline void rte_prefetch0(const volatile void *p) @@ -33,6 +34,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) rte_prefetch0(p); } +static inline void +__rte_experimental +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/arm/include/rte_prefetch_64.h b/lib/librte_eal/arm/include/rte_prefetch_64.h index fc2b391..6e5ee07 100644 --- a/lib/librte_eal/arm/include/rte_prefetch_64.h +++ b/lib/librte_eal/arm/include/rte_prefetch_64.h @@ -10,6 +10,7 @@ #endif #include +#include #include "generic/rte_prefetch.h" static inline void rte_prefetch0(const volatile void *p) @@ -32,6 +33,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) asm volatile ("PRFM PLDL1STRM, [%0]" : : "r" (p)); } +static inline void +__rte_experimental +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h index 6e47bdf..3474548 100644 --- a/lib/librte_eal/include/generic/rte_prefetch.h +++ b/lib/librte_eal/include/generic/rte_prefetch.h @@ -51,4 +51,20 @@ */ static inline void rte_prefetch_non_temporal(const volatile void *p); +/** + * Demote a cache line to a more distant level of cache from the processor. + * + * CLDEMOTE hints to hardware to move (demote) a cache line from the closest to + * the processor to a level more distant from the processor. It is a hint and + * not guarantee. rte_cldemote is intended to move the cache line to the more + * remote cache, where it expects sharing to be efficient and to indicate that a + * line may be accessed by a different core in the future. + * + * @param p + * Address to demote + */ +static inline void +__rte_experimental +rte_cldemote(const volatile void *p); + #endif /* _RTE_PREFETCH_H_ */ diff --git a/lib/librte_eal/ppc/include/rte_prefetch.h b/lib/librte_eal/ppc/include/rte_prefetch.h index 9ba07c8..9630227 100644 --- a/lib/librte_eal/ppc/include/rte_prefetch.h +++ b/lib/librte_eal/ppc/include/rte_prefetch.h @@ -11,6 +11,7 @@ #endif #include +#include #include "generic/rte_prefetch.h" static inline void rte_prefetch0(const volatile void *p) @@ -34,6 +35,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) rte_prefetch0(p); } +static inline void +__rte_experimental +rte_cldemote(const volatile void *p) +{ + RTE_SET_USED(p); +} + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/x86/include/rte_prefetch.h b/lib/librte_eal/x86/include/rte_prefetch.h index 384c6b3..e1e120e 100644 --- a/lib/librte_eal/x86/include/rte_prefetch.h +++ b/lib/librte_eal/x86/include/rte_prefetch.h @@ -10,6 +10,7 @@ #endif #include +#include #include "generic/rte_prefetch.h" static inline void rte_prefetch0(const volatile void *p) @@ -32,6 +33,17 @@ static inline void rte_prefetch_non_temporal(const volatile void *p) asm volatile ("prefetchnta %[p]" : : [p] "m" (*(const volatile char *)p)); } +/* + * we're using raw byte codes for now as only the newest compiler + * versions support this instruction natively. + */ +static inline void +__rte_experimental +rte_cldemote(const volatile void *p) +{ + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (p)); +} + #ifdef __cplusplus } #endif