From patchwork Tue Sep 8 09:50:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 76905 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16AF6A04AA; Tue, 8 Sep 2020 11:54:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 33B681BF8A; Tue, 8 Sep 2020 11:54:13 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id AC9D61BEE1 for ; Tue, 8 Sep 2020 11:54:11 +0200 (CEST) IronPort-SDR: H7jsKuavcuBQG++nRFjBy3WSttEw31H2Qgubi8vQlAl8d+t1ceEYMMdEq+bI7S7eNp2YZCYfpx VlMIxlM0piQw== X-IronPort-AV: E=McAfee;i="6000,8403,9737"; a="219662245" X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="219662245" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2020 02:54:10 -0700 IronPort-SDR: OgUiGIqydmM2lkuW1qa7U3bbdz8Dgbys75LQWMkIEvgSQp0EVhPAHPvDJfY8mKDgdjqd+IJxtn d3CmC+grGEdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="317136350" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by orsmga002.jf.intel.com with ESMTP; 08 Sep 2020 02:54:09 -0700 From: alvinx.zhang@intel.com To: jia.guo@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Tue, 8 Sep 2020 17:50:13 +0800 Message-Id: <20200908095015.23708-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 1/3] common/iavf: add GTPC support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang Add GTPC header and its field selector. Signed-off-by: Alvin Zhang --- drivers/common/iavf/virtchnl.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 79515ee..0042cc0 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -852,6 +852,7 @@ enum virtchnl_proto_hdr_type { VIRTCHNL_PROTO_HDR_ESP, VIRTCHNL_PROTO_HDR_AH, VIRTCHNL_PROTO_HDR_PFCP, + VIRTCHNL_PROTO_HDR_GTPC, }; /* Protocol header field within a protocol header. */ @@ -916,6 +917,9 @@ enum virtchnl_proto_hdr_field { VIRTCHNL_PROTO_HDR_PFCP_S_FIELD = PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_PFCP), VIRTCHNL_PROTO_HDR_PFCP_SEID, + /* GTPC */ + VIRTCHNL_PROTO_HDR_GTPC_TEID = + PROTO_HDR_FIELD_START(VIRTCHNL_PROTO_HDR_GTPC), }; struct virtchnl_proto_hdr { From patchwork Tue Sep 8 09:50:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 76906 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5BC54A04AA; Tue, 8 Sep 2020 11:54:20 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 94B001C0CD; Tue, 8 Sep 2020 11:54:14 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 02D981BEE1 for ; Tue, 8 Sep 2020 11:54:12 +0200 (CEST) IronPort-SDR: 8WcWi2CG9+rbtFQuMNdjylGE7/DPxHK3PDv8e3EPL66T/J4R9eSfcqsTyFLVlimrL76mnQ0Jhk q06T4WlGhkpA== X-IronPort-AV: E=McAfee;i="6000,8403,9737"; a="219662248" X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="219662248" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2020 02:54:12 -0700 IronPort-SDR: qOEc0iyF/HB/gtvvPacM7ohRQnj8Q37jt3nvvGxujkGaUn/F/+crLZRGys8ptmnXnjj6foU3Pz qyUFV+DGH+HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="317136366" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by orsmga002.jf.intel.com with ESMTP; 08 Sep 2020 02:54:10 -0700 From: alvinx.zhang@intel.com To: jia.guo@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Tue, 8 Sep 2020 17:50:14 +0800 Message-Id: <20200908095015.23708-2-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200908095015.23708-1-alvinx.zhang@intel.com> References: <20200908095015.23708-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 2/3] net/iavf: support outer IP hash for GTPC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang Add patterns and headers for GTPC, now outer IP hash can be configured as input sets for GTPC packet. Signed-off-by: Alvin Zhang --- drivers/net/iavf/iavf_generic_flow.c | 18 ++++++++++++++++++ drivers/net/iavf/iavf_generic_flow.h | 6 ++++++ drivers/net/iavf/iavf_hash.c | 15 +++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/drivers/net/iavf/iavf_generic_flow.c b/drivers/net/iavf/iavf_generic_flow.c index 321a4dc..00e7f15 100644 --- a/drivers/net/iavf/iavf_generic_flow.c +++ b/drivers/net/iavf/iavf_generic_flow.c @@ -315,6 +315,15 @@ enum rte_flow_item_type iavf_pattern_eth_qinq_ipv6_icmp6[] = { RTE_FLOW_ITEM_TYPE_END, }; +/* IPv4 GTPC */ +enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpc[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV4, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_GTPC, + RTE_FLOW_ITEM_TYPE_END, +}; + /* IPV4 GTPU (EH) */ enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpu[] = { RTE_FLOW_ITEM_TYPE_ETH, @@ -333,6 +342,15 @@ enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpu_eh[] = { RTE_FLOW_ITEM_TYPE_END, }; +/* IPv6 GTPC */ +enum rte_flow_item_type iavf_pattern_eth_ipv6_gtpc[] = { + RTE_FLOW_ITEM_TYPE_ETH, + RTE_FLOW_ITEM_TYPE_IPV6, + RTE_FLOW_ITEM_TYPE_UDP, + RTE_FLOW_ITEM_TYPE_GTPC, + RTE_FLOW_ITEM_TYPE_END, +}; + /* IPV6 GTPU (EH) */ enum rte_flow_item_type iavf_pattern_eth_ipv6_gtpu[] = { RTE_FLOW_ITEM_TYPE_ETH, diff --git a/drivers/net/iavf/iavf_generic_flow.h b/drivers/net/iavf/iavf_generic_flow.h index f365cc3..dbc7294 100644 --- a/drivers/net/iavf/iavf_generic_flow.h +++ b/drivers/net/iavf/iavf_generic_flow.h @@ -182,10 +182,16 @@ extern enum rte_flow_item_type iavf_pattern_eth_vlan_ipv6_icmp6[]; extern enum rte_flow_item_type iavf_pattern_eth_qinq_ipv6_icmp6[]; +/* IPv4 GTPC */ +extern enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpc[]; + /* IPv4 GTPU (EH) */ extern enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpu[]; extern enum rte_flow_item_type iavf_pattern_eth_ipv4_gtpu_eh[]; +/* IPv4 GTPC */ +extern enum rte_flow_item_type iavf_pattern_eth_ipv6_gtpc[]; + /* IPv6 GTPU (EH) */ extern enum rte_flow_item_type iavf_pattern_eth_ipv6_gtpu[]; extern enum rte_flow_item_type iavf_pattern_eth_ipv6_gtpu_eh[]; diff --git a/drivers/net/iavf/iavf_hash.c b/drivers/net/iavf/iavf_hash.c index aab8b14..ddea3dd 100644 --- a/drivers/net/iavf/iavf_hash.c +++ b/drivers/net/iavf/iavf_hash.c @@ -132,6 +132,9 @@ struct iavf_hash_flow_cfg { VIRTCHNL_PROTO_HDR_PFCP, \ FIELD_SELECTOR(VIRTCHNL_PROTO_HDR_PFCP_SEID), {BUFF_NOUSED} } +#define proto_hdr_gtpc { \ + VIRTCHNL_PROTO_HDR_GTPC, 0, {BUFF_NOUSED} } + #define TUNNEL_LEVEL_OUTER 0 #define TUNNEL_LEVEL_INNER 1 @@ -256,6 +259,14 @@ struct virtchnl_proto_hdrs ipv6_pfcp_tmplt = { TUNNEL_LEVEL_OUTER, 2, {proto_hdr_ipv6, proto_hdr_pfcp} }; +struct virtchnl_proto_hdrs ipv4_udp_gtpc_tmplt = { + TUNNEL_LEVEL_OUTER, 3, {proto_hdr_ipv4, proto_hdr_udp, proto_hdr_gtpc} +}; + +struct virtchnl_proto_hdrs ipv6_udp_gtpc_tmplt = { + TUNNEL_LEVEL_OUTER, 3, {proto_hdr_ipv6, proto_hdr_udp, proto_hdr_gtpc} +}; + /* rss type super set */ /* IPv4 outer */ @@ -365,6 +376,7 @@ struct virtchnl_proto_hdrs ipv6_pfcp_tmplt = { {iavf_pattern_eth_ipv4_ah, IAVF_RSS_TYPE_IPV4_AH, &ipv4_ah_tmplt}, {iavf_pattern_eth_ipv4_l2tpv3, IAVF_RSS_TYPE_IPV4_L2TPV3, &ipv4_l2tpv3_tmplt}, {iavf_pattern_eth_ipv4_pfcp, IAVF_RSS_TYPE_IPV4_PFCP, &ipv4_pfcp_tmplt}, + {iavf_pattern_eth_ipv4_gtpc, ETH_RSS_IPV4, &ipv4_udp_gtpc_tmplt}, /* IPv6 */ {iavf_pattern_eth_ipv6, IAVF_RSS_TYPE_OUTER_IPV6, &outer_ipv6_tmplt}, {iavf_pattern_eth_ipv6_udp, IAVF_RSS_TYPE_OUTER_IPV6_UDP, &outer_ipv6_udp_tmplt}, @@ -391,6 +403,7 @@ struct virtchnl_proto_hdrs ipv6_pfcp_tmplt = { {iavf_pattern_eth_ipv6_ah, IAVF_RSS_TYPE_IPV6_AH, &ipv6_ah_tmplt}, {iavf_pattern_eth_ipv6_l2tpv3, IAVF_RSS_TYPE_IPV6_L2TPV3, &ipv6_l2tpv3_tmplt}, {iavf_pattern_eth_ipv6_pfcp, IAVF_RSS_TYPE_IPV6_PFCP, &ipv6_pfcp_tmplt}, + {iavf_pattern_eth_ipv6_gtpc, ETH_RSS_IPV6, &ipv6_udp_gtpc_tmplt}, }; struct virtchnl_proto_hdrs *iavf_hash_default_hdrs[] = { @@ -592,6 +605,8 @@ struct virtchnl_proto_hdrs *iavf_hash_default_hdrs[] = { else if (rss_type & ETH_RSS_L4_DST_ONLY) VIRTCHNL_DEL_PROTO_HDR_FIELD(hdr, VIRTCHNL_PROTO_HDR_UDP_SRC_PORT); + } else { + hdr->field_selector = 0; } break; case VIRTCHNL_PROTO_HDR_TCP: From patchwork Tue Sep 8 09:50:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 76907 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58090A04AA; Tue, 8 Sep 2020 11:54:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 15F271C0D4; Tue, 8 Sep 2020 11:54:16 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id B7E101C0CF for ; Tue, 8 Sep 2020 11:54:14 +0200 (CEST) IronPort-SDR: A5UQaYmtPG6fAUJa0DDyiUih6iCLZF86HpTBeu+kHXDXNYCiwRZTSE+T42qS8LbbZN9Dqk7P7R KLPA/L9tS7iA== X-IronPort-AV: E=McAfee;i="6000,8403,9737"; a="219662250" X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="219662250" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2020 02:54:14 -0700 IronPort-SDR: wtNtAF17B39nVgWfvTLLB11b2EpoNI0UpMbB8hP56X/dAs1OVQlWLki6u/FifcecukcrsM28hD piZ/sfDHAaNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,405,1592895600"; d="scan'208";a="317136377" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by orsmga002.jf.intel.com with ESMTP; 08 Sep 2020 02:54:12 -0700 From: alvinx.zhang@intel.com To: jia.guo@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Tue, 8 Sep 2020 17:50:15 +0800 Message-Id: <20200908095015.23708-3-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200908095015.23708-1-alvinx.zhang@intel.com> References: <20200908095015.23708-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 3/3] net/iavf: support outer IP hash for GTPU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang Add headers for GTPU, now outer IP hash can be configured as input sets for GTPU packet. Signed-off-by: Alvin Zhang --- drivers/net/iavf/iavf_hash.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/iavf/iavf_hash.c b/drivers/net/iavf/iavf_hash.c index ddea3dd..8aeb3f83 100644 --- a/drivers/net/iavf/iavf_hash.c +++ b/drivers/net/iavf/iavf_hash.c @@ -135,6 +135,9 @@ struct iavf_hash_flow_cfg { #define proto_hdr_gtpc { \ VIRTCHNL_PROTO_HDR_GTPC, 0, {BUFF_NOUSED} } +#define proto_hdr_gtpu { \ + VIRTCHNL_PROTO_HDR_GTPU_IP, 0, {BUFF_NOUSED} } + #define TUNNEL_LEVEL_OUTER 0 #define TUNNEL_LEVEL_INNER 1 @@ -267,6 +270,14 @@ struct virtchnl_proto_hdrs ipv6_udp_gtpc_tmplt = { TUNNEL_LEVEL_OUTER, 3, {proto_hdr_ipv6, proto_hdr_udp, proto_hdr_gtpc} }; +struct virtchnl_proto_hdrs outer_ipv4_udp_gtpu_tmplt = { + TUNNEL_LEVEL_OUTER, 3, {proto_hdr_ipv4, proto_hdr_udp, proto_hdr_gtpu} +}; + +struct virtchnl_proto_hdrs outer_ipv6_udp_gtpu_tmplt = { + TUNNEL_LEVEL_OUTER, 3, {proto_hdr_ipv6, proto_hdr_udp, proto_hdr_gtpu} +}; + /* rss type super set */ /* IPv4 outer */ @@ -359,6 +370,7 @@ struct virtchnl_proto_hdrs ipv6_udp_gtpc_tmplt = { {iavf_pattern_eth_vlan_ipv4_udp, IAVF_RSS_TYPE_VLAN_IPV4_UDP, &outer_ipv4_udp_tmplt}, {iavf_pattern_eth_vlan_ipv4_tcp, IAVF_RSS_TYPE_VLAN_IPV4_TCP, &outer_ipv4_tcp_tmplt}, {iavf_pattern_eth_vlan_ipv4_sctp, IAVF_RSS_TYPE_VLAN_IPV4_SCTP, &outer_ipv4_sctp_tmplt}, + {iavf_pattern_eth_ipv4_gtpu, ETH_RSS_IPV4, &outer_ipv4_udp_gtpu_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv4, IAVF_RSS_TYPE_GTPU_IPV4, &inner_ipv4_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv4_udp, IAVF_RSS_TYPE_GTPU_IPV4_UDP, &inner_ipv4_udp_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv4_tcp, IAVF_RSS_TYPE_GTPU_IPV4_TCP, &inner_ipv4_tcp_tmplt}, @@ -386,6 +398,7 @@ struct virtchnl_proto_hdrs ipv6_udp_gtpc_tmplt = { {iavf_pattern_eth_vlan_ipv6_udp, IAVF_RSS_TYPE_VLAN_IPV6_UDP, &outer_ipv6_udp_tmplt}, {iavf_pattern_eth_vlan_ipv6_tcp, IAVF_RSS_TYPE_VLAN_IPV6_TCP, &outer_ipv6_tcp_tmplt}, {iavf_pattern_eth_vlan_ipv6_sctp, IAVF_RSS_TYPE_VLAN_IPV6_SCTP, &outer_ipv6_sctp_tmplt}, + {iavf_pattern_eth_ipv6_gtpu, ETH_RSS_IPV6, &outer_ipv6_udp_gtpu_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv6, IAVF_RSS_TYPE_GTPU_IPV6, &inner_ipv6_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv6_udp, IAVF_RSS_TYPE_GTPU_IPV6_UDP, &inner_ipv6_udp_tmplt}, {iavf_pattern_eth_ipv4_gtpu_ipv6_tcp, IAVF_RSS_TYPE_GTPU_IPV6_TCP, &inner_ipv6_tcp_tmplt},