From patchwork Tue Jun 23 08:41:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 72009 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E1C6A0350; Tue, 23 Jun 2020 10:41:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 043461D5AF; Tue, 23 Jun 2020 10:41:29 +0200 (CEST) Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130054.outbound.protection.outlook.com [40.107.13.54]) by dpdk.org (Postfix) with ESMTP id 0E45F1D5AD for ; Tue, 23 Jun 2020 10:41:28 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XhFMhCwYg6ZBppeNxd09dfwnNlfTUeLgVIq41AMcWHtcQtLF3b85R3ofujsGbGlaIo5nCkwBvf8/n4nM9hiwVVUhLnEz21e9sEVc9/KrgW0ihFrpF+fAE46nWv916tyOkY6a89mEcRWB3guiO0CRKC2YnQDyKMFhBSwjwGZFw+zX10NdxdXk3Wd6+qHeDeQmP8ru5o2EMZqTtYkgq4jSDe4ulr/zixE09X9M16R6vmgMJ1WJtbKdkIs6w9AYUP6Qf46ydEIE0eJ/I+jacBP87GtPImdtP3JLiz3a1gB8/D2tUO+wd9ZvLDXNUPp0/2EePcElut/pgD98hZ0XP7/dXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wToKHgcSZGpzGfssAz0AUiMrOJJ6kugslaNZlDdqT60=; b=NKXcoPVITxx31/hMVM2nfgSLNXO1iuGXV6ity4OQbZONnnM2XM3d3HHJAMd5mHIHFHvv/9KD89+AJUqR2F0nMNU9DtRYWl/Qvhx5ld1+u8669vO3xKIr49EdsiKIaMe+lOhMot0Ilwf8Ry5Sb7L1xNP/trP3DjA9bQD+yF1U8JSHGzhDrgiZi/pk5AJfZXQgLgmZLOuMw579jfE6+F/HTrvx0+3biGWXqy3B8M2z979IqXsS7Gw5JhYxAF60A3fu+T/HoDtNGuvxH5n9Jyvb1G4+XcCMnZsKCZ1bS9zhbb2EZjyHTnD+DoAXNy6wtedU/qGwGJ34mI4IJ+k4ve6xJA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mellanox.com; dmarc=pass action=none header.from=mellanox.com; dkim=pass header.d=mellanox.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wToKHgcSZGpzGfssAz0AUiMrOJJ6kugslaNZlDdqT60=; b=k1nj2xAkbu6+kUwBctQkkCgRY5eyf9LpOzqZTE8hNROApAL/k36Tg+N7l9ooZR/J/q8GE+PPE+uuQ0cjq/UTscu52a1/hcO9KbdLoXo2ee0DhXTLqIY+bdvgHPxeCATkWGx1Afmyi6eFUY73SStN+gXp4isdNQUyaPvzkE+FKbI= Authentication-Results: dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com; Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) by AM0PR0502MB4036.eurprd05.prod.outlook.com (2603:10a6:208:d::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Tue, 23 Jun 2020 08:41:26 +0000 Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60]) by AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60%4]) with mapi id 15.20.3109.021; Tue, 23 Jun 2020 08:41:26 +0000 From: Shiri Kuzin To: dev@dpdk.org Cc: matan@mellanox.com, viacheslavo@mellanox.com Date: Tue, 23 Jun 2020 11:41:05 +0300 Message-Id: <1592901667-12161-2-git-send-email-shirik@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1592901667-12161-1-git-send-email-shirik@mellanox.com> References: <1592901667-12161-1-git-send-email-shirik@mellanox.com> X-ClientProxiedBy: AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) To AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mellanox.com (94.188.199.18) by AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22 via Frontend Transport; Tue, 23 Jun 2020 08:41:25 +0000 X-Mailer: git-send-email 1.8.3.1 X-Originating-IP: [94.188.199.18] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d751c98f-946b-4715-d2be-08d81751372e X-MS-TrafficTypeDiagnostic: AM0PR0502MB4036: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-Forefront-PRVS: 04433051BF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TYP6Nf183JbXWj0pcEfQ+oYwlsOXz40PCNWVwFmaWp7p7pPA+yDQzkMU3WJuDxsBBMNtZb0FXuYC1I76YSdvP6qGIAysc0vNojLWSIA5I42Tnr9ePQrrd21uzNtUQkIaf8tLq32oW9SXVrlwQsXc1LwceJvzFRk1RYscyQQB5tPmsjH9qjuNYS1Naosmpz0i0m3B2yXgD4k+ErA4xUGLnyeQMsPvPPlFpru7D+Jq32BJht/UAXu6NRFcbQx+NDDgQt0CwtI24A51/P43Gtyx1CuVDU64JhlBg+EYd5Pl+O4ml4+PjDfldTfiqYK2PTGt X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0502MB3874.eurprd05.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(366004)(346002)(396003)(376002)(136003)(956004)(52116002)(7696005)(8676002)(2616005)(36756003)(55016002)(86362001)(316002)(26005)(107886003)(4326008)(16526019)(186003)(478600001)(8936002)(5660300002)(66946007)(66476007)(6666004)(66556008)(2906002)(8886007)(6916009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: xkq7aW/XWH14yWm3fS/zJUG/5BOzDgKkKMJhc/Et8z/ntAbudKrUBuwe2LpiuJj2hFQedQsT2c1FQQgbvlV4w1DdzFq/e3V9DMa+OcSEuBT60gwGrlW6UaXgXVar8CM/djXvaeZhs5/6um5xkS8pr158xkTdX0XASvxOpohNeSMibRpgwx/41Yf/UJSts3z/cuJAj0nszXxu2ZK6zNrm/uCmWsdOr1RkYrAwuK/oTOKsqJp1YMTAmqCBnhXNXbLZb1S28+ZBdmF4/pkD9N2I7DuFuV6gz0O6GfrSABmfCXtnGddWUDpM+TpFAppSPApPAW609qrvMalW6NrdapQ4ndAFz3BAdguiuGo5bq1rTy0sgROV7RO0GCWP2WWzr7R1Dn8KfRCP4ND3NERmHhFlb6ErR2FxBc3rmZA2eNXd1ymPnsYalsxQyCr4W2q36SX8A16t1Idm6ky/7mFGFAltvhe+v66YRGBP6dZWkEpFjZs= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: d751c98f-946b-4715-d2be-08d81751372e X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2020 08:41:26.1888 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ru7LS/lTg3FKPC/OEu4aCv8eokC2+CX/3IVsJDdJjdg5YsqiXp6Pq8bWPt1Ozy0Ae8FRMLFdI/MacvELT54QKA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4036 Subject: [dpdk-dev] [PATCH 1/3] common/mlx5: add default miss action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add dv_create_action_default_miss wrapper function for the action added to the rdma-core MLX5DV_FLOW_ACTION_DEFAULT_MISS. When a packet matches MLX5DV_FLOW_ACTION_DEFAULT_MISS action it is steered to the default miss of the verbs steering domain. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/common/mlx5/Makefile | 5 +++++ drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/linux/mlx5_glue.c | 13 +++++++++++++ drivers/common/mlx5/linux/mlx5_glue.h | 1 + 4 files changed, 21 insertions(+) diff --git a/drivers/common/mlx5/Makefile b/drivers/common/mlx5/Makefile index 622bde4..f6c762b 100644 --- a/drivers/common/mlx5/Makefile +++ b/drivers/common/mlx5/Makefile @@ -157,6 +157,11 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh enum MLX5DV_FLOW_ACTION_COUNTERS_DEVX \ $(AUTOCONF_OUTPUT) $Q sh -- '$<' '$@' \ + HAVE_MLX5_DR_CREATE_ACTION_DEFAULT_MISS \ + infiniband/mlx5dv.h \ + enum MLX5DV_FLOW_ACTION_DEFAULT_MISS \ + $(AUTOCONF_OUTPUT) + $Q sh -- '$<' '$@' \ HAVE_IBV_DEVX_ASYNC \ infiniband/mlx5dv.h \ func mlx5dv_devx_obj_query_async \ diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 638bb2b..2294213 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -95,6 +95,8 @@ has_sym_args = [ 'mlx5dv_devx_obj_create' ], [ 'HAVE_IBV_FLOW_DEVX_COUNTERS', 'infiniband/mlx5dv.h', 'MLX5DV_FLOW_ACTION_COUNTERS_DEVX' ], + [ 'HAVE_MLX5_DR_CREATE_ACTION_DEFAULT_MISS', 'infiniband/mlx5dv.h', + 'MLX5DV_FLOW_ACTION_DEFAULT_MISS' ], [ 'HAVE_IBV_DEVX_ASYNC', 'infiniband/mlx5dv.h', 'mlx5dv_devx_obj_query_async' ], [ 'HAVE_IBV_DEVX_QP', 'infiniband/mlx5dv.h', diff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c index c91ee33..62c4cc7 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.c +++ b/drivers/common/mlx5/linux/mlx5_glue.c @@ -795,6 +795,17 @@ #endif } +static void * +mlx5_glue_dr_create_flow_action_default_miss(void) +{ +#if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_DEFAULT_MISS) + return mlx5dv_dr_action_create_default_miss(); +#else + errno = ENOTSUP; + return NULL; +#endif +} + static int mlx5_glue_dv_destroy_flow(void *flow_id) { @@ -1276,6 +1287,8 @@ .dv_create_flow_action_tag = mlx5_glue_dv_create_flow_action_tag, .dv_create_flow_action_meter = mlx5_glue_dv_create_flow_action_meter, .dv_modify_flow_action_meter = mlx5_glue_dv_modify_flow_action_meter, + .dr_create_flow_action_default_miss = + mlx5_glue_dr_create_flow_action_default_miss, .dv_destroy_flow = mlx5_glue_dv_destroy_flow, .dv_destroy_flow_matcher = mlx5_glue_dv_destroy_flow_matcher, .dv_open_device = mlx5_glue_dv_open_device, diff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h index 5d238a4..069d854 100644 --- a/drivers/common/mlx5/linux/mlx5_glue.h +++ b/drivers/common/mlx5/linux/mlx5_glue.h @@ -237,6 +237,7 @@ struct mlx5_glue { (struct mlx5dv_dr_flow_meter_attr *attr); int (*dv_modify_flow_action_meter)(void *action, struct mlx5dv_dr_flow_meter_attr *attr, uint64_t modify_bits); + void *(*dr_create_flow_action_default_miss)(void); int (*dv_destroy_flow)(void *flow); int (*dv_destroy_flow_matcher)(void *matcher); struct ibv_context *(*dv_open_device)(struct ibv_device *device); From patchwork Tue Jun 23 08:41:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 72010 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1D3F9A0350; Tue, 23 Jun 2020 10:41:42 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9BC1F1D5C8; Tue, 23 Jun 2020 10:41:32 +0200 (CEST) Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130045.outbound.protection.outlook.com [40.107.13.45]) by dpdk.org (Postfix) with ESMTP id 46BF21D5C1 for ; Tue, 23 Jun 2020 10:41:30 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g6ZRpNSmcZbTj3nlLzhijMPrck4baHer4/FwimEIamPJNd4wzkxDK+92DNsEff6ZuSRoN1xpWwYj0yGXiNlG8464kdxyMw2aAH2M16lFlhWINpNakXdYzSBz3wN8xseSngvxRLUfi9U8Ns9VPX866ei4gBkXebPsqAlw8dXtW3V1jjIwaTvfyL1ybZ1iNoTM13ccJHKnhY0n23ffs7bOtrtuaqeLW1epzF/1Pn4IPizUSBVGpt3mDEkiTEXsa7YrJZJtz5GlC/efbxQcHMw/lXXXRA7P4GVzVpW83AZ1WXgD7ztsbGh63nJWv+/ke7N4cDjvn5NVIlUzgmB1Ep6T0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Kv0l57G/SZFCw/1FjjywPq5N1Uh8CtrkMr4Gm4ADq2E=; b=nLFaEiM3j2c0PbYPd/HfWvquvXMj4uHriZpOdkoSOAHwv9v7CO7htOY2eW1rNcWye8C9jb0NIt/kWI6tKEXWcmI6GWEumPv/ZhoTIwS3M0Pjf7YTEuioZ3HRPCgeUt3zanX4hhiKZNIOcFmd4EoOti/tfh7T8heW8JslnN9H5djn80cf/1RC1I/yNASGMVKfJ+tbuNBPQ4v9gOEFq1WRu0YfHWWr5ToE+fLJNcdy5SEFORP3oYiKAOakug2+xUUOpy24SG+vQ8XbrdblbNYm1pJkeuKABOtWa7CZN9zot+Evt2boypxM8thamTs2aOdi4qm26HAWRoIn6DtcVZSjEA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mellanox.com; dmarc=pass action=none header.from=mellanox.com; dkim=pass header.d=mellanox.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Kv0l57G/SZFCw/1FjjywPq5N1Uh8CtrkMr4Gm4ADq2E=; b=USTtAthRKX5LOXtE2mHcBMlPq/1PDXNsh0NUL9s0RjpIyweFn1TpQH/LKezmZKOVLChXRBKd6wO9Irrk5fbtDE4DJTIxZCfuyqAda2uvy6GH8xi64FO3Ij0AoO4uCe/7G/U9aU3ionxZXTwwAZBId3M1seaM/ZyMSHYTy/nV/VE= Authentication-Results: dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com; Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) by AM0PR0502MB4036.eurprd05.prod.outlook.com (2603:10a6:208:d::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Tue, 23 Jun 2020 08:41:28 +0000 Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60]) by AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60%4]) with mapi id 15.20.3109.021; Tue, 23 Jun 2020 08:41:28 +0000 From: Shiri Kuzin To: dev@dpdk.org Cc: matan@mellanox.com, viacheslavo@mellanox.com Date: Tue, 23 Jun 2020 11:41:06 +0300 Message-Id: <1592901667-12161-3-git-send-email-shirik@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1592901667-12161-1-git-send-email-shirik@mellanox.com> References: <1592901667-12161-1-git-send-email-shirik@mellanox.com> X-ClientProxiedBy: AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) To AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mellanox.com (94.188.199.18) by AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22 via Frontend Transport; Tue, 23 Jun 2020 08:41:28 +0000 X-Mailer: git-send-email 1.8.3.1 X-Originating-IP: [94.188.199.18] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 64ca3863-e64f-4532-ea96-08d8175138d8 X-MS-TrafficTypeDiagnostic: AM0PR0502MB4036: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-Forefront-PRVS: 04433051BF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sOMDikGreZekNAu4yUC1swaigaCmLtaEnMhlrsnKaze0grm8vCVIgCufGBSKrRhoLhp6bhpCMwUiCwhcuoRWDAXfnf3cH6YDNNfFHoKFxALgrZi8bM9o7MnqL3jawGnZ7L+tKsz1QeBpiICEskJv2htZhG2O2O5L5QQXcFCZVx9mhyXMMLnD2aDMofXWdPUUW2nK34ELGEQZ1ZUjqYeZAlz8YWYudHTrE6+jDtm5169mboj7XIsJ6afwVw7AaATK6weRVYttHYV4ddCYrCkSldKifQQM4/trOXExZRhUSR1HNOL/Nu0sFtHBfdtX9cEREdVZZLH3kGyQbhlK1TGQhQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0502MB3874.eurprd05.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(366004)(346002)(396003)(376002)(136003)(956004)(52116002)(7696005)(8676002)(2616005)(36756003)(55016002)(86362001)(316002)(26005)(107886003)(4326008)(16526019)(186003)(30864003)(478600001)(8936002)(5660300002)(66946007)(66476007)(83380400001)(6666004)(66556008)(2906002)(8886007)(6916009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 6wNBPCzuIpCy9DWGfAr8L5dourvrY/WgKL/wFKrRkfPlOvGH/GspDo9ly1qABaAOQWBxnubkuGAGEwOSiV3xf+jirgoU65UZSaHhckkDBbfq6lbmmdBJLcYGkbybDE3MOPLBEEGgQ5jDbFTHIpMinU0YseqHYDyvqc9PTdJQH249IXIGgNNkVwOn3CsxxFT1HIA60WMVvh+nQmKZHqg2uaT3z5+XQNgKrppByuLVqLXyJAE4ikE6VDQbcakF3kQOtAfThCIlsmw/7GB3IkNLmFM19rkdjGgh1Y93KsqjMTS1Kvr+dCNQZbpYVLWuuRIEc3jD3TxpeOc/WRjvBI3g0/cng7uaSs2hcqTsq2AhnHx98wXmGEqTZq3CedjmOgC1sOoQ5zBwv0dLRkdd3BqIEaYOoyGPwuUkBDdcBsadc37sa416kdEJC9gbNDCs57RXS/Cbe1qghssaOlJa2b4+YkeJgN5PQFAsmhAjjr2VqZo= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 64ca3863-e64f-4532-ea96-08d8175138d8 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2020 08:41:28.8323 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 12/M4Rudh7oTLBzRb0RSePd30Mio0TsVDEvzY4heMxX2NLLIsH2a5g70chTynjxJod07AwLuMKv4ydGLi3MNBQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4036 Subject: [dpdk-dev] [PATCH 2/3] net/mlx5: add default miss action to flow engine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The new action is an internal mlx5 action that will call the rdma-core function MLX5DV_FLOW_ACTION_DEFAULT_MISS. The default miss action will be used when a bond is configured to allow traffic related to the bond to be managed in the kernel. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.h | 9 +++ drivers/net/mlx5/mlx5_flow.c | 92 +++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 11 +++- drivers/net/mlx5/mlx5_flow_dv.c | 127 +++++++++++++++++++++++++++++++++++++--- 4 files changed, 231 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8a09ebc..93bde5a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -451,6 +451,12 @@ struct mlx5_flow_counter_mng { LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; }; +/* Default miss action resource structure. */ +struct mlx5_flow_default_miss_resource { + void *action; /* Pointer to the rdma-core action. */ + rte_atomic32_t refcnt; /* Default miss action reference counter. */ +}; + #define MLX5_AGE_EVENT_NEW 1 #define MLX5_AGE_TRIGGER 2 #define MLX5_AGE_SET(age_info, BIT) \ @@ -559,6 +565,8 @@ struct mlx5_dev_ctx_shared { uint32_t port_id_action_list; /* List of port ID actions. */ uint32_t push_vlan_action_list; /* List of push VLAN actions. */ struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ + struct mlx5_flow_default_miss_resource default_miss; + /* Default miss action resource structure. */ struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; /* Memory Pool for mlx5 flow resources. */ struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ @@ -872,6 +880,7 @@ int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, int mlx5_ctrl_flow(struct rte_eth_dev *dev, struct rte_flow_item_eth *eth_spec, struct rte_flow_item_eth *eth_mask); +int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 3a48b89..4700ec1 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1238,6 +1238,43 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, } /* + * Validate the default miss action. + * + * @param[in] action_flags + * Bit-fields that holds the actions detected until now. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_validate_action_default_miss(uint64_t action_flags, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + if (action_flags & MLX5_FLOW_FATE_ACTIONS) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, NULL, + "can't have 2 fate actions in" + " same flow"); + if (attr->egress) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, + "default miss action not supported " + "for egress"); + if (attr->group) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, + "only group 0 is supported"); + if (attr->transfer) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, + NULL, "transfer is not supported"); + return 0; +} + +/* * Validate the count action. * * @param[in] dev @@ -4984,6 +5021,61 @@ struct rte_flow * } /** + * Create default miss flow rule matching lacp traffic + * + * @param dev + * Pointer to Ethernet device. + * @param eth_spec + * An Ethernet flow spec to apply. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_lacp_miss(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + /* + * The LACP matching is done by only using ether type since using + * a multicast dst mac causes kernel to give low priority to this flow. + */ + static const struct rte_flow_item_eth lacp_spec = { + .type = RTE_BE16(0x8809), + }; + static const struct rte_flow_item_eth lacp_mask = { + .type = 0xffff, + }; + const struct rte_flow_attr attr = { + .ingress = 1, + }; + struct rte_flow_item items[] = { + { + .type = RTE_FLOW_ITEM_TYPE_ETH, + .spec = &lacp_spec, + .mask = &lacp_mask, + }, + { + .type = RTE_FLOW_ITEM_TYPE_END, + }, + }; + struct rte_flow_action actions[] = { + { + .type = MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, + }, + { + .type = RTE_FLOW_ACTION_TYPE_END, + }, + }; + struct rte_flow_error error; + uint32_t flow_idx = flow_list_create(dev, &priv->ctrl_flows, + &attr, items, actions, false, &error); + + if (!flow_idx) + return -rte_errno; + return 0; +} + +/** * Destroy a flow. * * @see rte_flow_destroy() diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 2c96677..50ec741 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -43,6 +43,7 @@ enum mlx5_rte_flow_action_type { MLX5_RTE_FLOW_ACTION_TYPE_TAG, MLX5_RTE_FLOW_ACTION_TYPE_MARK, MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, + MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, }; /* Matches on selected register. */ @@ -200,10 +201,12 @@ enum mlx5_feature_name { #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32) #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33) #define MLX5_FLOW_ACTION_AGE (1ull << 34) +#define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35) #define MLX5_FLOW_FATE_ACTIONS \ (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \ - MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP) + MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \ + MLX5_FLOW_ACTION_DEFAULT_MISS) #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \ (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \ @@ -364,6 +367,7 @@ enum mlx5_flow_fate_type { MLX5_FLOW_FATE_JUMP, MLX5_FLOW_FATE_PORT_ID, MLX5_FLOW_FATE_DROP, + MLX5_FLOW_FATE_DEFAULT_MISS, MLX5_FLOW_FATE_MAX, }; @@ -545,6 +549,8 @@ struct mlx5_flow_handle { /**< Index to port ID action resource. */ uint32_t rix_fate; /**< Generic value indicates the fate action. */ + uint32_t rix_default_fate; + /**< Indicates default miss fate action. */ }; #ifdef HAVE_IBV_FLOW_DV_SUPPORT struct mlx5_flow_handle_dv dvh; @@ -946,6 +952,9 @@ int mlx5_flow_validate_action_rss(const struct rte_flow_action *action, const struct rte_flow_attr *attr, uint64_t item_flags, struct rte_flow_error *error); +int mlx5_flow_validate_action_default_miss(uint64_t action_flags, + const struct rte_flow_attr *attr, + struct rte_flow_error *error); int mlx5_flow_validate_attributes(struct rte_eth_dev *dev, const struct rte_flow_attr *attributes, struct rte_flow_error *error); diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f174009..d1eb65b 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -79,6 +79,9 @@ flow_dv_tbl_resource_release(struct rte_eth_dev *dev, struct mlx5_flow_tbl_resource *tbl); +static int +flow_dv_default_miss_resource_release(struct rte_eth_dev *dev); + /** * Initialize flow attributes structure according to flow items' types. * @@ -2676,6 +2679,42 @@ struct field_modify_info modify_tcp[] = { } /** + * Find existing default miss resource or create and register a new one. + * + * @param[in, out] dev + * Pointer to rte_eth_dev structure. + * @param[out] error + * pointer to error structure. + * + * @return + * 0 on success otherwise -errno and errno is set. + */ +static int +flow_dv_default_miss_resource_register(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_flow_default_miss_resource *cache_resource = + &sh->default_miss; + int cnt = rte_atomic32_read(&cache_resource->refcnt); + + if (!cnt) { + MLX5_ASSERT(cache_resource->action); + cache_resource->action = + mlx5_glue->dr_create_flow_action_default_miss(); + if (!cache_resource->action) + return rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "cannot create default miss action"); + DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++", + (void *)cache_resource->action, cnt); + } + rte_atomic32_inc(&cache_resource->refcnt); + return 0; +} + +/** * Find existing table port ID resource or create and register a new one. * * @param[in, out] dev @@ -5249,6 +5288,15 @@ struct field_modify_info modify_tcp[] = { action_flags |= MLX5_FLOW_ACTION_RSS; ++actions_n; break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + ret = + mlx5_flow_validate_action_default_miss(action_flags, + attr, error); + if (ret < 0) + return ret; + action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS; + ++actions_n; + break; case RTE_FLOW_ACTION_TYPE_COUNT: ret = flow_dv_validate_action_count(dev, error); if (ret < 0) @@ -8212,6 +8260,11 @@ struct field_modify_info modify_tcp[] = { return -rte_errno; action_flags |= MLX5_FLOW_ACTION_SET_TAG; break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS; + dev_flow->handle->fate_action = + MLX5_FLOW_FATE_DEFAULT_MISS; + break; case RTE_FLOW_ACTION_TYPE_METER: mtr = actions->conf; if (!flow->meter) { @@ -8304,7 +8357,11 @@ struct field_modify_info modify_tcp[] = { flow_dv_translate_item_eth(match_mask, match_value, items, tunnel, dev_flow->dv.group); - matcher.priority = MLX5_PRIORITY_MAP_L2; + matcher.priority = action_flags & + MLX5_FLOW_ACTION_DEFAULT_MISS && + !dev_flow->external ? + MLX5_PRIORITY_MAP_L3 : + MLX5_PRIORITY_MAP_L2; last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : MLX5_FLOW_LAYER_OUTER_L2; break; @@ -8604,7 +8661,19 @@ struct field_modify_info modify_tcp[] = { } dh->rix_hrxq = hrxq_idx; dv->actions[n++] = hrxq->action; + } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) { + if (flow_dv_default_miss_resource_register + (dev, error)) { + rte_flow_error_set + (error, rte_errno, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "cannot create default miss resource"); + goto error_default_miss; + } + dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS; + dv->actions[n++] = priv->sh->default_miss.action; } + dh->ib_flow = mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object, (void *)&dv->value, n, @@ -8629,6 +8698,9 @@ struct field_modify_info modify_tcp[] = { } return 0; error: + if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) + flow_dv_default_miss_resource_release(dev); +error_default_miss: err = rte_errno; /* Save rte_errno before cleanup. */ SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, handle_idx, dh, next) { @@ -8766,6 +8838,36 @@ struct field_modify_info modify_tcp[] = { } /** + * Release a default miss resource. + * + * @param dev + * Pointer to Ethernet device. + * @return + * 1 while a reference on it exists, 0 when freed. + */ +static int +flow_dv_default_miss_resource_release(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_flow_default_miss_resource *cache_resource = + &sh->default_miss; + + MLX5_ASSERT(cache_resource->action); + DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--", + (void *)cache_resource->action, + rte_atomic32_read(&cache_resource->refcnt)); + if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) { + claim_zero(mlx5_glue->destroy_flow_action + (cache_resource->action)); + DRV_LOG(DEBUG, "default miss resource %p: removed", + (void *)cache_resource->action); + return 0; + } + return 1; +} + +/** * Release a modify-header resource. * * @param handle @@ -8892,16 +8994,26 @@ struct field_modify_info modify_tcp[] = { { if (!handle->rix_fate) return; - if (handle->fate_action == MLX5_FLOW_FATE_DROP) + switch (handle->fate_action) { + case MLX5_FLOW_FATE_DROP: mlx5_hrxq_drop_release(dev); - else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE) + break; + case MLX5_FLOW_FATE_QUEUE: mlx5_hrxq_release(dev, handle->rix_hrxq); - else if (handle->fate_action == MLX5_FLOW_FATE_JUMP) + break; + case MLX5_FLOW_FATE_JUMP: flow_dv_jump_tbl_resource_release(dev, handle); - else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID) + break; + case MLX5_FLOW_FATE_PORT_ID: flow_dv_port_id_action_resource_release(dev, handle); - else + break; + case MLX5_FLOW_FATE_DEFAULT_MISS: + flow_dv_default_miss_resource_release(dev); + break; + default: DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action); + break; + } handle->rix_fate = 0; } @@ -8934,7 +9046,8 @@ struct field_modify_info modify_tcp[] = { dh->ib_flow = NULL; } if (dh->fate_action == MLX5_FLOW_FATE_DROP || - dh->fate_action == MLX5_FLOW_FATE_QUEUE) + dh->fate_action == MLX5_FLOW_FATE_QUEUE || + dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) flow_dv_fate_resource_release(dev, dh); if (dh->vf_vlan.tag && dh->vf_vlan.created) mlx5_vlan_vmwa_release(dev, &dh->vf_vlan); From patchwork Tue Jun 23 08:41:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 72011 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C54FAA0350; Tue, 23 Jun 2020 10:41:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 462AB1D5EB; Tue, 23 Jun 2020 10:41:34 +0200 (CEST) Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50080.outbound.protection.outlook.com [40.107.5.80]) by dpdk.org (Postfix) with ESMTP id EEB9C1D5C8 for ; Tue, 23 Jun 2020 10:41:31 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VH/iLA63WXDYO6HGgm03sfRRyw5BiBA5VKHR23Oej/jnVgaWXwUrqnawpd6Yt36LlOX66Fx6fi5UlHPqe1sb1xlvkAY9qbxCXRRzPBGCWOq/3Vfh1YfYVZ/AOMxukBkj00bsWuJwwuIMxZnVIfH60hRo4uPnSuosy/gQ10SGPT5X8rxR6QGMIqWyGqwU5HYHEhKlXdtC0HZaHMmd6kSQaAOZeidOrU2pG5mG4isuyB2Y8XWrHsO090sN5D2e/pB+EASyxVcsdJrbz61Q3MPJOp7xOxmJtfbrQuBwb2UVH9t6xA8jphP6wa0VYL+Gtg0iMm3I3NSa2qLPkCcyYp/p8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uGwVy9b+VAlgLTeNRNNCTzq3FkL7LSapKDpIlhc6QE4=; b=KJ0YMaZCLN4KOOGm+GyhKnWPu84wrenVHNLVjgKpbMQDNRo1dJQ6ZLsrE/9Fp5UtnQZXhra+2vsagT64+FEvcv4rZJEHNnrj5OEVXMlo5i9tPU5ii8ljLhB1ERD09Vbc6INFgxOwB5F9sgSaz8aTfTvMl1W3gIHnmzrQEzchaM15D7TsklcliqZLeldHg4Vvj8wEMmgB/J1koNxIg3dS2Wr7VxGh5sIv14gak5gIQs9N3CJLHxjAM5ox/gqPVnpq0XHI5cb1FBz7jbadPMYmVz9KmsJO1l9R6j0d6hjL1wv3Vd4SLNV/gyp6X39vhkJy6XJvUnk6Z3C38Ej2tn+Flw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mellanox.com; dmarc=pass action=none header.from=mellanox.com; dkim=pass header.d=mellanox.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uGwVy9b+VAlgLTeNRNNCTzq3FkL7LSapKDpIlhc6QE4=; b=afSD0gGX1xDNCK2A7D4hqG2XKOTYGowyMeYbDr7a9tBe5UTm2Mg1ltU5WrQN0xN7GK7k2Y2R4dsVkZhmQ4tKBeHGKgngAyiG1kb7wYaZlg6HbzPnkPWIhYPMu2xEPCy7PZH8fNQv3jvy7nBung+T4xnUOXa5iaUkzOnh+JWzA/Q= Authentication-Results: dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com; Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) by AM0PR0502MB3618.eurprd05.prod.outlook.com (2603:10a6:208:18::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22; Tue, 23 Jun 2020 08:41:31 +0000 Received: from AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60]) by AM0PR0502MB3874.eurprd05.prod.outlook.com ([fe80::84e5:30fb:782e:5e60%4]) with mapi id 15.20.3109.021; Tue, 23 Jun 2020 08:41:31 +0000 From: Shiri Kuzin To: dev@dpdk.org Cc: matan@mellanox.com, viacheslavo@mellanox.com Date: Tue, 23 Jun 2020 11:41:07 +0300 Message-Id: <1592901667-12161-4-git-send-email-shirik@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1592901667-12161-1-git-send-email-shirik@mellanox.com> References: <1592901667-12161-1-git-send-email-shirik@mellanox.com> X-ClientProxiedBy: AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) To AM0PR0502MB3874.eurprd05.prod.outlook.com (2603:10a6:208:1a::29) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mellanox.com (94.188.199.18) by AM0PR04CA0088.eurprd04.prod.outlook.com (2603:10a6:208:be::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.22 via Frontend Transport; Tue, 23 Jun 2020 08:41:30 +0000 X-Mailer: git-send-email 1.8.3.1 X-Originating-IP: [94.188.199.18] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5ca18fcf-6203-428c-57ae-08d817513a17 X-MS-TrafficTypeDiagnostic: AM0PR0502MB3618: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 04433051BF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HEOIneTjMkZdyGfx6j05w/pgAqufYGE92JDr6LJ38mv7ft9qAgs6otT27vbRCPovyDahAfBQc8VtaoQT9X1EI6DsTjWSJC85TCkRfNtRgAWyESjV/4bfUtOIfFPKRZ67JqWGVeknj8BeCJC/gH9s1jw4JPFgkjg9UMkeSEoyiMdHMEWUMPJNg4zuwAWpMBmpgg4Dycy+wixPJSPHFnKTC6F0VRTpVyRS+7pc1YXGVmC3KtKIZENA8iJxSOI9c7cAE8vu99BKlASrBHesRc9hj0+g270xnLC93x+R1I+r48XCN9ZIEDdCaOYE/zzmg1DUj5m9g3XyJKmEoHpgKyQ84OUCykzuhlPxfq1EeFQMil4bRcEnZLll8+OoFjPuw0eW X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR0502MB3874.eurprd05.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(376002)(366004)(346002)(39860400002)(396003)(136003)(2906002)(478600001)(66476007)(66556008)(8886007)(107886003)(55016002)(4326008)(52116002)(7696005)(316002)(36756003)(8936002)(8676002)(83380400001)(86362001)(186003)(16526019)(6666004)(956004)(2616005)(6916009)(66946007)(5660300002)(26005)(309714004); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: Ha5U+jQsIe1+d7CVSojHMBcfT+d9K+jClqYylhmpdMfkWCe6xag2qqZSiVuJ0B37yJfIiBau5mfn85/2BNnTo0nHXhmW2awfojAAG35NYKIwITt1JXudmmJcJff8cuil2QBrUGumI3FwAFL7ktTpNa/mzZqIekM9EHZcZ9scRmG70E5+33MUfW70yzVvo0pGr1hHrvssKUgUnw9sjhhbxCAEsNmszUCChtPg95hAhi3c+ZlvraxCog6mMroIAA4GPN72Qb2ONK0lOpSloPZHjg8AZjzxJsSLg4RJW9AnfGP/aqqkYwhdAPn7nXWab+CZ1rX8tknfOiOdf+XXKA9Km0e5MO/hUJewnqL5FEuJJCUSt0559iZ8lZR8NJHi6MjgFSdnKtR6XTdOnrisWoTBYnrF3vuTIizmMxCD5y8wTZS0Jw8COYEUKSpO7949b6MOupyzUPF0yKCf1//RMEVkMy1L0NZVj4iKrqd1rb7caD4= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ca18fcf-6203-428c-57ae-08d817513a17 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2020 08:41:30.9652 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bz3Yuzp3lhZucTVj/cRk0AfvtaIhX96XP9BUMK/4PYGr/6LnSPfqcEs+rYg5/Ip7syF70xJNkl+GL+Qgwdyuxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3618 Subject: [dpdk-dev] [PATCH 3/3] net/mlx5: add new devarg for LACP packets control X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The new devarg will control the steering of the lacp traffic. When setting dv_lacp_by_user = 0 the lacp traffic will be steered to kernel and managed there. When setting dv_lacp_by_user = 1 the lacp traffic will not be steered and the user will need to manage it. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- doc/guides/nics/mlx5.rst | 10 ++++++++++ doc/guides/rel_notes/release_20_08.rst | 1 + drivers/net/mlx5/mlx5.c | 6 ++++++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/mlx5_trigger.c | 9 +++++++++ 5 files changed, 28 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 0ff3c53..b51aa67 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -796,6 +796,16 @@ Driver options Enabled by default if supported. +- ``lacp_by_user`` parameter [int] + + A nonzero value enables the control of LACP traffic by the user application. + When a bond exists in the driver, by default it should be managed by the + kernel and therefore LACP traffic should be steered to the kernel. + If this devarg is set to 1 it will allow the user to manage the bond by + itself and not steer LACP traffic to the kernel. + + Disabled by default (set to 0). + - ``mr_ext_memseg_en`` parameter [int] A nonzero value enables extending memseg when registering DMA memory. If diff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst index cc39984..f03762b 100644 --- a/doc/guides/rel_notes/release_20_08.rst +++ b/doc/guides/rel_notes/release_20_08.rst @@ -67,6 +67,7 @@ New Features Updated Mellanox mlx5 driver with new features and improvements, including: * Added new PMD devarg ``reclaim_mem_mode``. + * Added new devarg ``lacp_by_user``. * **Added vDPA device APIs to query virtio queue statistics.** diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index ddbe29d..07c6add 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -140,6 +140,9 @@ /* Enable extensive flow metadata support. */ #define MLX5_DV_XMETA_EN "dv_xmeta_en" +/* Device parameter to let the user manage the lacp traffic of bonded device */ +#define MLX5_LACP_BY_USER "lacp_by_user" + /* Activate Netlink support in VF mode. */ #define MLX5_VF_NL_EN "vf_nl_en" @@ -1352,6 +1355,8 @@ struct mlx5_dev_ctx_shared * return -rte_errno; } config->dv_xmeta_en = tmp; + } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { + config->lacp_by_user = !!tmp; } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { config->mr_ext_memseg_en = !!tmp; } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { @@ -1419,6 +1424,7 @@ struct mlx5_dev_ctx_shared * MLX5_DV_ESW_EN, MLX5_DV_FLOW_EN, MLX5_DV_XMETA_EN, + MLX5_LACP_BY_USER, MLX5_MR_EXT_MEMSEG_EN, MLX5_REPRESENTOR, MLX5_MAX_DUMP_FILES_NUM, diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 93bde5a..46e66eb 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -210,6 +210,8 @@ struct mlx5_dev_config { unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ unsigned int dv_flow_en:1; /* Enable DV flow. */ unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ + unsigned int lacp_by_user:1; + /* Enable user to manage LACP traffic. */ unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ unsigned int devx:1; /* Whether devx interface is available or not. */ unsigned int dest_tir:1; /* Whether advanced DR API is available. */ diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index c7c2ee6..ef74609 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -464,6 +464,15 @@ " configured - only Eswitch group 0 flows are" " supported.", dev->data->port_id); } + if (!priv->config.lacp_by_user && priv->pf_bond >= 0) { + ret = mlx5_flow_lacp_miss(dev); + if (ret) + DRV_LOG(INFO, "port %u LACP rule cannot be created - " + "forward LACP to kernel.", dev->data->port_id); + else + DRV_LOG(INFO, "LACP traffic will be missed in port %u." + , dev->data->port_id); + } if (priv->isolated) return 0; if (dev->data->promiscuous) {