From patchwork Wed Jun 17 05:43:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Ting" X-Patchwork-Id: 71648 X-Patchwork-Delegate: cristian.dumitrescu@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B62F9A04A5; Wed, 17 Jun 2020 07:44:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 98FB11BFE4; Wed, 17 Jun 2020 07:44:07 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id C073B1BFD1; Wed, 17 Jun 2020 07:44:05 +0200 (CEST) IronPort-SDR: RZaV6NDrUDRE0LJ06a7FQPC6SotMZZwh0qcxAMRD3JXDzjBydJlh7DtoylYUpRo+Ecbg2fWV71 UEzU1o27rz+Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2020 22:44:04 -0700 IronPort-SDR: 8GKli4bJOdHY2DseqpcsHR/eCLFPNb2NosrbMBvGUiHzF48vVC95yYd1eCuDE6JPvcg7OAw0jp cJxpziBqGrzw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,521,1583222400"; d="scan'208";a="383090463" Received: from dpdk-xuting-main.sh.intel.com ([10.67.117.84]) by fmsmga001.fm.intel.com with ESMTP; 16 Jun 2020 22:44:03 -0700 From: Ting Xu To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com, stable@dpdk.org Date: Wed, 17 Jun 2020 13:43:55 +0800 Message-Id: <20200617054355.7895-1-ting.xu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200616162705.83575-1-ting.xu@intel.com> References: <20200616162705.83575-1-ting.xu@intel.com> Subject: [dpdk-dev] [PATCH v2] lib/table: fix cache alignment issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When create softnic hash table with 16 keys, it failed on 32bit environment because of the structure rte_bucket_4_16 alignment issue. Add __rte_cache_aligned to ensure correct cache align. Fixes: 8aa327214c ("table: hash") Cc: stable@dpdk.org Signed-off-by: Ting Xu Tested-by: junx.w.zhou@intel.com Signed-off-by: Ting Xu --- v1->v2: Correct patch time --- lib/librte_table/rte_table_hash_key16.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c index 2cca1c924..5e1665c15 100644 --- a/lib/librte_table/rte_table_hash_key16.c +++ b/lib/librte_table/rte_table_hash_key16.c @@ -44,7 +44,7 @@ struct rte_bucket_4_16 { uint64_t key[4][2]; /* Cache line 2 */ - uint8_t data[0]; + uint8_t data[0] __rte_cache_aligned; }; struct rte_table_hash {