From patchwork Wed Aug 7 14:37:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57527 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 269084C80; Wed, 7 Aug 2019 16:38:08 +0200 (CEST) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by dpdk.org (Postfix) with ESMTP id 9D9AB2BD3 for ; Wed, 7 Aug 2019 16:37:55 +0200 (CEST) Received: by mail-wr1-f65.google.com with SMTP id q12so1367841wrj.12 for ; Wed, 07 Aug 2019 07:37:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=+dQK5r3hE/LlmUpr0euGBUpPqnR9PVPnHXAgKqYV2IU=; b=Wrv9UcHYljPUM4Y2PYy0KkVi8Q3vTO3ZZk7VSU9uGrXCtti8vSd5rNQjt+DYdPTi9u e6ptiinLqVkDXM7iMsaett4HUOqt03+oZ2A+x1lR50PbwmEscF3GSVKeEOhDMgfAvrZq 403W6vRQci+61CiP9b2WF+EzgagHAR+IA722zMP4esoaNbDGPBWMVwfk2l8ljKVTpQKI 2Gc001u0RPAJktnYOIhTKO1zcMBun7XCYzvfsl3chciMUdR/s80DiWKm4mooLpniJLvH B7C3/8+CnAKgGPXaA2F2Czcq1iZvmtMV6jC4jUwUiHdxO0Un1u/nU+r7Wc0ZIi7b4reE 82/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=+dQK5r3hE/LlmUpr0euGBUpPqnR9PVPnHXAgKqYV2IU=; b=JHRxT4x3BC6KV5b1U4VGmT34FUFKO795DBBzl+XJDw1lfgoXj4erxdazuw2ED2ICFR yuTVwrTbtU2NOj+e0triR3pC3Z0q5RnRqiumYSNRThCALtAkSLZDHDrbl8BSes3rNPIB mMcXGWOzHu+WPG5eN4Qy0jONlfYA/G/9bJIV0vg7QfpJn7jo6DBDl92/UFhNI6eBbdy+ pRwlSJStfb5qCVxPIX+uaOhPFhy0zCqqN7kVNjmg0Ua4ImVttn6OTGr/dkNKZ5T6KIy9 CaWm8eoL+pRRO+L3FxwI/b6j1zJHuHKgoLf9aU/iDe2BFZcjYn/IEY9wOoXXPT/WlPcQ 1Y1A== X-Gm-Message-State: APjAAAWx11DajEBbmLfFCPkov7LCLavyDZcgtUVU/xaSqQMZ6Scryu6l EfM0OOXEXGDWFLPnXJotuzXG31x8/A== X-Google-Smtp-Source: APXvYqxp2O3CFzgjPt3O9/ZEN6XKIB60XwVWBxZCcYodXiJnkq8nrGDv6znpeFuNSYGfQn+Ul8ZbaQ== X-Received: by 2002:adf:de8e:: with SMTP id w14mr11302047wrl.79.1565188675102; Wed, 07 Aug 2019 07:37:55 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id 2sm133441211wrn.29.2019.08.07.07.37.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 07:37:54 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 16:37:23 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 04/12] net/e1000: fix Tx descriptor status api (em) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: b9082317cab3 ("net/e1000: implement descriptor status API (em)") Cc: stable at dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/em_rxtx.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c index 5925e490641b..3061998c7768 100644 --- a/drivers/net/e1000/em_rxtx.c +++ b/drivers/net/e1000/em_rxtx.c @@ -152,6 +152,7 @@ struct em_tx_queue { uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */ volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ + volatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t tx_tail; /**< Current value of TDT register. */ /**< Start freeing TX buffers if there are less free descriptors than @@ -1304,6 +1305,7 @@ eth_em_tx_queue_setup(struct rte_eth_dev *dev, txq->port_id = dev->data->port_id; txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx)); + txq->tdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDH(queue_idx)); txq->tx_ring_phys_addr = tz->iova; txq->tx_ring = (struct e1000_data_desc *) tz->addr; @@ -1557,22 +1559,33 @@ eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct em_tx_queue *txq = tx_queue; volatile uint8_t *status; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = e1000_read_addr(txq->tdh_reg_addr); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].upper.fields.status; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].upper.fields.status; if (*status & E1000_TXD_STAT_DD) return RTE_ETH_TX_DESC_DONE;