From patchwork Wed Aug 7 14:37:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57529 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AC0164CAF; Wed, 7 Aug 2019 16:38:13 +0200 (CEST) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by dpdk.org (Postfix) with ESMTP id A4E252C18 for ; Wed, 7 Aug 2019 16:37:57 +0200 (CEST) Received: by mail-wr1-f68.google.com with SMTP id k2so5781606wrq.2 for ; Wed, 07 Aug 2019 07:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=DiNaj7bCpueaIXVSQoi3gGNIfDeDl3LZhYADJ5kq8W8=; b=aW21NVj2ICeC5Ih1MGmCGFjsDBEhLacPjmkBY8IJfofu39Hun9dOnooZSSKSqDX/Y7 kSRIyIGDLIDQ8mPLVN6btS/5+7XPZBO9zANNFRclRtJSZOQz7S8WsnBF+xMItgVbEA8h ve0rH9mXWzymusHIoafjtDwWhfAtb19418FP+ZKOeFtcBNdmCGGxhJmR2edxb0kSPz1d o5Cf57lf52KP36EjrVdSXf99pFyQOP9rEmkblZnUsCX4613gYl2jsDStqZ1EcVu4ZH60 M8S7C/oAoRV/0uhbP1afWgQie9hoCG6dfd2hxcOo4bR2VnXRHhbxDQ7b3zt1lkgkGNSj jOTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=DiNaj7bCpueaIXVSQoi3gGNIfDeDl3LZhYADJ5kq8W8=; b=eUmzDo9l9kOfZ3/GWvqTeqbon4QqJ7568d+bmFpDVqxeWzNTx0CZEmMQkoCMa91/rd ZyCi6LzftUITsuwMdcx14vtdWDuspprp2e7e/nVyV3af57tHvo2ueRmU5rHKoHn6QleH 9qrkPCQxjrdvYuTxX5vFHnpc7cba1Fj0uU5Z48r/IbwxSbYDZN2wRzA+ilJEmehbc5Q7 lOf0i2NJmtOpxUW+2Y/151S2Vr5HZEEpgezQcUv4b1RuEmYeYUwe+XTAG2zPLl4IxG3V y8T+hstz9GCtgcT6/YQAwSLJlktcFAFuHLFO0QSNGHFbUj3LfAzaWMm3deT3KrChLzoz fYrw== X-Gm-Message-State: APjAAAVscQwabx8+iM3GLDvJJi15nVqe+bsJ9wa4G3Z7hNyro9AVK0Jl 54B1VANbencZdqI82gfQDw9WMqz/+g== X-Google-Smtp-Source: APXvYqzGErF4ySbiLrW6p4NjfQXRXYbFK+IRe3oqw4OhpG7LT9W4+qSYYvZB+LnO2Ypi3Tryq1E4Iw== X-Received: by 2002:a5d:4804:: with SMTP id l4mr194917wrq.111.1565188677167; Wed, 07 Aug 2019 07:37:57 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id 2sm133441211wrn.29.2019.08.07.07.37.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 07:37:56 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 16:37:25 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 06/12] net/i40e: fix Tx descriptor status api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: a9dd9af6f38e ("net/i40e: implement descriptor status API") Cc: stable at dpdk.org Signed-off-by: Olivier Matz --- drivers/net/i40e/i40e_rxtx.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 692c3bab4b5f..4fbbc097ed4f 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -2031,22 +2031,39 @@ i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) struct i40e_tx_queue *txq = tx_queue; volatile uint64_t *status; uint64_t mask, expect; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; + + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = I40E_READ_REG(I40E_VSI_TO_HW(txq->vsi), + I40E_QTX_HEAD(txq->reg_idx)); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].cmd_type_offset_bsz; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + + /* In full featured mode, RS bit is only set in the last descriptor */ + /* of a multisegments packet */ + if (!((txq->offloads == 0) && + (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST))) + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].cmd_type_offset_bsz; mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK); expect = rte_cpu_to_le_64( I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);