From patchwork Fri Sep 6 21:52:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 58911 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4E7931F4D3; Sat, 7 Sep 2019 00:00:13 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 2DB561F4CE for ; Sat, 7 Sep 2019 00:00:10 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id x86M06Of004220; Fri, 6 Sep 2019 15:00:07 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Cc: nirranjan@chelsio.com Date: Sat, 7 Sep 2019 03:22:31 +0530 Message-Id: X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 10/12] net/cxgbe: fetch max Tx coalesce limit from firmware X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Query firmware for max number of packets that can be coalesced by Tx. Signed-off-by: Rahul Lakkireddy --- doc/guides/nics/cxgbe.rst | 18 ++++++------ drivers/net/cxgbe/base/common.h | 1 + drivers/net/cxgbe/base/t4fw_interface.h | 3 +- drivers/net/cxgbe/cxgbe_main.c | 39 ++++++++++++------------- drivers/net/cxgbe/cxgbe_pfvf.h | 10 +++++++ drivers/net/cxgbe/cxgbevf_main.c | 12 ++++++-- drivers/net/cxgbe/sge.c | 4 +-- 7 files changed, 52 insertions(+), 35 deletions(-) diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst index f15e0b90a..a7b333dca 100644 --- a/doc/guides/nics/cxgbe.rst +++ b/doc/guides/nics/cxgbe.rst @@ -70,7 +70,7 @@ in :ref:`t5-nics` and :ref:`t6-nics`. Prerequisites ------------- -- Requires firmware version **1.17.14.0** and higher. Visit +- Requires firmware version **1.23.4.0** and higher. Visit `Chelsio Download Center `_ to get latest firmware bundled with the latest Chelsio Unified Wire package. @@ -215,7 +215,7 @@ Unified Wire package for Linux operating system are as follows: .. code-block:: console - firmware-version: 1.17.14.0, TP 0.1.4.9 + firmware-version: 1.23.4.0, TP 0.1.23.2 Running testpmd ~~~~~~~~~~~~~~~ @@ -273,7 +273,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system. EAL: PCI memory mapped at 0x7fd7c0200000 EAL: PCI memory mapped at 0x7fd77cdfd000 EAL: PCI memory mapped at 0x7fd7c10b7000 - PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9 + PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2 PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter Interactive-mode selected Configuring Port 0 (socket 0) @@ -379,16 +379,16 @@ virtual functions. [...] EAL: PCI device 0000:02:01.0 on NUMA socket 0 EAL: probe driver: 1425:5803 net_cxgbevf - PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0 - PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9 + PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0 + PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2 PMD: rte_cxgbe_pmd: Chelsio rev 0 PMD: rte_cxgbe_pmd: No bootstrap loaded PMD: rte_cxgbe_pmd: No Expansion ROM loaded PMD: rte_cxgbe_pmd: 0000:02:01.0 Chelsio rev 0 1G/10GBASE-SFP EAL: PCI device 0000:02:01.1 on NUMA socket 0 EAL: probe driver: 1425:5803 net_cxgbevf - PMD: rte_cxgbe_pmd: Firmware version: 1.17.14.0 - PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.4.9 + PMD: rte_cxgbe_pmd: Firmware version: 1.23.4.0 + PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2 PMD: rte_cxgbe_pmd: Chelsio rev 0 PMD: rte_cxgbe_pmd: No bootstrap loaded PMD: rte_cxgbe_pmd: No Expansion ROM loaded @@ -465,7 +465,7 @@ Unified Wire package for FreeBSD operating system are as follows: .. code-block:: console - dev.t5nex.0.firmware_version: 1.17.14.0 + dev.t5nex.0.firmware_version: 1.23.4.0 Running testpmd ~~~~~~~~~~~~~~~ @@ -583,7 +583,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system. EAL: PCI memory mapped at 0x8007ec000 EAL: PCI memory mapped at 0x842800000 EAL: PCI memory mapped at 0x80086c000 - PMD: rte_cxgbe_pmd: fw: 1.17.14.0, TP: 0.1.4.9 + PMD: rte_cxgbe_pmd: fw: 1.23.4.0, TP: 0.1.23.2 PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter Interactive-mode selected Configuring Port 0 (socket 0) diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index 973d4d7dd..6047642c5 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -272,6 +272,7 @@ struct adapter_params { bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ u8 fw_caps_support; /* 32-bit Port Capabilities */ u8 filter2_wr_support; /* FW support for FILTER2_WR */ + u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ }; /* Firmware Port Capabilities types. diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h index 06d3ef3a6..e992d196d 100644 --- a/drivers/net/cxgbe/base/t4fw_interface.h +++ b/drivers/net/cxgbe/base/t4fw_interface.h @@ -692,7 +692,8 @@ enum fw_params_param_pfvf { FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, - FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A + FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, + FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, }; /* diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index 23b74c754..4701518a6 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -37,6 +37,7 @@ #include "base/t4_regs.h" #include "base/t4_msg.h" #include "cxgbe.h" +#include "cxgbe_pfvf.h" #include "clip_tbl.h" #include "l2t.h" #include "mps_tcam.h" @@ -1162,20 +1163,10 @@ static int adap_init0(struct adapter *adap) /* * Grab some of our basic fundamental operating parameters. */ -#define FW_PARAM_DEV(param) \ - (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ - V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) - -#define FW_PARAM_PFVF(param) \ - (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ - V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ - V_FW_PARAMS_PARAM_Y(0) | \ - V_FW_PARAMS_PARAM_Z(0)) - - params[0] = FW_PARAM_PFVF(L2T_START); - params[1] = FW_PARAM_PFVF(L2T_END); - params[2] = FW_PARAM_PFVF(FILTER_START); - params[3] = FW_PARAM_PFVF(FILTER_END); + params[0] = CXGBE_FW_PARAM_PFVF(L2T_START); + params[1] = CXGBE_FW_PARAM_PFVF(L2T_END); + params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START); + params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val); if (ret < 0) goto bye; @@ -1184,8 +1175,8 @@ static int adap_init0(struct adapter *adap) adap->tids.ftid_base = val[2]; adap->tids.nftids = val[3] - val[2] + 1; - params[0] = FW_PARAM_PFVF(CLIP_START); - params[1] = FW_PARAM_PFVF(CLIP_END); + params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START); + params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); if (ret < 0) goto bye; @@ -1215,14 +1206,14 @@ static int adap_init0(struct adapter *adap) if (is_t4(adap->params.chip)) { adap->params.filter2_wr_support = 0; } else { - params[0] = FW_PARAM_DEV(FILTER2_WR); + params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); } /* query tid-related parameters */ - params[0] = FW_PARAM_DEV(NTID); + params[0] = CXGBE_FW_PARAM_DEV(NTID); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); if (ret < 0) @@ -1235,7 +1226,7 @@ static int adap_init0(struct adapter *adap) * firmware won't understand this and we'll just get * unencapsulated messages ... */ - params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); + params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); val[0] = 1; (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); @@ -1248,12 +1239,20 @@ static int adap_init0(struct adapter *adap) if (is_t4(adap->params.chip)) { adap->params.ulptx_memwrite_dsgl = false; } else { - params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); + params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); } + /* Query for max number of packets that can be coalesced for Tx */ + params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); + ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val); + if (!ret && val[0] > 0) + adap->params.max_tx_coalesce_num = val[0]; + else + adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM; + /* * The MTU/MSS Table is initialized by now, so load their values. If * we're initializing the adapter, then we'll make any modifications diff --git a/drivers/net/cxgbe/cxgbe_pfvf.h b/drivers/net/cxgbe/cxgbe_pfvf.h index 03145cea6..098dbe8f6 100644 --- a/drivers/net/cxgbe/cxgbe_pfvf.h +++ b/drivers/net/cxgbe/cxgbe_pfvf.h @@ -6,6 +6,16 @@ #ifndef _CXGBE_PFVF_H_ #define _CXGBE_PFVF_H_ +#define CXGBE_FW_PARAM_DEV(param) \ + (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) + +#define CXGBE_FW_PARAM_PFVF(param) \ + (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ + V_FW_PARAMS_PARAM_Y(0) | \ + V_FW_PARAMS_PARAM_Z(0)) + void cxgbe_dev_rx_queue_release(void *q); void cxgbe_dev_tx_queue_release(void *q); void cxgbe_dev_stop(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/cxgbe/cxgbevf_main.c b/drivers/net/cxgbe/cxgbevf_main.c index 82f40f358..66fb92375 100644 --- a/drivers/net/cxgbe/cxgbevf_main.c +++ b/drivers/net/cxgbe/cxgbevf_main.c @@ -11,6 +11,7 @@ #include "base/t4_regs.h" #include "base/t4_msg.h" #include "cxgbe.h" +#include "cxgbe_pfvf.h" #include "mps_tcam.h" /* @@ -122,11 +123,18 @@ static int adap_init0vf(struct adapter *adapter) * firmware won't understand this and we'll just get * unencapsulated messages ... */ - param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | - V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP); + param = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP); val = 1; t4vf_set_params(adapter, 1, ¶m, &val); + /* Query for max number of packets that can be coalesced for Tx */ + param = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR); + err = t4vf_query_params(adapter, 1, ¶m, &val); + if (!err && val > 0) + adapter->params.max_tx_coalesce_num = val; + else + adapter->params.max_tx_coalesce_num = ETH_COALESCE_VF_PKT_NUM; + /* * Grab our Virtual Interface resource allocation, extract the * features that we're interested in and do a bit of sanity testing on diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c index 0df870a41..aba85a209 100644 --- a/drivers/net/cxgbe/sge.c +++ b/drivers/net/cxgbe/sge.c @@ -1004,8 +1004,6 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq, struct cpl_tx_pkt_core *cpl; struct tx_sw_desc *sd; unsigned int idx = q->coalesce.idx, len = mbuf->pkt_len; - unsigned int max_coal_pkt_num = is_pf4(adap) ? ETH_COALESCE_PKT_NUM : - ETH_COALESCE_VF_PKT_NUM; if (q->coalesce.type == 0) { mc = (struct ulp_txpkt *)q->coalesce.ptr; @@ -1083,7 +1081,7 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq, * for coalescing the next Tx burst and send the packets now. */ q->coalesce.idx++; - if (q->coalesce.idx == max_coal_pkt_num || + if (q->coalesce.idx == adap->params.max_tx_coalesce_num || (adap->devargs.tx_mode_latency && q->coalesce.idx >= nb_pkts)) ship_tx_pkt_coalesce_wr(adap, txq);