From patchwork Sun Dec 20 22:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 85569 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BEDDAA09FD; Mon, 21 Dec 2020 00:04:21 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CDF8ECBA8; Mon, 21 Dec 2020 00:04:06 +0100 (CET) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 34402CA30 for ; Mon, 21 Dec 2020 00:04:04 +0100 (CET) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id 0BKN40hF011885; Sun, 20 Dec 2020 15:04:01 -0800 From: Rahul Lakkireddy To: dev@dpdk.org Cc: kaara.satwik@chelsio.com Date: Mon, 21 Dec 2020 04:17:40 +0530 Message-Id: X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 1/3] net/cxgbe: remove legacy 16-bit link capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Karra Satwik Remove legacy 16-bit link capabilities and always request for the 32-bit link capabilities from firmware. Signed-off-by: Karra Satwik Signed-off-by: Rahul Lakkireddy --- doc/guides/nics/cxgbe.rst | 14 +- drivers/net/cxgbe/base/common.h | 9 - drivers/net/cxgbe/base/t4_hw.c | 233 +++++------------------- drivers/net/cxgbe/base/t4fw_interface.h | 70 +------ drivers/net/cxgbe/base/t4vf_hw.c | 79 +++----- 5 files changed, 78 insertions(+), 327 deletions(-) diff --git a/doc/guides/nics/cxgbe.rst b/doc/guides/nics/cxgbe.rst index f01cd6560..4b9913669 100644 --- a/doc/guides/nics/cxgbe.rst +++ b/doc/guides/nics/cxgbe.rst @@ -70,7 +70,7 @@ in :ref:`t5-nics` and :ref:`t6-nics`. Prerequisites ------------- -- Requires firmware version **1.24.11.0** and higher. Visit +- Requires firmware version **1.24.17.0** and higher. Visit `Chelsio Download Center `_ to get latest firmware bundled with the latest Chelsio Unified Wire package. @@ -404,7 +404,7 @@ Unified Wire package for Linux operating system are as follows: .. code-block:: console - firmware-version: 1.24.11.0, TP 0.1.23.2 + firmware-version: 1.24.17.0, TP 0.1.23.2 Running testpmd ~~~~~~~~~~~~~~~ @@ -462,7 +462,7 @@ devices managed by librte_net_cxgbe in Linux operating system. EAL: PCI memory mapped at 0x7fd7c0200000 EAL: PCI memory mapped at 0x7fd77cdfd000 EAL: PCI memory mapped at 0x7fd7c10b7000 - PMD: rte_cxgbe_pmd: fw: 1.24.11.0, TP: 0.1.23.2 + PMD: rte_cxgbe_pmd: fw: 1.24.17.0, TP: 0.1.23.2 PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter Interactive-mode selected Configuring Port 0 (socket 0) @@ -568,7 +568,7 @@ virtual functions. [...] EAL: PCI device 0000:02:01.0 on NUMA socket 0 EAL: probe driver: 1425:5803 net_cxgbevf - PMD: rte_cxgbe_pmd: Firmware version: 1.24.11.0 + PMD: rte_cxgbe_pmd: Firmware version: 1.24.17.0 PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2 PMD: rte_cxgbe_pmd: Chelsio rev 0 PMD: rte_cxgbe_pmd: No bootstrap loaded @@ -576,7 +576,7 @@ virtual functions. PMD: rte_cxgbe_pmd: 0000:02:01.0 Chelsio rev 0 1G/10GBASE-SFP EAL: PCI device 0000:02:01.1 on NUMA socket 0 EAL: probe driver: 1425:5803 net_cxgbevf - PMD: rte_cxgbe_pmd: Firmware version: 1.24.11.0 + PMD: rte_cxgbe_pmd: Firmware version: 1.24.17.0 PMD: rte_cxgbe_pmd: TP Microcode version: 0.1.23.2 PMD: rte_cxgbe_pmd: Chelsio rev 0 PMD: rte_cxgbe_pmd: No bootstrap loaded @@ -654,7 +654,7 @@ Unified Wire package for FreeBSD operating system are as follows: .. code-block:: console - dev.t5nex.0.firmware_version: 1.24.11.0 + dev.t5nex.0.firmware_version: 1.24.17.0 Running testpmd ~~~~~~~~~~~~~~~ @@ -772,7 +772,7 @@ devices managed by librte_net_cxgbe in FreeBSD operating system. EAL: PCI memory mapped at 0x8007ec000 EAL: PCI memory mapped at 0x842800000 EAL: PCI memory mapped at 0x80086c000 - PMD: rte_cxgbe_pmd: fw: 1.24.11.0, TP: 0.1.23.2 + PMD: rte_cxgbe_pmd: fw: 1.24.17.0, TP: 0.1.23.2 PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter Interactive-mode selected Configuring Port 0 (socket 0) diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index 8fe8e2a36..86f3dc80b 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -274,7 +274,6 @@ struct adapter_params { struct arch_specific_params arch; /* chip specific params */ bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ - u8 fw_caps_support; /* 32-bit Port Capabilities */ u8 filter2_wr_support; /* FW support for FILTER2_WR */ u32 viid_smt_extn_support:1; /* FW returns vin and smt index */ u32 max_tx_coalesce_num; /* Max # of Tx packets that can be coalesced */ @@ -282,15 +281,8 @@ struct adapter_params { /* Firmware Port Capabilities types. */ -typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ -enum fw_caps { - FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ - FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ - FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ -}; - struct link_config { fw_port_cap32_t pcaps; /* link capabilities */ fw_port_cap32_t acaps; /* advertised capabilities */ @@ -552,5 +544,4 @@ static inline int t4_memory_rw(struct adapter *adap, int win, { return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir); } -fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16); #endif /* __CHELSIO_COMMON_H */ diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index 9217956b4..44227740c 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -2811,81 +2811,6 @@ void t4_dump_version_info(struct adapter *adapter) #define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \ FW_PORT_CAP32_ANEG) -/** - * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits - * @caps16: a 16-bit Port Capabilities value - * - * Returns the equivalent 32-bit Port Capabilities value. - */ -fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16) -{ - fw_port_cap32_t caps32 = 0; - -#define CAP16_TO_CAP32(__cap) \ - do { \ - if (caps16 & FW_PORT_CAP_##__cap) \ - caps32 |= FW_PORT_CAP32_##__cap; \ - } while (0) - - CAP16_TO_CAP32(SPEED_100M); - CAP16_TO_CAP32(SPEED_1G); - CAP16_TO_CAP32(SPEED_25G); - CAP16_TO_CAP32(SPEED_10G); - CAP16_TO_CAP32(SPEED_40G); - CAP16_TO_CAP32(SPEED_100G); - CAP16_TO_CAP32(FC_RX); - CAP16_TO_CAP32(FC_TX); - CAP16_TO_CAP32(ANEG); - CAP16_TO_CAP32(MDIX); - CAP16_TO_CAP32(MDIAUTO); - CAP16_TO_CAP32(FEC_RS); - CAP16_TO_CAP32(FEC_BASER_RS); - CAP16_TO_CAP32(802_3_PAUSE); - CAP16_TO_CAP32(802_3_ASM_DIR); - -#undef CAP16_TO_CAP32 - - return caps32; -} - -/** - * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits - * @caps32: a 32-bit Port Capabilities value - * - * Returns the equivalent 16-bit Port Capabilities value. Note that - * not all 32-bit Port Capabilities can be represented in the 16-bit - * Port Capabilities and some fields/values may not make it. - */ -static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32) -{ - fw_port_cap16_t caps16 = 0; - -#define CAP32_TO_CAP16(__cap) \ - do { \ - if (caps32 & FW_PORT_CAP32_##__cap) \ - caps16 |= FW_PORT_CAP_##__cap; \ - } while (0) - - CAP32_TO_CAP16(SPEED_100M); - CAP32_TO_CAP16(SPEED_1G); - CAP32_TO_CAP16(SPEED_10G); - CAP32_TO_CAP16(SPEED_25G); - CAP32_TO_CAP16(SPEED_40G); - CAP32_TO_CAP16(SPEED_100G); - CAP32_TO_CAP16(FC_RX); - CAP32_TO_CAP16(FC_TX); - CAP32_TO_CAP16(802_3_PAUSE); - CAP32_TO_CAP16(802_3_ASM_DIR); - CAP32_TO_CAP16(ANEG); - CAP32_TO_CAP16(MDIX); - CAP32_TO_CAP16(MDIAUTO); - CAP32_TO_CAP16(FEC_RS); - CAP32_TO_CAP16(FEC_BASER_RS); - -#undef CAP32_TO_CAP16 - - return caps16; -} /* Translate Firmware Pause specification to Common Code */ static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause) @@ -2957,7 +2882,6 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, struct link_config *lc) { unsigned int fw_mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); - unsigned int fw_caps = adap->params.fw_caps_support; fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap; struct fw_port_cmd cmd; @@ -2999,15 +2923,10 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, F_FW_CMD_REQUEST | F_FW_CMD_EXEC | V_FW_PORT_CMD_PORTID(port)); cmd.action_to_len16 = - cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ? - FW_PORT_ACTION_L1_CFG : - FW_PORT_ACTION_L1_CFG32) | + cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | FW_LEN16(cmd)); - if (fw_caps == FW_CAPS16) - cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); - else - cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap); + cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap); return t4_wr_mbox(adap, mbox, &cmd, sizeof(cmd), NULL); } @@ -4539,73 +4458,31 @@ static unsigned int fwcap_to_speed(fw_port_cap32_t caps) static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl) { const struct fw_port_cmd *cmd = (const void *)rpl; - int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16)); - fw_port_cap32_t pcaps, acaps, linkattr; + u8 link_ok, link_down_rc, mod_type, port_type; + u32 action, pcaps, acaps, linkattr, lstatus; struct link_config *lc = &pi->link_cfg; struct adapter *adapter = pi->adapter; - enum fw_port_module_type mod_type; - enum fw_port_type port_type; unsigned int speed, fc, fec; - int link_ok, linkdnrc; /* Extract the various fields from the Port Information message. */ - switch (action) { - case FW_PORT_ACTION_GET_PORT_INFO: { - u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype); - - link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0; - linkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus); - port_type = G_FW_PORT_CMD_PTYPE(lstatus); - mod_type = G_FW_PORT_CMD_MODTYPE(lstatus); - pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap)); - acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap)); - - /* Unfortunately the format of the Link Status in the old - * 16-bit Port Information message isn't the same as the - * 16-bit Port Capabilities bitfield used everywhere else ... - */ - linkattr = 0; - if (lstatus & F_FW_PORT_CMD_RXPAUSE) - linkattr |= FW_PORT_CAP32_FC_RX; - if (lstatus & F_FW_PORT_CMD_TXPAUSE) - linkattr |= FW_PORT_CAP32_FC_TX; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) - linkattr |= FW_PORT_CAP32_SPEED_100M; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) - linkattr |= FW_PORT_CAP32_SPEED_1G; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) - linkattr |= FW_PORT_CAP32_SPEED_10G; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) - linkattr |= FW_PORT_CAP32_SPEED_25G; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) - linkattr |= FW_PORT_CAP32_SPEED_40G; - if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) - linkattr |= FW_PORT_CAP32_SPEED_100G; - - break; - } - - case FW_PORT_ACTION_GET_PORT_INFO32: { - u32 lstatus32 = - be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32); - - link_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0; - linkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32); - port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32); - mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32); - pcaps = be32_to_cpu(cmd->u.info32.pcaps32); - acaps = be32_to_cpu(cmd->u.info32.acaps32); - linkattr = be32_to_cpu(cmd->u.info32.linkattr32); - break; - } - - default: + action = be32_to_cpu(cmd->action_to_len16); + if (G_FW_PORT_CMD_ACTION(action) != FW_PORT_ACTION_GET_PORT_INFO32) { dev_warn(adapter, "Handle Port Information: Bad Command/Action %#x\n", - be32_to_cpu(cmd->action_to_len16)); + action); return; } + lstatus = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32); + link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS32) ? 1 : 0; + link_down_rc = G_FW_PORT_CMD_LINKDNRC32(lstatus); + port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus); + mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus); + + pcaps = be32_to_cpu(cmd->u.info32.pcaps32); + acaps = be32_to_cpu(cmd->u.info32.acaps32); + linkattr = be32_to_cpu(cmd->u.info32.linkattr32); + fec = fwcap_to_cc_fec(acaps); fc = fwcap_to_cc_pause(linkattr); @@ -4620,9 +4497,10 @@ static void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl) if (link_ok != lc->link_ok || speed != lc->speed || fc != lc->fc || fec != lc->fec) { /* something changed */ if (!link_ok && lc->link_ok) { - lc->link_down_rc = linkdnrc; + lc->link_down_rc = link_down_rc; dev_warn(adap, "Port %d link down, reason: %s\n", - pi->tx_chan, t4_link_down_rc_str(linkdnrc)); + pi->port_id, + t4_link_down_rc_str(link_down_rc)); } lc->link_ok = link_ok; lc->speed = speed; @@ -4691,9 +4569,7 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) unsigned int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); - if (opcode == FW_PORT_CMD && - (action == FW_PORT_ACTION_GET_PORT_INFO || - action == FW_PORT_ACTION_GET_PORT_INFO32)) { + if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO32) { /* link/module state change message */ int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); struct port_info *pi = NULL; @@ -5395,81 +5271,54 @@ int t4_init_rss_mode(struct adapter *adap, int mbox) int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) { - unsigned int fw_caps = adap->params.fw_caps_support; fw_port_cap32_t pcaps, acaps; enum fw_port_type port_type; struct fw_port_cmd cmd; u8 vivld = 0, vin = 0; int ret, i, j = 0; + u32 param, val; int mdio_addr; - u32 action; u8 addr[6]; + param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_PORT_CAPS32)); + val = 1; + ret = t4_set_params(adap, mbox, pf, vf, 1, ¶m, &val); + if (ret < 0) + return ret; + memset(&cmd, 0, sizeof(cmd)); for_each_port(adap, i) { struct port_info *pi = adap2pinfo(adap, i); unsigned int rss_size = 0; + u32 lstatus32; while ((adap->params.portvec & (1 << j)) == 0) j++; - /* If we haven't yet determined whether we're talking to - * Firmware which knows the new 32-bit Port Capabilities, it's - * time to find out now. This will also tell new Firmware to - * send us Port Status Updates using the new 32-bit Port - * Capabilities version of the Port Information message. - */ - if (fw_caps == FW_CAPS_UNKNOWN) { - u32 param, val, caps; - - caps = FW_PARAMS_PARAM_PFVF_PORT_CAPS32; - param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | - V_FW_PARAMS_PARAM_X(caps)); - val = 1; - ret = t4_set_params(adap, mbox, pf, vf, 1, ¶m, - &val); - fw_caps = ret == 0 ? FW_CAPS32 : FW_CAPS16; - adap->params.fw_caps_support = fw_caps; - } - memset(&cmd, 0, sizeof(cmd)); cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_READ | V_FW_PORT_CMD_PORTID(j)); - action = fw_caps == FW_CAPS16 ? FW_PORT_ACTION_GET_PORT_INFO : - FW_PORT_ACTION_GET_PORT_INFO32; - cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | + val = FW_PORT_ACTION_GET_PORT_INFO32; + cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(val) | FW_LEN16(cmd)); ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd); if (ret) return ret; - /* Extract the various fields from the Port Information message. + /* Extract the various fields from the Port Information + * message. */ - if (fw_caps == FW_CAPS16) { - u32 lstatus = - be32_to_cpu(cmd.u.info.lstatus_to_modtype); - - port_type = G_FW_PORT_CMD_PTYPE(lstatus); - mdio_addr = (lstatus & F_FW_PORT_CMD_MDIOCAP) ? - (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : -1; - pcaps = be16_to_cpu(cmd.u.info.pcap); - acaps = be16_to_cpu(cmd.u.info.acap); - pcaps = fwcaps16_to_caps32(pcaps); - acaps = fwcaps16_to_caps32(acaps); - } else { - u32 lstatus32 = - be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32); - - port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32); - mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ? - (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) : - -1; - pcaps = be32_to_cpu(cmd.u.info32.pcaps32); - acaps = be32_to_cpu(cmd.u.info32.acaps32); - } + lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32); + + port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32); + mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ? + (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) : -1; + pcaps = be32_to_cpu(cmd.u.info32.pcaps32); + acaps = be32_to_cpu(cmd.u.info32.acaps32); ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size, &vivld, &vin); diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h index 109273a39..153141247 100644 --- a/drivers/net/cxgbe/base/t4fw_interface.h +++ b/drivers/net/cxgbe/base/t4fw_interface.h @@ -1598,41 +1598,6 @@ struct fw_vi_stats_cmd { #define S_FW_VI_STATS_CMD_IX 0 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) -/* old 16-bit port capabilities bitmap */ -enum fw_port_cap { - FW_PORT_CAP_SPEED_100M = 0x0001, - FW_PORT_CAP_SPEED_1G = 0x0002, - FW_PORT_CAP_SPEED_25G = 0x0004, - FW_PORT_CAP_SPEED_10G = 0x0008, - FW_PORT_CAP_SPEED_40G = 0x0010, - FW_PORT_CAP_SPEED_100G = 0x0020, - FW_PORT_CAP_FC_RX = 0x0040, - FW_PORT_CAP_FC_TX = 0x0080, - FW_PORT_CAP_ANEG = 0x0100, - FW_PORT_CAP_MDIX = 0x0200, - FW_PORT_CAP_MDIAUTO = 0x0400, - FW_PORT_CAP_FEC_RS = 0x0800, - FW_PORT_CAP_FEC_BASER_RS = 0x1000, - FW_PORT_CAP_FEC_RESERVED = 0x2000, - FW_PORT_CAP_802_3_PAUSE = 0x4000, - FW_PORT_CAP_802_3_ASM_DIR = 0x8000, -}; - -#define S_FW_PORT_CAP_SPEED 0 -#define M_FW_PORT_CAP_SPEED 0x3f -#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) -#define G_FW_PORT_CAP_SPEED(x) \ - (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) - -enum fw_port_mdi { - FW_PORT_CAP_MDI_AUTO, -}; - -#define S_FW_PORT_CAP_MDI 9 -#define M_FW_PORT_CAP_MDI 3 -#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) -#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) - /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ #define FW_PORT_CAP32_SPEED_100M 0x00000001UL #define FW_PORT_CAP32_SPEED_1G 0x00000002UL @@ -1668,8 +1633,6 @@ enum fw_port_mdi32 { (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) enum fw_port_action { - FW_PORT_ACTION_L1_CFG = 0x0001, - FW_PORT_ACTION_GET_PORT_INFO = 0x0003, FW_PORT_ACTION_L1_CFG32 = 0x0009, FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, }; @@ -1814,37 +1777,12 @@ struct fw_port_cmd { (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) -#define S_FW_PORT_CMD_MDIOCAP 21 -#define M_FW_PORT_CMD_MDIOCAP 0x1 -#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) -#define G_FW_PORT_CMD_MDIOCAP(x) \ - (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) -#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) - -#define S_FW_PORT_CMD_MDIOADDR 16 -#define M_FW_PORT_CMD_MDIOADDR 0x1f -#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) -#define G_FW_PORT_CMD_MDIOADDR(x) \ - (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) - #define S_FW_PORT_CMD_PTYPE 8 #define M_FW_PORT_CMD_PTYPE 0x1f #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) #define G_FW_PORT_CMD_PTYPE(x) \ (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) -#define S_FW_PORT_CMD_LINKDNRC 5 -#define M_FW_PORT_CMD_LINKDNRC 0x7 -#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) -#define G_FW_PORT_CMD_LINKDNRC(x) \ - (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) - -#define S_FW_PORT_CMD_MODTYPE 0 -#define M_FW_PORT_CMD_MODTYPE 0x1f -#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) -#define G_FW_PORT_CMD_MODTYPE(x) \ - (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) - #define S_FW_PORT_CMD_LSTATUS32 31 #define M_FW_PORT_CMD_LSTATUS32 0x1 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) @@ -1924,10 +1862,10 @@ enum fw_port_module_type { FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, FW_PORT_MOD_TYPE_LRM = 0x6, - FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, - FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, - FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, - FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE + FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE32 - 3, + FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE32 - 2, + FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE32 - 1, + FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE32 }; /* used by FW and tools may use this to generate VPD */ diff --git a/drivers/net/cxgbe/base/t4vf_hw.c b/drivers/net/cxgbe/base/t4vf_hw.c index 649bacfb2..6454029aa 100644 --- a/drivers/net/cxgbe/base/t4vf_hw.c +++ b/drivers/net/cxgbe/base/t4vf_hw.c @@ -766,35 +766,24 @@ static int t4vf_alloc_vi(struct adapter *adapter, int port_id) int t4vf_port_init(struct adapter *adapter) { - unsigned int fw_caps = adapter->params.fw_caps_support; - struct fw_port_cmd port_cmd, port_rpl; + struct fw_port_cmd port_cmd, port_rpl, rpl; struct fw_vi_cmd vi_cmd, vi_rpl; fw_port_cap32_t pcaps, acaps; enum fw_port_type port_type; + u32 param, val; int mdio_addr; int ret, i; + param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_PORT_CAPS32)); + val = 1; + ret = t4vf_set_params(adapter, 1, ¶m, &val); + if (ret < 0) + return ret; + for_each_port(adapter, i) { struct port_info *p = adap2pinfo(adapter, i); - - /* - * If we haven't yet determined if we're talking to Firmware - * which knows the new 32-bit Port Caps, it's time to find - * out now. This will also tell new Firmware to send us Port - * Status Updates using the new 32-bit Port Capabilities - * version of the Port Information message. - */ - if (fw_caps == FW_CAPS_UNKNOWN) { - u32 param, val; - - param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | - V_FW_PARAMS_PARAM_X - (FW_PARAMS_PARAM_PFVF_PORT_CAPS32)); - val = 1; - ret = t4vf_set_params(adapter, 1, ¶m, &val); - fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16); - adapter->params.fw_caps_support = fw_caps; - } + u32 lstatus32; ret = t4vf_alloc_vi(adapter, p->port_id); if (ret < 0) { @@ -830,15 +819,14 @@ int t4vf_port_init(struct adapter *adapter) return 0; memset(&port_cmd, 0, sizeof(port_cmd)); - port_cmd.op_to_portid = cpu_to_be32 - (V_FW_CMD_OP(FW_PORT_CMD) | F_FW_CMD_REQUEST | - F_FW_CMD_READ | - V_FW_PORT_CMD_PORTID(p->port_id)); - port_cmd.action_to_len16 = cpu_to_be32 - (V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16 ? - FW_PORT_ACTION_GET_PORT_INFO : - FW_PORT_ACTION_GET_PORT_INFO32) | - FW_LEN16(port_cmd)); + port_cmd.op_to_portid = + cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | + F_FW_CMD_REQUEST | F_FW_CMD_READ | + V_FW_PORT_CMD_PORTID(p->port_id)); + val = FW_PORT_ACTION_GET_PORT_INFO32; + port_cmd.action_to_len16 = + cpu_to_be32(V_FW_PORT_CMD_ACTION(val) | + FW_LEN16(port_cmd)); ret = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl); if (ret != FW_SUCCESS) @@ -847,29 +835,14 @@ int t4vf_port_init(struct adapter *adapter) /* * Extract the various fields from the Port Information message. */ - if (fw_caps == FW_CAPS16) { - u32 lstatus = be32_to_cpu - (port_rpl.u.info.lstatus_to_modtype); - - port_type = G_FW_PORT_CMD_PTYPE(lstatus); - mdio_addr = ((lstatus & F_FW_PORT_CMD_MDIOCAP) ? - (int)G_FW_PORT_CMD_MDIOADDR(lstatus) : - -1); - pcaps = fwcaps16_to_caps32 - (be16_to_cpu(port_rpl.u.info.pcap)); - acaps = fwcaps16_to_caps32 - (be16_to_cpu(port_rpl.u.info.acap)); - } else { - u32 lstatus32 = be32_to_cpu - (port_rpl.u.info32.lstatus32_to_cbllen32); - - port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32); - mdio_addr = ((lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ? - (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) : - -1); - pcaps = be32_to_cpu(port_rpl.u.info32.pcaps32); - acaps = be32_to_cpu(port_rpl.u.info32.acaps32); - } + rpl = port_rpl; + lstatus32 = be32_to_cpu(rpl.u.info32.lstatus32_to_cbllen32); + + port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32); + mdio_addr = (lstatus32 & F_FW_PORT_CMD_MDIOCAP32) ? + (int)G_FW_PORT_CMD_MDIOADDR32(lstatus32) : -1; + pcaps = be32_to_cpu(port_rpl.u.info32.pcaps32); + acaps = be32_to_cpu(port_rpl.u.info32.acaps32); p->port_type = port_type; p->mdio_addr = mdio_addr;