From patchwork Wed Aug 7 15:09:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57540 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A201C31FC; Wed, 7 Aug 2019 17:09:52 +0200 (CEST) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by dpdk.org (Postfix) with ESMTP id 113BB2BD3 for ; Wed, 7 Aug 2019 17:09:41 +0200 (CEST) Received: by mail-wm1-f65.google.com with SMTP id 10so406583wmp.3 for ; Wed, 07 Aug 2019 08:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=gwekg01+K2ROk8rgN1MvmV23A7YN1+EmgHfiPl59XX7hcNbXvfGPMdDjNfv+eDue5h lhR0J79YQXRU+UAeOHyoD13KVXcBU3LGGzGJYMICCcBM8qXGIuSVJ22QyE3SEQ2lHUoT zjGm9YKOBvtjJyX/1q1B4THOeH7RdLDm24z/MTIajP3q4Izy3RQoe/+lV/0X6fDGbQQz 5rx9fe/T253O9WM/e8YTrGl2y/LRkOYQHtrYc3BPQjo2ZSAM272Z2SIjSk3IYM1CAa15 Pw2TbcpQRIImiorYPcZBVPRD9RssxVaG7AUky3f7jjOsBOTWcnGWCm2pX2GpvkYjIqjZ PQLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=eyb7lcdLuWlMO6a4FNDa5cItrINiiYMLSC6yOzfy5LBuWG70x7kwyxlyS5rLSXcVtI iIWkLl6d8LHKwLnUD1/cSyOXPSqtW1RWLkQgJ7c7NS/ncm5P0oLa52BGNAqVYsOhyd78 thvRGdTszY8TCSwN8LP5AIxnUpifANvnG5YVZgZnQbsxZKq0wYF6vUU1wL/RImD1rFaB wuJOfP86f6oJZWZd7lSfEm89ULzZz7i1Y6pt6wbc+YzOBgjo+3PBON7MTxW373Rkv9W1 vo4LfSxC2km0GpROexV8ICd+++aiezWJO1HyQ6OCMvIj47sTifO7XVSfkjQfLnsBXHFE /GDA== X-Gm-Message-State: APjAAAXI7Co9z9oit+ZtTD4Bt2HpElFbI+EAbpqF2ME7lRMMxR36LeQ4 1nYmE4ej/v8lsWkAcQNUuJeYiqmREA== X-Google-Smtp-Source: APXvYqwEJrDsRtlXic/pihT1LvQOuNSvUBdwLAQ7eaEumpGjsT3NSnEtESpH6aP9lts7opaP0X02og== X-Received: by 2002:a1c:9889:: with SMTP id a131mr437926wme.22.1565190580625; Wed, 07 Aug 2019 08:09:40 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:40 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:12 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 03/12] net/e1000: fix Tx descriptor status api (igb) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. Fixes: 978f8eea1719 ("net/e1000: implement descriptor status API (igb)") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/igb_rxtx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index c5606de5d7a0..c22118e59a21 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1835,14 +1835,15 @@ eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct igb_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; - desc = txq->tx_tail + offset; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + desc = txq->sw_ring[desc].last_id; status = &txq->tx_ring[desc].wb.status; if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD))