[v2,108/148] net/ice/base: add function to read Tx timestamp status register

Message ID b3cde9f50007e3b6fa4f0f9d10ba818ca79cee81.1718204529.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded
Delegated to: Bruce Richardson
Headers
Series Update net/ice base driver to latest upstream snapshot |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Anatoly Burakov June 12, 2024, 3:01 p.m. UTC
  From: Ian Stokes <ian.stokes@intel.com>

Both e822 and eth56g based hardware have a register indicating the status
of timestamps in the Tx timestamp memory bank. This register is used to
indicate which timestamps are currently valid. This is important because
the interrupt logic for these devices assumes that software will only read
registers with the valid bit set. If software does not follow this
practice, it can potentially cause hardware to stop reporting timestamp
interrupts.

Use of the status register value also allows software to avoid
unnecessarily reading timestamps which haven't yet been captured.

Add a helper function which reads the timestamp memory status registers for
these devices.

For e810, it is not clear if the hardware has an equivalent register.
Instead, implement a stub which just reports that all timestamps are valid.
This allows the timestamp tracking logic to use the same function for all
current device variants.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 113 ++++++++++++++++++++++++++++++
 drivers/net/ice/base/ice_ptp_hw.h |   6 ++
 2 files changed, 119 insertions(+)
  

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 938707afdf..7b1f462eee 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2374,6 +2374,33 @@  ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
 	return 0;
 }
 
+/**
+ * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to read from
+ * @tstamp_ready: contents of the Tx memory status register
+ *
+ * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
+ * the PHY are ready. A set bit means the corresponding timestamp is valid and
+ * ready to be captured from the PHY timestamp block.
+ */
+static int
+ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
+				   u64 *tstamp_ready)
+{
+	int err;
+
+	err = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
+					  tstamp_ready);
+	if (err) {
+		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
+			  port, err);
+		return err;
+	}
+
+	return 0;
+}
+
 #define ICE_DEVID_MASK 0xFFF8
 
 /**
@@ -4630,6 +4657,41 @@  ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
 	return 0;
 }
 
+/**
+ * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register
+ * @hw: pointer to the HW struct
+ * @quad: the timestamp quad to read from
+ * @tstamp_ready: contents of the Tx memory status register
+ *
+ * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
+ * the PHY are ready. A set bit means the corresponding timestamp is valid and
+ * ready to be captured from the PHY timestamp block.
+ */
+static int
+ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
+{
+	u32 hi, lo;
+	int err;
+
+	err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
+	if (err) {
+		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
+			  quad, err);
+		return err;
+	}
+
+	err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
+	if (err) {
+		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
+			  quad, err);
+		return err;
+	}
+
+	*tstamp_ready = (u64)hi << 32 | (u64)lo;
+
+	return 0;
+}
+
 /**
  * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
  * @hw: pointer to the HW struct
@@ -5168,6 +5230,22 @@  int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
 	return 0;
 }
 
+/**
+ * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to read
+ * @tstamp_ready: contents of the Tx memory status register
+ *
+ * E810 devices do not use a Tx memory status register. Instead simply
+ * indicate that all timestamps are currently ready.
+ */
+static int
+ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
+{
+	*tstamp_ready = 0xFFFFFFFFFFFFFFFF;
+	return 0;
+}
+
 /* E810T SMA functions
  *
  * The following functions operate specifically on E810T hardware and are used
@@ -6167,6 +6245,41 @@  int ice_ptp_init_phc(struct ice_hw *hw)
 	return err;
 }
 
+/**
+ * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
+ * @hw: pointer to the HW struct
+ * @block: the timestamp block to check
+ * @tstamp_ready: storage for the PHY Tx memory status information
+ *
+ * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
+ * which indicates which timestamps in the block may be captured. A set bit
+ * means the timestamp can be read. An unset bit means the timestamp is not
+ * ready and software should avoid reading the register.
+ */
+int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
+{
+	int err;
+
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		err = ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
+							 tstamp_ready);
+		break;
+	case ICE_PHY_E810:
+		err = ice_get_phy_tx_tstamp_ready_e810(hw, block,
+						       tstamp_ready);
+		break;
+	case ICE_PHY_E822:
+		err = ice_get_phy_tx_tstamp_ready_e822(hw, block,
+						       tstamp_ready);
+		break;
+	default:
+		err = ICE_ERR_NOT_SUPPORTED;
+	}
+
+	return err;
+}
+
 /**
  * refsync_pin_id_valid
  * @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index f20ce8cb0d..e11b47c528 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -146,8 +146,14 @@  void ice_ptp_reset_ts_memory(struct ice_hw *hw);
 int ice_ptp_init_phc(struct ice_hw *hw);
 bool refsync_pin_id_valid(struct ice_hw *hw, u8 id);
 int
+ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
+int
 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
 		     enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq);
+int
+ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
+int
+ice_ptp_read_phy_incval(struct ice_hw *hw, u8 port, u64 *incval);
 
 /* E822 family functions */
 int