From patchwork Mon Aug 30 16:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 97560 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CBB67A0547; Mon, 30 Aug 2021 18:15:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69D29410EA; Mon, 30 Aug 2021 18:15:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 408F6410E8 for ; Mon, 30 Aug 2021 18:15:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17UDOndM027947 for ; Mon, 30 Aug 2021 09:15:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=fWpgYgAhpG2yDk+yyLPhdAReufRUXUeSPWZZ8xuGkwk=; b=FJS7UlOf9kjB0eGmrZI7lJhBlsPtSm8K1jL1hj1+kXGcfrBArjyzccnLCGjjt3XuNrU+ Z41PbNtLU//e76XWA26ACsioVdLd2cI7RRQ7aHNbS0mMPMbPxbSvZ818qyOjQzpQoqQw aRb5SAAVKpURM7afAX6IAFq3ntQqdN0NGONKCjzYZF4Ji1KZ4nghgZzBkXThmIvQh7tn Ua9Ilo6IWkDUMpupwTEaQdJVa3UQ7mYIor9CNKYUDVHSvp3M4ogsSvLSXyV4CfajJIra ZkpV9/5kawUm8MAunXLV5De3xVIcQXM1AhAQt94T8kGwbRfsRV16fWxKw8q03Xjxz99u tw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3as06f8nda-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 30 Aug 2021 09:15:06 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 30 Aug 2021 09:15:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 30 Aug 2021 09:15:04 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 992FA3F7086; Mon, 30 Aug 2021 09:15:03 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , , "Pavan Nikhilesh" Date: Mon, 30 Aug 2021 21:44:46 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-GUID: 6UqbiEfahhRPTLrHSbZrp59pW-ha5Gvc X-Proofpoint-ORIG-GUID: 6UqbiEfahhRPTLrHSbZrp59pW-ha5Gvc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-08-30_05,2021-08-30_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2] event/cnxk: reduce max timer chunk pool cache size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reduced max chunk pool cache size from RTE_MEMPOOL_CACHE_MAX_SIZE(512) to 128. If chunk pool cache is empty, it gets filled during arm. Filling 512 entries at a time will fail arm if timeout is shorter. Fixes: 0e792433d051 ("event/cnxk: create and free timer adapter") Signed-off-by: Shijith Thotton --- v2: * Rebased. drivers/event/cnxk/cnxk_tim_evdev.c | 4 ++-- drivers/event/cnxk/cnxk_tim_evdev.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 9d40e336d7..c3e9dc508c 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -27,8 +27,8 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d", tim_ring->ring_id); - if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE) - cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; + if (cache_sz > CNXK_TIM_MAX_POOL_CACHE_SZ) + cache_sz = CNXK_TIM_MAX_POOL_CACHE_SZ; cache_sz = cache_sz != 0 ? cache_sz : 2; tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); if (!tim_ring->disable_npa) { diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index c369f6f472..9d95c45a7b 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -31,6 +31,7 @@ #define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1) #define CNXK_TIM_MIN_CHUNK_SLOTS (0x1) #define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE) +#define CNXK_TIM_MAX_POOL_CACHE_SZ (128) #define CN9K_TIM_MIN_TMO_TKS (256)