From patchwork Wed Aug 7 14:37:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57526 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C05473256; Wed, 7 Aug 2019 16:38:04 +0200 (CEST) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by dpdk.org (Postfix) with ESMTP id ADF122BCE for ; Wed, 7 Aug 2019 16:37:54 +0200 (CEST) Received: by mail-wm1-f66.google.com with SMTP id f17so294414wme.2 for ; Wed, 07 Aug 2019 07:37:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=aZmqPYsu57sWBTWUEE89iHO5N4VAKUs0E1rkakVYswo=; b=DmQJLSTv4/hnSs58bcrlCFsTpubwtW+fiRQ915ILlQ37Q4YUTERGEP5ufeJ2nwu1h3 ORhJ1QUMTFkL97BVf6T/ro7AoXOISWUrhCfHJkWnso7+Dxz8YCOY6iaMwwDt5rox98KA 9YCQy746PyKWy3iII0k8DnqG08OxU11IRLA9CYdKB7T9B/PonWntQRs1nL7x4ioiywNe jRl92LZokfrrmkmxmjsJFJfM7WPpXtFd+TwmiUGwOfQ2oDgoNTpJ5428hDjCiSjHkNRK 0zRlNTNG8mIIJckWBnT3pRc/av3/qGbWLRxvqv83Ys29NneFTS1KYw+CL3A442RUHwrL KSuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=aZmqPYsu57sWBTWUEE89iHO5N4VAKUs0E1rkakVYswo=; b=fA5s5t8OyMJ++fTMqoCzcg7YAmTjQskz4GOA+snsQaojKIZbw7kwJetUJuM25Db3wh FAT7xsArIkz3qixvClbIC9klkH7hG4Qv3ENW4/gBThxxxVw3WWFIYjL4yq6gzMUxd3+M zCCGhyBNyN3cgMayNo5zvbr3RL7EQz32jbJPb+qOVPGgtdSWYUXwQ/bi6JeKOMBPynLX mEZrC+HeZlv6/YusAbV2SogHs0B6gfV2o04wai2oq+PLlc61/sDkqFSBZ1ULb0rc7iRo YzMmZkR0cnFauHme4PP8Eu0/ghWm8InX7Xy5iDTQbX3fGOvWKOAl2nFzxGtMMiOJ04PI NpoQ== X-Gm-Message-State: APjAAAWbrOK93BiQExPFlUeYJn915CfL9yoDAIU1Lq7jhpHTtPrsmUz0 /hDymN74/eWdW3Wupf1fqGyia2GHsA== X-Google-Smtp-Source: APXvYqxUPv/FKVcoaTSBhx80MB+k7WO1GLPc3MwXFMrXxb+mYCaz31IRd20Ivlg/V1niK7OtKF3Fog== X-Received: by 2002:a1c:6c14:: with SMTP id h20mr314226wmc.168.1565188674253; Wed, 07 Aug 2019 07:37:54 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id 2sm133441211wrn.29.2019.08.07.07.37.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 07:37:53 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 16:37:22 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 03/12] net/e1000: fix Tx descriptor status api (igb) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. Fixes: 978f8eea1719 ("net/e1000: implement descriptor status API (igb)") Cc: stable at dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/igb_rxtx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index c5606de5d7a0..c22118e59a21 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1835,14 +1835,15 @@ eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct igb_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; - desc = txq->tx_tail + offset; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + desc = txq->sw_ring[desc].last_id; status = &txq->tx_ring[desc].wb.status; if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD))