From patchwork Thu Jun 15 15:48:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Mazarguil X-Patchwork-Id: 25357 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 177452BC3; Thu, 15 Jun 2017 17:49:10 +0200 (CEST) Received: from mail-wr0-f174.google.com (mail-wr0-f174.google.com [209.85.128.174]) by dpdk.org (Postfix) with ESMTP id 152C62BBB for ; Thu, 15 Jun 2017 17:49:09 +0200 (CEST) Received: by mail-wr0-f174.google.com with SMTP id 77so24723632wrb.1 for ; Thu, 15 Jun 2017 08:49:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2Az8hdYeSNWZ1V+skSLISlGWi0PL+Iz9Pa1Zs3RnsO4=; b=SIWFO8ihCQRw93qShtNZyW9bYo2tuAaE+GKgUbhEGW/WZgKTqUveIpqsnroinU/5tt wcOe3V8C4zvdhcUxHudvFTdqjt1X92fdIiUIRhuFRHOhUCW3hRm0rJ7Q+37W6LI61UKJ 08Tnh25YGrjMA/YaocY2ugohhYetVrAXLLNNdZYtIEpFMeojc1FGsRDEiH2zmgpBa46v it5CcBqDha5BIDTQHeMt6cK9FKE5CuDICpVqBKyQ80nv/IYgRDsRp0GbX3HFUWVje4Se zyafat0YlNRP3a2xfx8fEmc1cP3IEJfAFC4KeBw4iyjbkbX/vGLpkegntQH6v9aNa/BX oEug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2Az8hdYeSNWZ1V+skSLISlGWi0PL+Iz9Pa1Zs3RnsO4=; b=kE+hozqMgpmPC9akXFrDY2dqQzTmyCqOX0lmGM2WaIGi50oBtygdofUGGl0BDVMOfn RQQFd9NXJj9MJPDTLa/YPa2Hr6yyldpQVpy15Muad0VYw0eBqamJrrK0T1QtrUFGwPDC BV1hChTdnQEQTrli1eJcsGVDpKPPx7ew344LkN7F9jKBGfyfi4wFtB3+Nl2bboE6N0IV muJeItV303FrUzgdv7PeDj7np3Wl0V0U7AifvTS4NTaZoTtTW0JMoR8Fc6pr3bewMgkB UCbGbKOySXJt1FGFMUH3Pwh9fQ6xfgXhN7iYoVeXx8iaHMeRWMTB7ksvUGs8rLthvFIH xNEg== X-Gm-Message-State: AKS2vOyZQpT4tq+DthrNmHakYl/MM90BIBDrGfZmUuKwrz/GK2cRnaNk wP2z7X2895HQnHOw2rY= X-Received: by 10.223.134.34 with SMTP id 31mr4466170wrv.96.1497541748044; Thu, 15 Jun 2017 08:49:08 -0700 (PDT) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id w17sm475396wra.34.2017.06.15.08.49.06 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 15 Jun 2017 08:49:07 -0700 (PDT) From: Adrien Mazarguil To: dev@dpdk.org Cc: Thomas Monjalon , Nelio Laranjeiro Date: Thu, 15 Jun 2017 17:48:57 +0200 Message-Id: <7add1fdc469338ab1071ba786b0a5b0f9ec2c6d5.1497541557.git.adrien.mazarguil@6wind.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <840342851720fc237214aeb30d38565615293b58.1495101988.git.adrien.mazarguil@6wind.com> References: <840342851720fc237214aeb30d38565615293b58.1495101988.git.adrien.mazarguil@6wind.com> Subject: [dpdk-dev] [PATCH v2 1/3] eal: introduce big and little endian types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nelio Laranjeiro This commit introduces new rte_{le,be}{16,32,64}_t types and updates rte_{le,be,cpu}_to_{le,be,cpu}_*() accordingly. These types are added for documentation purposes, mainly to clarify the byte ordering to use for storage when not CPU order. Doing so eliminates uncertainty and conversion mistakes. Signed-off-by: Nelio Laranjeiro Signed-off-by: Adrien Mazarguil --- This is a rehash of Nelio's original patch [1] that drops all changes to protocol header structures and only focuses on adding these new types for documentation purposes. [1] http://dpdk.org/ml/archives/dev/2016-November/050060.html --- .../common/include/generic/rte_byteorder.h | 38 +++++++++++++------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/lib/librte_eal/common/include/generic/rte_byteorder.h b/lib/librte_eal/common/include/generic/rte_byteorder.h index e00bccb..df8cc84 100644 --- a/lib/librte_eal/common/include/generic/rte_byteorder.h +++ b/lib/librte_eal/common/include/generic/rte_byteorder.h @@ -76,6 +76,20 @@ #endif /* + * The following types should be used when handling values according to a + * specific byte ordering, which may differ from that of the host CPU. + * + * Libraries, public APIs and applications are encouraged to use them for + * documentation purposes. + */ +typedef uint16_t rte_be16_t; /**< 16-bit big-endian value. */ +typedef uint32_t rte_be32_t; /**< 32-bit big-endian value. */ +typedef uint64_t rte_be64_t; /**< 64-bit big-endian value. */ +typedef uint16_t rte_le16_t; /**< 16-bit little-endian value. */ +typedef uint32_t rte_le32_t; /**< 32-bit little-endian value. */ +typedef uint64_t rte_le64_t; /**< 64-bit little-endian value. */ + +/* * An internal function to swap bytes in a 16-bit value. * * It is used by rte_bswap16() when the value is constant. Do not use @@ -143,65 +157,65 @@ static uint64_t rte_bswap64(uint64_t x); /** * Convert a 16-bit value from CPU order to little endian. */ -static uint16_t rte_cpu_to_le_16(uint16_t x); +static rte_le16_t rte_cpu_to_le_16(uint16_t x); /** * Convert a 32-bit value from CPU order to little endian. */ -static uint32_t rte_cpu_to_le_32(uint32_t x); +static rte_le32_t rte_cpu_to_le_32(uint32_t x); /** * Convert a 64-bit value from CPU order to little endian. */ -static uint64_t rte_cpu_to_le_64(uint64_t x); +static rte_le64_t rte_cpu_to_le_64(uint64_t x); /** * Convert a 16-bit value from CPU order to big endian. */ -static uint16_t rte_cpu_to_be_16(uint16_t x); +static rte_be16_t rte_cpu_to_be_16(uint16_t x); /** * Convert a 32-bit value from CPU order to big endian. */ -static uint32_t rte_cpu_to_be_32(uint32_t x); +static rte_be32_t rte_cpu_to_be_32(uint32_t x); /** * Convert a 64-bit value from CPU order to big endian. */ -static uint64_t rte_cpu_to_be_64(uint64_t x); +static rte_be64_t rte_cpu_to_be_64(uint64_t x); /** * Convert a 16-bit value from little endian to CPU order. */ -static uint16_t rte_le_to_cpu_16(uint16_t x); +static uint16_t rte_le_to_cpu_16(rte_le16_t x); /** * Convert a 32-bit value from little endian to CPU order. */ -static uint32_t rte_le_to_cpu_32(uint32_t x); +static uint32_t rte_le_to_cpu_32(rte_le32_t x); /** * Convert a 64-bit value from little endian to CPU order. */ -static uint64_t rte_le_to_cpu_64(uint64_t x); +static uint64_t rte_le_to_cpu_64(rte_le64_t x); /** * Convert a 16-bit value from big endian to CPU order. */ -static uint16_t rte_be_to_cpu_16(uint16_t x); +static uint16_t rte_be_to_cpu_16(rte_be16_t x); /** * Convert a 32-bit value from big endian to CPU order. */ -static uint32_t rte_be_to_cpu_32(uint32_t x); +static uint32_t rte_be_to_cpu_32(rte_be32_t x); /** * Convert a 64-bit value from big endian to CPU order. */ -static uint64_t rte_be_to_cpu_64(uint64_t x); +static uint64_t rte_be_to_cpu_64(rte_be64_t x); #endif /* __DOXYGEN__ */