From patchwork Thu Aug 8 08:22:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57558 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BA9F42BF1; Thu, 8 Aug 2019 10:23:02 +0200 (CEST) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by dpdk.org (Postfix) with ESMTP id BE53A2B87 for ; Thu, 8 Aug 2019 10:22:54 +0200 (CEST) Received: by mail-wr1-f68.google.com with SMTP id k2so8137890wrq.2 for ; Thu, 08 Aug 2019 01:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=XY1n8fq7qCYaBAKR6OUoWyiUnO8h3/Ju2Yd2A+lwyf1+3MoHEVlb6aRqg4tilCiA5V FHkWfjRDNtNXdTL7QS1A/DPflmu6oyUFVz3Xm+QEiqwh8+l7Hx1S9i8rsMnisEYt48+b FhP7X2XgaZn1fgABsd+I5xKqxrni2W0F8fXE4JuRnFiIGc0yvjKOZENuK4YicgxIN+BS BpYrW5kObLHArCTy++goonYL7jDBaWxW/QeUlNW66sIQ8BJUWZWy6mAL/FhpoirkmSET PiO1KSVMvUpCxCl2okmMNgPMsfd6/OvQ9sxMaa5UD1uQjZjcUdCLW6fcgoAwHEc5d21M y3tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=fLip2T5sJPQirhzNx5kakqyi0DT8TmELrfDtexSGVbPdnvMDK7KcUzATHbBgaveEoA 9SGtL5UOntcY+6MQhI79f72m8wot0eLRqQbJ1sTy3pZHUCcgjMJnl5BLkB7ksyyARMYQ 7AIBKUPSQDrCF2JdL1zvPOX//bIED6cfcnLwTnJpHmScjIREzzDKTCmkPgL8UnsZDjN7 hFUqSQf0fpAvIn31nX8Wuegbnher+8YzHUE6xjCgbtcX5IaUGKuNKdaQxUD5qRFlPq/7 xAzsW9BwbGbURMftmTpvqSDAg4wh7RrLzpx2gPpNteHVvpdd4jQbycJcRgbkuuP9hRLn h0Iw== X-Gm-Message-State: APjAAAXKNdJ3DKrAT+sFTSc22Fjycwsm1Ju8+ron6E3AOYL/xFSaAUsB h05jX4vZSqUhqmREJ7qcOAfpKiHBew== X-Google-Smtp-Source: APXvYqzxWFl9WIRxRdqmS8o3HxjO1MUP6qn5so92aYW1kf20LaYgqYRGa9AhuPH9YKA03E7+0BiUpA== X-Received: by 2002:a05:6000:152:: with SMTP id r18mr5161056wrx.41.1565252574335; Thu, 08 Aug 2019 01:22:54 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id t13sm111437018wrr.0.2019.08.08.01.22.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Aug 2019 01:22:53 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Thu, 8 Aug 2019 10:22:08 +0200 Message-Id: <6fa4aa21b2ab176fcc767272f8ab3dc59907d5a1.1565252336.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V3 03/12] net/e1000: fix Tx descriptor status api (igb) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. Fixes: 978f8eea1719 ("net/e1000: implement descriptor status API (igb)") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/igb_rxtx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index c5606de5d7a0..c22118e59a21 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1835,14 +1835,15 @@ eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct igb_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; - desc = txq->tx_tail + offset; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + desc = txq->sw_ring[desc].last_id; status = &txq->tx_ring[desc].wb.status; if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD))