diff mbox series

[1/2] net/mlx5/hws: recognize IPIP in definer layer

Message ID 20250620104203.261435-2-junfengg@nvidia.com (mailing list archive)
State Accepted
Delegated to: Raslan Darawsheh
Headers
Series Support IPIP Tunnel in NT2HWS and HWS |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/aws-unit-testing success Unit Testing PASS

Commit Message

Junfeng Guo June 20, 2025, 10:42 a.m. UTC 
Definers are HW objects that are used for matching, rte items are
translated to definers, each definer holds the fields and bit-masks
used for HW flow matching.

This patch recognize IP-in-IP tunnel type in definer layer, including
the following combinations:
 - IPv4 over IPv4
 - IPv4 over IPv6
 - IPv6 over IPv4
 - IPv6 over IPv6

Signed-off-by: Junfeng Guo <junfengg@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 9c11d6c2cb..7464d95373 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -3322,11 +3322,21 @@  mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
 				(MLX5_FLOW_LAYER_OUTER_VLAN | MLX5_FLOW_LAYER_OUTER_L2);
 			break;
 		case RTE_FLOW_ITEM_TYPE_IPV4:
+			if (cd.last_item == RTE_FLOW_ITEM_TYPE_IPV4 ||
+			    cd.last_item == RTE_FLOW_ITEM_TYPE_IPV6) {
+				cd.tunnel = true;
+				item_flags |= MLX5_FLOW_LAYER_IPIP;
+			}
 			ret = mlx5dr_definer_conv_item_ipv4(&cd, items, i);
 			item_flags |= cd.tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
 						  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
 			break;
 		case RTE_FLOW_ITEM_TYPE_IPV6:
+			if (cd.last_item == RTE_FLOW_ITEM_TYPE_IPV4 ||
+			    cd.last_item == RTE_FLOW_ITEM_TYPE_IPV6) {
+				cd.tunnel = true;
+				item_flags |= MLX5_FLOW_LAYER_IPIP;
+			}
 			ret = mlx5dr_definer_conv_item_ipv6(&cd, items, i);
 			item_flags |= cd.tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
 						  MLX5_FLOW_LAYER_OUTER_L3_IPV6;