net/cnxk: support ESP based RSS hashing
Checks
Commit Message
From: Satheesh Paul <psatheesh@marvell.com>
Support ESP based RSS hashing.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
---
drivers/common/cnxk/roc_mbox.h | 1 +
drivers/net/cnxk/cnxk_ethdev.c | 3 ++
drivers/net/cnxk/cnxk_ethdev.h | 67 ++++++++++++++++------------------
3 files changed, 36 insertions(+), 35 deletions(-)
Comments
> -----Original Message-----
> From: psatheesh@marvell.com <psatheesh@marvell.com>
> Sent: Wednesday, April 2, 2025 1:55 PM
> To: Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>; Kiran Kumar
> Kokkilagadda <kirankumark@marvell.com>; Sunil Kumar Kori
> <skori@marvell.com>; Satha Koteswara Rao Kottidi
> <skoteshwar@marvell.com>; Harman Kalra <hkalra@marvell.com>
> Cc: dev@dpdk.org; Satheesh Paul Antonysamy <psatheesh@marvell.com>
> Subject: [EXTERNAL] [dpdk-dev] [PATCH ] net/cnxk: support ESP based RSS
> hashing
>
> From: Satheesh Paul <psatheesh@ marvell. com> Support ESP based RSS
> hashing. Signed-off-by: Satheesh Paul <psatheesh@ marvell. com> Reviewed-by:
> Kiran Kumar K <kirankumark@ marvell. com> ---
> drivers/common/cnxk/roc_mbox. h | 1 + drivers/net/cnxk/cnxk_ethdev. c
>
> From: Satheesh Paul <psatheesh@marvell.com>
>
> Support ESP based RSS hashing.
>
> Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
> Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Applied to dpdk-next-net-mrvl/for-main. Thanks
@@ -1777,6 +1777,7 @@ struct nix_rss_flowkey_cfg {
#define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
#define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
#define FLOW_KEY_TYPE_VLAN BIT(20)
+#define FLOW_KEY_TYPE_ESP BIT(23)
#define FLOW_KEY_TYPE_L4_DST BIT(28)
#define FLOW_KEY_TYPE_L4_SRC BIT(29)
#define FLOW_KEY_TYPE_L3_DST BIT(30)
@@ -935,6 +935,9 @@ cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
if (ethdev_rss & RTE_ETH_RSS_GTPU)
flowkey_cfg |= FLOW_KEY_TYPE_GTPU;
+ if (ethdev_rss & RTE_ETH_RSS_ESP)
+ flowkey_cfg |= FLOW_KEY_TYPE_ESP;
+
return flowkey_cfg;
}
@@ -49,47 +49,44 @@
/* LPB & SPB */
#define CNXK_NIX_NUM_POOLS_MAX 2
-#define CNXK_NIX_DEF_SQ_COUNT 512
-
-#define CNXK_NIX_RSS_L3_L4_SRC_DST \
- (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
- RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
-
-#define CNXK_NIX_RSS_OFFLOAD \
- (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | \
- RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL | \
- RTE_ETH_RSS_L2_PAYLOAD | CNXK_NIX_RSS_L3_L4_SRC_DST | \
- RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN)
-
-#define CNXK_NIX_TX_OFFLOAD_CAPA \
- (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
- RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
- RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
- RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
- RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | \
- RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \
- RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
+#define CNXK_NIX_DEF_SQ_COUNT 512
+
+#define CNXK_NIX_RSS_L3_L4_SRC_DST \
+ (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | RTE_ETH_RSS_L4_SRC_ONLY | \
+ RTE_ETH_RSS_L4_DST_ONLY)
+
+#define CNXK_NIX_RSS_OFFLOAD \
+ (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \
+ RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL | RTE_ETH_RSS_L2_PAYLOAD | \
+ CNXK_NIX_RSS_L3_L4_SRC_DST | RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN | \
+ RTE_ETH_RSS_ESP)
+
+#define CNXK_NIX_TX_OFFLOAD_CAPA \
+ (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
+ RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
+ RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
+ RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | \
+ RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \
+ RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_SECURITY)
-#define CNXK_NIX_RX_OFFLOAD_CAPA \
- (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
- RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \
- RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \
- RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
+#define CNXK_NIX_RX_OFFLOAD_CAPA \
+ (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
+ RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \
+ RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \
+ RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
RTE_ETH_RX_OFFLOAD_SECURITY)
-#define RSS_IPV4_ENABLE \
- (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \
- RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
- RTE_ETH_RSS_NONFRAG_IPV4_SCTP)
+#define RSS_IPV4_ENABLE \
+ (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_SCTP)
-#define RSS_IPV6_ENABLE \
- (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | \
- RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
- RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
+#define RSS_IPV6_ENABLE \
+ (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
-#define RSS_IPV6_EX_ENABLE \
- (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX)
+#define RSS_IPV6_EX_ENABLE (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX)
#define RSS_MAX_LEVELS 3